Total properties:
33
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09099464
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Filing Dt:
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06/18/1998
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Title:
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REGULATED DRAM CELL PLATE AND PRECHARGE VOLTAGE GENERATOR
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09106755
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Filing Dt:
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06/30/1998
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Title:
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PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09129878
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Filing Dt:
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08/06/1998
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Publication #:
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Pub Dt:
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11/15/2001
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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Patent #:
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Issue Dt:
|
11/09/1999
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Application #:
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09163341
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Filing Dt:
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09/30/1998
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Title:
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BI-DIRECTIONAL DATA BUS SCHEME WITH OPTIMIZED READ AND WRITE CHARACTERS
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09182494
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Filing Dt:
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10/30/1998
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Publication #:
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Pub Dt:
|
11/29/2001
| | | | |
Title:
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HIGH BANDWIDTH MEMORY INTERFACE
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Patent #:
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Issue Dt:
|
10/24/2000
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Application #:
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09182495
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Filing Dt:
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10/30/1998
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Title:
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COLUMN REDUNDANCY CIRCUIT WITH REDUCED SIGNAL PATH DELAY
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Patent #:
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Issue Dt:
|
10/17/2000
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Application #:
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09364181
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Filing Dt:
|
07/29/1999
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Title:
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BI-DIRECTIONAL DATA BUS SCHEME WITH OPTIMIZED READ AND WRITE CHARACTERS
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Patent #:
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Issue Dt:
|
11/20/2001
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Application #:
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09533128
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Filing Dt:
|
03/23/2000
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Title:
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Dynamic content addressable memory cell
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Patent #:
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Issue Dt:
|
08/27/2002
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Application #:
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09562024
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Filing Dt:
|
05/01/2000
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Title:
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FREQUENCY-DOUBLING DELAY LOCKED LOOP
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Patent #:
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|
Issue Dt:
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11/19/2002
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Application #:
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09977982
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Filing Dt:
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10/17/2001
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Publication #:
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Pub Dt:
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04/18/2002
| | | | |
Title:
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DYNAMIC CONTENT ADDRESSABLE MEMORY CELL
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|
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10227547
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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03/06/2003
| | | | |
Title:
|
FREQUENCY-DOUBLING DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
|
08/17/2004
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Application #:
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10247821
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Filing Dt:
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09/20/2002
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Publication #:
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Pub Dt:
|
04/03/2003
| | | | |
Title:
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HIGH BANDWIDTH MEMORY INTERFACE
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Patent #:
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Issue Dt:
|
08/03/2004
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Application #:
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10290317
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Filing Dt:
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11/08/2002
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Publication #:
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Pub Dt:
|
04/03/2003
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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|
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Patent #:
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Issue Dt:
|
03/09/2010
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Application #:
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10614558
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Filing Dt:
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07/07/2003
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Publication #:
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Pub Dt:
|
01/15/2004
| | | | |
Title:
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METHOD AND APPARATUS FOR PROVIDING A PACKET BUFFER RANDOM ACCESS MEMORY
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|
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10855968
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Filing Dt:
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05/28/2004
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Publication #:
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Pub Dt:
|
02/10/2005
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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Patent #:
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|
Issue Dt:
|
04/01/2008
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Application #:
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10880432
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Filing Dt:
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06/29/2004
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Publication #:
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|
Pub Dt:
|
02/10/2005
| | | | |
Title:
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LINK AGGREGATION
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|
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Patent #:
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|
Issue Dt:
|
11/20/2007
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Application #:
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10919491
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Filing Dt:
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08/17/2004
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Publication #:
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|
Pub Dt:
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04/14/2005
| | | | |
Title:
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HIGH BANDWIDTH MEMORY INTERFACE
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Patent #:
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|
Issue Dt:
|
11/25/2008
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Application #:
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11495212
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
|
FREQUENCY-DOUBLING DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11673834
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Filing Dt:
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02/12/2007
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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11906756
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Filing Dt:
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10/03/2007
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Publication #:
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Pub Dt:
|
03/13/2008
| | | | |
Title:
|
HIGH BANDWIDTH MEMORY INTERFACE
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Patent #:
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Issue Dt:
|
07/27/2010
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Application #:
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11978896
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Filing Dt:
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10/30/2007
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Publication #:
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Pub Dt:
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05/22/2008
| | | | |
Title:
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APPARATUSES FOR SYNCHRONOUS TRANSFER OF INFORMATION
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Patent #:
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Issue Dt:
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08/21/2012
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Application #:
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11978988
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Filing Dt:
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10/30/2007
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Publication #:
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Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH BANDWIDTH MEMORY INTERFACE
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Patent #:
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|
Issue Dt:
|
02/15/2011
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Application #:
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12026813
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Filing Dt:
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02/06/2008
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Publication #:
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Pub Dt:
|
06/19/2008
| | | | |
Title:
|
PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME
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Patent #:
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|
Issue Dt:
|
06/29/2010
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Application #:
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12284763
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Filing Dt:
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09/25/2008
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Publication #:
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Pub Dt:
|
02/12/2009
| | | | |
Title:
|
FREQUENCY-DOUBLING DELAY LOCKED LOOP
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Patent #:
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|
Issue Dt:
|
01/04/2011
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Application #:
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12371255
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Filing Dt:
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02/13/2009
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Publication #:
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|
Pub Dt:
|
07/09/2009
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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12773531
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Filing Dt:
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05/04/2010
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12784157
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Filing Dt:
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05/20/2010
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Publication #:
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Pub Dt:
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09/09/2010
| | | | |
Title:
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FREQUENCY-DOUBLING DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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13049487
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Filing Dt:
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03/16/2011
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Publication #:
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Pub Dt:
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08/18/2011
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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13327154
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/07/2012
| | | | |
Title:
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SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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13607015
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Filing Dt:
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09/07/2012
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Publication #:
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Pub Dt:
|
01/17/2013
| | | | |
Title:
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FREQUENCY-DOUBLING DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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13741994
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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05/30/2013
| | | | |
Title:
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PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13743794
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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HIGH BANDWIDTH MEMORY INTERFACE
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Patent #:
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Issue Dt:
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06/17/2014
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Application #:
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14023047
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Filing Dt:
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09/10/2013
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Publication #:
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Pub Dt:
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01/09/2014
| | | | |
Title:
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FREQUENCY-DOUBLING DELAY LOCKED LOOP
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