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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054372/0194			Pages:	75
		Recorded:	11/10/2020
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 68

Patent #:	6410967	Issue Dt:	06/25/2002	Application #:	09173273	Filing Dt:	10/15/1998
Title:	TRANSISTOR HAVING ENHANCED METAL SILICIDE AND A SELF-ALIGNED GATE ELECTRODE

Patent #:	6210999	Issue Dt:	04/03/2001	Application #:	09205047	Filing Dt:	12/04/1998
Title:	METHOD AND TEST STRUCTURE FOR LOW-TEMPERATURE INTEGRATION OF HIGH DIELECTRIC CONSTANT GATE DIELECTRICS INTO SELF-ALIGNED SEMICONDUCTOR DEVICES

Patent #:	7071101	Issue Dt:	07/04/2006	Application #:	09208325	Filing Dt:	12/09/1998
Title:	SACRIFICIAL TIN ARC LAYER FOR INCREASED PAD ETCH THROUGHPUT

Patent #:	6380091	Issue Dt:	04/30/2002	Application #:	09238050	Filing Dt:	01/27/1999
Title:	DUAL DAMASCENE ARRANGEMENT FOR METAL INTERCONNECTION WITH OXIDE DIELECTRIC LAYER AND LOW K DIELECTRIC CONSTANT LAYER

Patent #:	6265253	Issue Dt:	07/24/2001	Application #:	09305098	Filing Dt:	05/05/1999
Title:	ALUMINUM DISPOSABLE SPACER TO REDUCE MASK COUNT IN CMOS TRANSISTOR FORMATION

Patent #:	6127259	Issue Dt:	10/03/2000	Application #:	09372443	Filing Dt:	08/11/1999
Title:	PHOSPHORIC ACID PROCESS FOR REMOVAL OF CONTACT BARC LAYER

Patent #:	6358803	Issue Dt:	03/19/2002	Application #:	09489369	Filing Dt:	01/21/2000
Title:	Method of fabricating a deep source/drain

Patent #:	6310822	Issue Dt:	10/30/2001	Application #:	09498739	Filing Dt:	02/07/2000
Title:	Delay Locking High Speed Clock Synchronization Method And Circuit

Patent #:	6314030	Issue Dt:	11/06/2001	Application #:	09594442	Filing Dt:	06/14/2000
Title:	Semiconductor memory having segmented row repair

Patent #:	6724051	Issue Dt:	04/20/2004	Application #:	09679877	Filing Dt:	10/05/2000
Title:	NICKEL SILICIDE PROCESS USING NON-REACTIVE SPACER

Patent #:	6524947	Issue Dt:	02/25/2003	Application #:	09774800	Filing Dt:	02/01/2001
Title:	SLOTTED TRENCH DUAL INLAID STRUCTURE AND METHOD OF FORMING THEREOF

Patent #:	6531347	Issue Dt:	03/11/2003	Application #:	09776713	Filing Dt:	02/06/2001
Title:	RECESSED SOURCE DRAINS TO REDUCE FRINGING CAPACITANCE

Patent #:	6365450	Issue Dt:	04/02/2002	Application #:	09809706	Filing Dt:	03/15/2001
Title:	FABRICATION OF P-CHANNEL FIELD EFFECT TRANSISTOR WITH MINIMIZED DEGRADATION OF METAL OXIDE GATE

Patent #:	6518154	Issue Dt:	02/11/2003	Application #:	09813310	Filing Dt:	03/21/2001
Title:	METHOD OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENTLY COMPOSED METAL-BASED GATE ELECTRODES

Patent #:	6518646	Issue Dt:	02/11/2003	Application #:	09819615	Filing Dt:	03/29/2001
Title:	SEMICONDUCTOR DEVICE WITH VARIABLE COMPOSITION LOW-K INTER-LAYER DIELECTRIC AND METHOD OF MAKING

Patent #:	6686248	Issue Dt:	02/03/2004	Application #:	09825658	Filing Dt:	04/03/2001
Title:	METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A MOS TRANSISTOR WITH A HIGH DIELECTRIC CONSTANT MATERIAL

Patent #:	6635409	Issue Dt:	10/21/2003	Application #:	09902568	Filing Dt:	07/12/2001
Title:	METHOD OF STRENGTHENING PHOTORESIST TO PREVENT PATTERN COLLAPSE

Patent #:	6462416	Issue Dt:	10/08/2002	Application #:	09905469	Filing Dt:	07/13/2001
Title:	GRADATED BARRIER LAYER IN INTEGRATED CIRCUIT INTERCONNECTS

Patent #:	6442084	Issue Dt:	08/27/2002	Application #:	09928404	Filing Dt:	08/14/2001
Publication #:	US20010053101	Pub Dt:	12/20/2001
Title:	SEMICONDUCTOR MEMORY HAVING SEGMENTED ROW REPAIR

Patent #:	6500754	Issue Dt:	12/31/2002	Application #:	09999661	Filing Dt:	10/31/2001
Title:	ANNEAL HILLOCK SUPPRESSION METHOD IN INTEGRATED CIRCUIT INTERCONNECTS

Patent #:	6821713	Issue Dt:	11/23/2004	Application #:	10085242	Filing Dt:	02/27/2002
Title:	METHOD FOR LATERAL TRIMMING OF SPACERS

Patent #:	6587383	Issue Dt:	07/01/2003	Application #:	10100856	Filing Dt:	03/19/2002
Title:	ERASE BLOCK ARCHITECTURE FOR NON-VOLATILE MEMORY

Patent #:	6895474	Issue Dt:	05/17/2005	Application #:	10133386	Filing Dt:	04/29/2002
Publication #:	US20030204674	Pub Dt:	10/30/2003
Title:	SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE

Patent #:	7089438	Issue Dt:	08/08/2006	Application #:	10179882	Filing Dt:	06/25/2002
Publication #:	US20030235103	Pub Dt:	12/25/2003
Title:	CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Patent #:	7123512	Issue Dt:	10/17/2006	Application #:	10199725	Filing Dt:	07/19/2002
Publication #:	US20040015674	Pub Dt:	01/22/2004
Title:	CONTIGUOUS BLOCK ADDRESSING SCHEME

Patent #:	6573172	Issue Dt:	06/03/2003	Application #:	10244439	Filing Dt:	09/16/2002
Title:	METHODS FOR IMPROVING CARRIER MOBILITY OF PMOS AND NMOS DEVICES

Patent #:	6611029	Issue Dt:	08/26/2003	Application #:	10290158	Filing Dt:	11/08/2002
Title:	DOUBLE GATE SEMICONDUCTOR DEVICE HAVING SEPARATE GATES

Patent #:	6936480	Issue Dt:	08/30/2005	Application #:	10304573	Filing Dt:	11/26/2002
Publication #:	US20040023490	Pub Dt:	02/05/2004
Title:	METHOD OF CONTROLLING THE CHEMICAL MECHANICAL POLISHING OF STACKED LAYERS HAVING A SURFACE TOPOLOGY

Patent #:	7022599	Issue Dt:	04/04/2006	Application #:	10306335	Filing Dt:	11/27/2002
Publication #:	US20030119302	Pub Dt:	06/26/2003
Title:	METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

Patent #:	6892318	Issue Dt:	05/10/2005	Application #:	10375994	Filing Dt:	02/27/2003
Publication #:	US20030154422	Pub Dt:	08/14/2003
Title:	METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY

Patent #:	6724663	Issue Dt:	04/20/2004	Application #:	10376936	Filing Dt:	02/28/2003
Publication #:	US20030179624	Pub Dt:	09/25/2003
Title:	ERASE BLOCK ARCHITECTURE FOR NON-VOLATILE MEMORY

Patent #:	6861350	Issue Dt:	03/01/2005	Application #:	10464508	Filing Dt:	06/19/2003
Title:	METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE COMPRISING SILICON-RICH TASIN METAL GATE ELECTRODE

Patent #:	6812119	Issue Dt:	11/02/2004	Application #:	10614052	Filing Dt:	07/08/2003
Title:	NARROW FINS BY OXIDATION IN DOUBLE-GATE FINFET

Patent #:	7034361	Issue Dt:	04/25/2006	Application #:	10653234	Filing Dt:	09/03/2003
Title:	NARROW BODY RAISED SOURCE/DRAIN METAL GATE MOSFET

Patent #:	7141502	Issue Dt:	11/28/2006	Application #:	10673597	Filing Dt:	09/29/2003
Title:	SLURRY-LESS POLISHING FOR REMOVAL OF EXCESS INTERCONNECT MATERIAL DURING FABRICATION OF A SILICON INTEGRATED CIRCUIT

Patent #:	7081966	Issue Dt:	07/25/2006	Application #:	10731764	Filing Dt:	12/09/2003
Publication #:	US20040120005	Pub Dt:	06/24/2004
Title:	DEMONSTRATION CONTROL ADJUNCT DEVICE FOR PRINTERS

Patent #:	7005358	Issue Dt:	02/28/2006	Application #:	10786401	Filing Dt:	02/25/2004
Publication #:	US20050026380	Pub Dt:	02/03/2005
Title:	TECHNIQUE FOR FORMING RECESSED SIDEWALL SPACERS FOR A POLYSILICON LINE

Patent #:	7031219	Issue Dt:	04/18/2006	Application #:	10861157	Filing Dt:	06/04/2004
Publication #:	US20050270880	Pub Dt:	12/08/2005
Title:	INTERNAL POWER MANAGEMENT SCHEME FOR A MEMORY CHIP IN DEEP POWER DOWN MODE

Patent #:	7091097	Issue Dt:	08/15/2006	Application #:	10933424	Filing Dt:	09/03/2004
Title:	END-OF-RANGE DEFECT MINIMIZATION IN SEMICONDUCTOR DEVICE

Patent #:	6981100	Issue Dt:	12/27/2005	Application #:	10972324	Filing Dt:	10/26/2004
Publication #:	US20050083758	Pub Dt:	04/21/2005
Title:	SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE

Patent #:	7154780	Issue Dt:	12/26/2006	Application #:	11206529	Filing Dt:	08/18/2005
Publication #:	US20050276130	Pub Dt:	12/15/2005
Title:	CONTIGUOUS BLOCK ADDRESSING SCHEME

Patent #:	7154781	Issue Dt:	12/26/2006	Application #:	11207017	Filing Dt:	08/18/2005
Publication #:	US20050276121	Pub Dt:	12/15/2005
Title:	CONTIGUOUS BLOCK ADDRESSING SCHEME

Patent #:	7154782	Issue Dt:	12/26/2006	Application #:	11207105	Filing Dt:	08/18/2005
Publication #:	US20050278481	Pub Dt:	12/15/2005
Title:	CONTIGUOUS BLOCK ADDRESSING SCHEME

Patent #:	7120754	Issue Dt:	10/10/2006	Application #:	11268760	Filing Dt:	11/08/2005
Publication #:	US20060112231	Pub Dt:	05/25/2006
Title:	SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE

Patent #:	7292494	Issue Dt:	11/06/2007	Application #:	11339624	Filing Dt:	01/26/2006
Publication #:	US20060146636	Pub Dt:	07/06/2006
Title:	INTERNAL POWER MANAGEMENT SCHEME FOR A MEMORY CHIP IN DEEP POWER DOWN MODE

Patent #:	7473623	Issue Dt:	01/06/2009	Application #:	11428022	Filing Dt:	06/30/2006
Publication #:	US20080003789	Pub Dt:	01/03/2008
Title:	PROVIDING STRESS UNIFORMITY IN A SEMICONDUCTOR DEVICE

Patent #:	7669068	Issue Dt:	02/23/2010	Application #:	11449499	Filing Dt:	06/07/2006
Publication #:	US20060230303	Pub Dt:	10/12/2006
Title:	CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Patent #:	7531403	Issue Dt:	05/12/2009	Application #:	11538001	Filing Dt:	10/02/2006
Publication #:	US20080079074	Pub Dt:	04/03/2008
Title:	SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION

Patent #:	7696052	Issue Dt:	04/13/2010	Application #:	11558006	Filing Dt:	11/09/2006
Publication #:	US20070228482	Pub Dt:	10/04/2007
Title:	TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS

Patent #:	7546440	Issue Dt:	06/09/2009	Application #:	11581887	Filing Dt:	10/17/2006
Publication #:	US20070038800	Pub Dt:	02/15/2007
Title:	NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF

Patent #:	7504287	Issue Dt:	03/17/2009	Application #:	11689764	Filing Dt:	03/22/2007
Publication #:	US20080233738	Pub Dt:	09/25/2008
Title:	METHODS FOR FABRICATING AN INTEGRATED CIRCUIT

Patent #:	7906424	Issue Dt:	03/15/2011	Application #:	11832486	Filing Dt:	08/01/2007
Publication #:	US20090032940	Pub Dt:	02/05/2009
Title:	CONDUCTOR BUMP METHOD AND APPARATUS

Patent #:	7754556	Issue Dt:	07/13/2010	Application #:	12027583	Filing Dt:	02/07/2008
Publication #:	US20090001484	Pub Dt:	01/01/2009
Title:	REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS

Patent #:	7816199	Issue Dt:	10/19/2010	Application #:	12037533	Filing Dt:	02/26/2008
Publication #:	US20090035924	Pub Dt:	02/05/2009
Title:	METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS OF A NON-DOPING ELEMENT

Patent #:	7870435	Issue Dt:	01/11/2011	Application #:	12336371	Filing Dt:	12/16/2008
Publication #:	US20090100291	Pub Dt:	04/16/2009
Title:	MEMORY DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY

Patent #:	7908427	Issue Dt:	03/15/2011	Application #:	12387058	Filing Dt:	04/27/2009
Publication #:	US20100030949	Pub Dt:	02/04/2010
Title:	NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF

Patent #:	7986008	Issue Dt:	07/26/2011	Application #:	12413185	Filing Dt:	03/27/2009
Publication #:	US20090184372	Pub Dt:	07/23/2009
Title:	SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION

Patent #:	8318598	Issue Dt:	11/27/2012	Application #:	12537321	Filing Dt:	08/07/2009
Publication #:	US20100078823	Pub Dt:	04/01/2010
Title:	CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE

Patent #:	8412968	Issue Dt:	04/02/2013	Application #:	12652897	Filing Dt:	01/06/2010
Publication #:	US20100174932	Pub Dt:	07/08/2010
Title:	CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Patent #:	8274120	Issue Dt:	09/25/2012	Application #:	12710744	Filing Dt:	02/23/2010
Publication #:	US20100155850	Pub Dt:	06/24/2010
Title:	TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS

Patent #:	8183605	Issue Dt:	05/22/2012	Application #:	12791290	Filing Dt:	06/01/2010
Publication #:	US20100237431	Pub Dt:	09/23/2010
Title:	REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS

Patent #:	8294266	Issue Dt:	10/23/2012	Application #:	13027076	Filing Dt:	02/14/2011
Publication #:	US20110133338	Pub Dt:	06/09/2011
Title:	CONDUCTOR BUMP METHOD AND APPARATUS

Patent #:	8145832	Issue Dt:	03/27/2012	Application #:	13035580	Filing Dt:	02/25/2011
Publication #:	US20110238894	Pub Dt:	09/29/2011
Title:	NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF

Patent #:	9213630	Issue Dt:	12/15/2015	Application #:	13399587	Filing Dt:	02/17/2012
Publication #:	US20120215967	Pub Dt:	08/23/2012
Title:	NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF

Patent #:	9003214	Issue Dt:	04/07/2015	Application #:	13796677	Filing Dt:	03/12/2013
Publication #:	US20130275799	Pub Dt:	10/17/2013
Title:	CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Patent #:	9239979	Issue Dt:	01/19/2016	Application #:	14598219	Filing Dt:	01/15/2015
Title:	SYNTHETIC BARCODE PAYMENT SYSTEM AND METHOD

Patent #:	9201489	Issue Dt:	12/01/2015	Application #:	14659934	Filing Dt:	03/17/2015
Publication #:	US20150192982	Pub Dt:	07/09/2015
Title:	CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Patent #:	9489670	Issue Dt:	11/08/2016	Application #:	14836456	Filing Dt:	08/26/2015
Publication #:	US20160210613	Pub Dt:	07/21/2016
Title:	HYBRID WIRELESS SHORT RANGE PAYMENT SYSTEM AND METHOD

Assignor

CPPIB CREDIT INVESTMENTS INC.

Exec Dt:

10/28/2020

Assignee

CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

515 LEGGET DRIVE

SUITE 704

OTTAWA, CANADA K2K 3G4

Correspondence name and address
	CONVERSANT IP MANAGEMENT CORP
	5830 GRANITE PARKWAY #100-247
	SUITE 247
	PLANO, TX 75024

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