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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 12 of 85
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Patent #:	7683428	Issue Dt:	03/23/2010	Application #:	10597288	Filing Dt:	07/19/2006
Publication #:	US20090200604	Pub Dt:	08/13/2009
Title:	VERTICAL FIN-FET MOS DEVICES

Patent #:	6780736	Issue Dt:	08/24/2004	Application #:	10604009	Filing Dt:	06/20/2003
Title:	METHOD FOR IMAGE REVERSAL OF IMPLANT RESIST USING A SINGLE PHOTOLITHOGRAPHY EXPOSURE AND STRUCTURES FORMED THEREBY

Patent #:	7030031	Issue Dt:	04/18/2006	Application #:	10604056	Filing Dt:	06/24/2003
Publication #:	US20040266201	Pub Dt:	12/30/2004
Title:	METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH DIFFUSION BARRIER MATERIAL

Patent #:	7350160	Issue Dt:	03/25/2008	Application #:	10604059	Filing Dt:	06/24/2003
Publication #:	US20040268284	Pub Dt:	12/30/2004
Title:	METHOD OF DISPLAYING A GUARD RING WITHIN AN INTEGRATED CIRCUIT

Patent #:	6969648	Issue Dt:	11/29/2005	Application #:	10604081	Filing Dt:	06/25/2003
Publication #:	US20050009268	Pub Dt:	01/13/2005
Title:	METHOD FOR FORMING BURIED PLATE OF TRENCH CAPACITOR

Patent #:	6992354	Issue Dt:	01/31/2006	Application #:	10604086	Filing Dt:	06/25/2003
Publication #:	US20040262688	Pub Dt:	12/30/2004
Title:	FINFET HAVING SUPPRESSED PARASITIC DEVICE CHARACTERISTICS

Patent #:	7068564	Issue Dt:	06/27/2006	Application #:	10604168	Filing Dt:	06/29/2003
Publication #:	US20040264289	Pub Dt:	12/30/2004
Title:	TIMER LOCKOUT CIRCUIT FOR SYNCHRONOUS APPLICATIONS

Patent #:	6943405	Issue Dt:	09/13/2005	Application #:	10604206	Filing Dt:	07/01/2003
Publication #:	US20050001273	Pub Dt:	01/06/2005
Title:	INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS

Patent #:	6960820	Issue Dt:	11/01/2005	Application #:	10604212	Filing Dt:	07/01/2003
Publication #:	US20050012180	Pub Dt:	01/20/2005
Title:	BIPOLAR TRANSISTOR SELF-ALIGNMENT WITH RAISED EXTRINSIC BASE EXTENSION AND METHODS OF FORMING SAME

Patent #:	7202764	Issue Dt:	04/10/2007	Application #:	10604278	Filing Dt:	07/08/2003
Publication #:	US20050007217	Pub Dt:	01/13/2005
Title:	NOBLE METAL CONTACTS FOR MICRO-ELECTROMECHANICAL SWITCHES

Patent #:	6954387	Issue Dt:	10/11/2005	Application #:	10604375	Filing Dt:	07/15/2003
Publication #:	US20050013185	Pub Dt:	01/20/2005
Title:	DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER

Patent #:	6833603	Issue Dt:	12/21/2004	Application #:	10604696	Filing Dt:	08/11/2003
Title:	DYNAMICALLY PATTERNED SHIELDED HIGH-Q INDUCTOR

Patent #:	6930004	Issue Dt:	08/16/2005	Application #:	10604731	Filing Dt:	08/13/2003
Publication #:	US20050037561	Pub Dt:	02/17/2005
Title:	SELF-ALIGNED DRAIN/CHANNEL JUNCTION IN VERTICAL PASS TRANSISTOR DRAM CELL DESIGN FOR DEVICE SCALING

Patent #:	6788591	Issue Dt:	09/07/2004	Application #:	10604909	Filing Dt:	08/26/2003
Title:	SYSTEM AND METHOD FOR DIRECT WRITE TO DYNAMIC RANDOM ACCESS MEMORY (DRAM) USING PFET BIT-SWITCH

Patent #:	6831866	Issue Dt:	12/14/2004	Application #:	10604911	Filing Dt:	08/26/2003
Title:	METHOD AND APPARATUS FOR READ BITLINE CLAMPING FOR GAIN CELL DRAM DEVICES

Patent #:	6921711	Issue Dt:	07/26/2005	Application #:	10605106	Filing Dt:	09/09/2003
Publication #:	US20050051854	Pub Dt:	03/10/2005
Title:	METHOD FOR FORMING METAL REPLACEMENT GATE OF HIGH PERFORMANCE

Patent #:	6821833	Issue Dt:	11/23/2004	Application #:	10605110	Filing Dt:	09/09/2003
Title:	METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY

Patent #:	6908850	Issue Dt:	06/21/2005	Application #:	10605130	Filing Dt:	09/10/2003
Publication #:	US20050055494	Pub Dt:	03/10/2005
Title:	STRUCTURE AND METHOD FOR SILICIDED METAL GATE TRANSISTORS

Patent #:	6906360	Issue Dt:	06/14/2005	Application #:	10605134	Filing Dt:	09/10/2003
Publication #:	US20050051851	Pub Dt:	03/10/2005
Title:	STRUCTURE AND METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS

Patent #:	7112535	Issue Dt:	09/26/2006	Application #:	10605439	Filing Dt:	09/30/2003
Publication #:	US20050070102	Pub Dt:	03/31/2005
Title:	PRECISION POLYSILICON RESISTOR PROCESS

Patent #:	7071532	Issue Dt:	07/04/2006	Application #:	10605440	Filing Dt:	09/30/2003
Publication #:	US20050067673	Pub Dt:	03/31/2005
Title:	ADJUSTABLE SELF-ALIGNED AIR GAP DIELECTRIC FOR LOW CAPACITANCE WIRING

Patent #:	6876028	Issue Dt:	04/05/2005	Application #:	10605444	Filing Dt:	09/30/2003
Publication #:	US20050067701	Pub Dt:	03/31/2005
Title:	METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION

Patent #:	7127560	Issue Dt:	10/24/2006	Application #:	10605616	Filing Dt:	10/14/2003
Publication #:	US20050080994	Pub Dt:	04/14/2005
Title:	METHOD OF DYNAMICALLY CONTROLLING CACHE SIZE

Patent #:	7119403	Issue Dt:	10/10/2006	Application #:	10605672	Filing Dt:	10/16/2003
Publication #:	US20050082634	Pub Dt:	04/21/2005
Title:	HIGH PERFORMANCE STRAINED CMOS DEVICES

Patent #:	6861716	Issue Dt:	03/01/2005	Application #:	10605861	Filing Dt:	10/31/2003
Title:	LADDER-TYPE GATE STRUCTURE FOR FOUR-TERMINAL SOI SEMICONDUCTOR DEVICE

Patent #:	7015582	Issue Dt:	03/21/2006	Application #:	10605891	Filing Dt:	11/04/2003
Publication #:	US20040195670	Pub Dt:	10/07/2004
Title:	DUMMY METAL FILL SHAPES FOR IMPROVED RELIABILITY OF HYBRID OXIDE/LOW-K DIELECTRICS

Patent #:	6962843	Issue Dt:	11/08/2005	Application #:	10605905	Filing Dt:	11/05/2003
Publication #:	US20050093074	Pub Dt:	05/05/2005
Title:	METHOD OF FABRICATING A FINFET

Patent #:	6879448	Issue Dt:	04/12/2005	Application #:	10609237	Filing Dt:	06/26/2003
Publication #:	US20040264007	Pub Dt:	12/30/2004
Title:	APPARATUS FOR ACHROMATIZING OPTICAL BEAMS

Patent #:	6876252	Issue Dt:	04/05/2005	Application #:	10609360	Filing Dt:	06/28/2003
Publication #:	US20040263237	Pub Dt:	12/30/2004
Title:	NON-ABRUPT SWITCHING OF SLEEP TRANSISTOR OF POWER GATE STRUCTURE

Patent #:	6936882	Issue Dt:	08/30/2005	Application #:	10614001	Filing Dt:	07/08/2003
Title:	SELECTIVE SILICIDATION OF GATES IN SEMICONDUCTOR DEVICES TO ACHIEVE MULTIPLE THRESHOLD VOLTAGES

Patent #:	7045384	Issue Dt:	05/16/2006	Application #:	10614031	Filing Dt:	07/08/2003
Title:	METHOD FOR DETERMINING METAL WORK FUNCTION BY FORMATION OF SCHOTTKY DIODES WITH SHADOW MASK

Patent #:	7694110	Issue Dt:	04/06/2010	Application #:	10614970	Filing Dt:	07/08/2003
Title:	SYSTEM AND METHOD OF IMPLEMENTING MICROCODE OPERATIONS AS SUBROUTINES

Patent #:	7321964	Issue Dt:	01/22/2008	Application #:	10615101	Filing Dt:	07/08/2003
Publication #:	US20050010744	Pub Dt:	01/13/2005
Title:	STORE-TO-LOAD FORWARDING BUFFER USING INDEXED LOOKUP

Patent #:	6901003	Issue Dt:	05/31/2005	Application #:	10616847	Filing Dt:	07/10/2003
Publication #:	US20050007813	Pub Dt:	01/13/2005
Title:	LOWER POWER AND REDUCED DEVICE SPLIT LOCAL AND CONTINUOUS BITLINE FOR DOMINO READ SRAMS

Patent #:	7006209	Issue Dt:	02/28/2006	Application #:	10628021	Filing Dt:	07/25/2003
Publication #:	US20050018208	Pub Dt:	01/27/2005
Title:	METHOD AND APPARATUS FOR MONITORING AND CONTROLLING IMAGING IN IMMERSION LITHOGRAPHY SYSTEMS

Patent #:	7071539	Issue Dt:	07/04/2006	Application #:	10628925	Filing Dt:	07/28/2003
Publication #:	US20050023689	Pub Dt:	02/03/2005
Title:	CHEMICAL PLANARIZATION PERFORMANCE FOR COPPER/LOW-K INTERCONNECT STRUCTURES

Patent #:	6905924	Issue Dt:	06/14/2005	Application #:	10629436	Filing Dt:	07/29/2003
Publication #:	US20040188768	Pub Dt:	09/30/2004
Title:	DIODE STRUCTURE FOR SOI CIRCUITS

Patent #:	7128472	Issue Dt:	10/31/2006	Application #:	10631933	Filing Dt:	07/31/2003
Publication #:	US20050025434	Pub Dt:	02/03/2005
Title:	METHOD AND APPARATUS FOR PROVIDING OPTOELECTRONIC COMMUNICATION WITH AN ELECTRONIC DEVICE

Patent #:	7055119	Issue Dt:	05/30/2006	Application #:	10632183	Filing Dt:	07/31/2003
Publication #:	US20050028130	Pub Dt:	02/03/2005
Title:	CUSTOMIZED MESH PLANE, METHOD AND COMPUTER PROGRAM PRODUCT FOR CREATING CUSTOMIZED MESH PLANES WITHIN ELECTRONIC PACKAGES

Patent #:	7045372	Issue Dt:	05/16/2006	Application #:	10632652	Filing Dt:	08/02/2003
Publication #:	US20040021201	Pub Dt:	02/05/2004
Title:	APPARATUS AND METHOD FOR FORMING A BATTERY IN AN INTEGRATED CIRCUIT

Patent #:	7095065	Issue Dt:	08/22/2006	Application #:	10633504	Filing Dt:	08/05/2003
Publication #:	US20050029603	Pub Dt:	02/10/2005
Title:	VARYING CARRIER MOBILITY IN SEMICONDUCTOR DEVICES TO ACHIEVE OVERALL DESIGN GOALS

Patent #:	7061578	Issue Dt:	06/13/2006	Application #:	10638927	Filing Dt:	08/11/2003
Publication #:	US20050037269	Pub Dt:	02/17/2005
Title:	METHOD AND APPARATUS FOR MONITORING AND CONTROLLING IMAGING IN IMMERSION LITHOGRAPHY SYSTEMS

Patent #:	7060624	Issue Dt:	06/13/2006	Application #:	10639989	Filing Dt:	08/13/2003
Publication #:	US20050037608	Pub Dt:	02/17/2005
Title:	DEEP FILLED VIAS

Patent #:	6791855	Issue Dt:	09/14/2004	Application #:	10641753	Filing Dt:	08/14/2003
Publication #:	US20040052134	Pub Dt:	03/18/2004
Title:	REDUNDANT ARRAY ARCHITECTURE FOR WORD REPLACEMENT IN CAM

Patent #:	6924182	Issue Dt:	08/02/2005	Application #:	10642375	Filing Dt:	08/15/2003
Title:	STRAINED SILICON MOSFET HAVING REDUCED LEAKAGE AND METHOD OF ITS FORMATION

Patent #:	8214169	Issue Dt:	07/03/2012	Application #:	10643193	Filing Dt:	08/18/2003
Publication #:	US20050043908	Pub Dt:	02/24/2005
Title:	CIRCUITS AND METHODS FOR CHARACTERIZING RANDOM VARIATIONS IN DEVICE CHARACTERISTICS IN SEMICONDUCTOR INTEGRATED CIRCUITS

Patent #:	7923785	Issue Dt:	04/12/2011	Application #:	10643461	Filing Dt:	08/18/2003
Publication #:	US20050040477	Pub Dt:	02/24/2005
Title:	FIELD EFFECT TRANSISTOR HAVING INCREASED CARRIER MOBILITY

Patent #:	6943097	Issue Dt:	09/13/2005	Application #:	10643534	Filing Dt:	08/19/2003
Publication #:	US20050042865	Pub Dt:	02/24/2005
Title:	ATOMIC LAYER DEPOSITION OF METALLIC CONTACTS, GATES AND DIFFUSION BARRIERS

Patent #:	6952113	Issue Dt:	10/04/2005	Application #:	10644211	Filing Dt:	08/20/2003
Publication #:	US20050040881	Pub Dt:	02/24/2005
Title:	METHOD OF REDUCING LEAKAGE CURRENT IN SUB ONE VOLT SOI CIRCUITS

Patent #:	6815277	Issue Dt:	11/09/2004	Application #:	10645063	Filing Dt:	08/21/2003
Publication #:	US20040038464	Pub Dt:	02/26/2004
Title:	MULTIPLE-PLANE FINFET CMOS

Patent #:	6987689	Issue Dt:	01/17/2006	Application #:	10645240	Filing Dt:	08/20/2003
Publication #:	US20050040455	Pub Dt:	02/24/2005
Title:	NON-VOLATILE MULTI-STABLE MEMORY DEVICE AND METHODS OF MAKING AND USING THE SAME

Patent #:	6815278	Issue Dt:	11/09/2004	Application #:	10647395	Filing Dt:	08/25/2003
Title:	ULTRA-THIN SILICON-ON-INSULATOR AND STRAINED-SILICON-DIRECT-ON-INSULATOR WITH HYBRID CRYSTAL ORIENTATIONS

Patent #:	7081673	Issue Dt:	07/25/2006	Application #:	10648884	Filing Dt:	08/27/2003
Publication #:	US20040207084	Pub Dt:	10/21/2004
Title:	MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES

Patent #:	6894390	Issue Dt:	05/17/2005	Application #:	10649049	Filing Dt:	08/27/2003
Publication #:	US20040164409	Pub Dt:	08/26/2004
Title:	SOFT ERROR RESISTANT SEMICONDUCTOR DEVICE

Patent #:	6920061	Issue Dt:	07/19/2005	Application #:	10649200	Filing Dt:	08/27/2003
Publication #:	US20050047196	Pub Dt:	03/03/2005
Title:	LOADLESS NMOS FOUR TRANSISTOR DYNAMIC DUAL VT SRAM CELL

Patent #:	6914303	Issue Dt:	07/05/2005	Application #:	10650229	Filing Dt:	08/28/2003
Publication #:	US20050048752	Pub Dt:	03/03/2005
Title:	ULTRA THIN CHANNEL MOSFET

Patent #:	6855963	Issue Dt:	02/15/2005	Application #:	10652400	Filing Dt:	08/29/2003
Publication #:	US20050045905	Pub Dt:	03/03/2005
Title:	ULTRA HIGH-SPEED SI/SIGE MODULATION-DOPED FIELD EFFECT TRANSISTORS ON ULTRA THIN SOI/SGOI SUBSTRATE

Patent #:	6876042	Issue Dt:	04/05/2005	Application #:	10653105	Filing Dt:	09/03/2003
Title:	ADDITIONAL GATE CONTROL FOR A DOUBLE-GATE MOSFET

Patent #:	6841228	Issue Dt:	01/11/2005	Application #:	10653295	Filing Dt:	09/03/2003
Publication #:	US20040081810	Pub Dt:	04/29/2004
Title:	STRUCTURE HAVING EMBEDDED FLUSH CIRCUITRY FEATURES AND METHOD OF FABRICATING

Patent #:	6873184	Issue Dt:	03/29/2005	Application #:	10653802	Filing Dt:	09/03/2003
Title:	CIRCULAR BUFFER USING GROUPING FOR FIND FIRST FUNCTION

Patent #:	7014966	Issue Dt:	03/21/2006	Application #:	10653844	Filing Dt:	09/02/2003
Publication #:	US20050048223	Pub Dt:	03/03/2005
Title:	METHOD AND APPARATUS FOR ELIMINATION OF BUBBLES IN IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY SYSTEMS

Patent #:	6989058	Issue Dt:	01/24/2006	Application #:	10654232	Filing Dt:	09/03/2003
Publication #:	US20050048778	Pub Dt:	03/03/2005
Title:	USE OF THIN SOI TO INHIBIT RELAXATION OF SIGE LAYERS

Patent #:	6955969	Issue Dt:	10/18/2005	Application #:	10654497	Filing Dt:	09/03/2003
Publication #:	US20050048743	Pub Dt:	03/03/2005
Title:	METHOD OF GROWING AS A CHANNEL REGION TO REDUCE SOURCE/DRAIN JUNCTION CAPACITANCE

Patent #:	7051300	Issue Dt:	05/23/2006	Application #:	10655390	Filing Dt:	09/04/2003
Title:	METHOD AND SYSTEM FOR ARCHITECTURAL POWER ESTIMATION

Patent #:	6821718	Issue Dt:	11/23/2004	Application #:	10657168	Filing Dt:	09/09/2003
Publication #:	US20040048204	Pub Dt:	03/11/2004
Title:	RADIATION SENSITIVE SILICON-CONTAINING NEGATIVE RESISTS AND USE THEREOF

Patent #:	6928377	Issue Dt:	08/09/2005	Application #:	10658940	Filing Dt:	09/09/2003
Publication #:	US20050055173	Pub Dt:	03/10/2005
Title:	SELF-TEST ARCHITECTURE TO IMPLEMENT DATA COLUMN REDUNDANCY IN A RAM

Patent #:	6815296	Issue Dt:	11/09/2004	Application #:	10659950	Filing Dt:	09/11/2003
Publication #:	US20040046208	Pub Dt:	03/11/2004
Title:	POLYSILICON BACK-GATED SOI MOSFET FOR DYNAMIC THRESHOLD VOLTAGE CONTROL

Patent #:	7030008	Issue Dt:	04/18/2006	Application #:	10661041	Filing Dt:	09/12/2003
Publication #:	US20050056823	Pub Dt:	03/17/2005
Title:	TECHNIQUES FOR PATTERNING FEATURES IN SEMICONDUCTOR DEVICES

Patent #:	7029951	Issue Dt:	04/18/2006	Application #:	10661299	Filing Dt:	09/12/2003
Publication #:	US20050059238	Pub Dt:	03/17/2005
Title:	COOLING SYSTEM FOR A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

Patent #:	7067437	Issue Dt:	06/27/2006	Application #:	10662022	Filing Dt:	09/12/2003
Publication #:	US20050059258	Pub Dt:	03/17/2005
Title:	STRUCTURES WITH IMPROVED INTERFACIAL STRENGTH OF SICOH DIELECTRICS AND METHOD FOR PREPARING THE SAME

Patent #:	7114136	Issue Dt:	09/26/2006	Application #:	10663020	Filing Dt:	09/16/2003
Publication #:	US20050262454	Pub Dt:	11/24/2005
Title:	METHOD FOR VLSI SYSTEM DEBUG AND TIMING ANALYSIS

Patent #:	7205185	Issue Dt:	04/17/2007	Application #:	10663471	Filing Dt:	09/15/2003
Publication #:	US20050059252	Pub Dt:	03/17/2005
Title:	SELF-ALIGNED PLANAR DOUBLE-GATE PROCESS BY SELF-ALIGNED OXIDATION

Patent #:	7063127	Issue Dt:	06/20/2006	Application #:	10665798	Filing Dt:	09/18/2003
Publication #:	US20050061474	Pub Dt:	03/24/2005
Title:	METHOD AND APPARATUS FOR CHIP-COOLING

Patent #:	7428716	Issue Dt:	09/23/2008	Application #:	10666353	Filing Dt:	09/19/2003
Publication #:	US20050065765	Pub Dt:	03/24/2005
Title:	SYSTEM AND METHOD FOR STATISTICAL TIMING ANALYSIS OF DIGITAL CIRCUITS

Patent #:	6872641	Issue Dt:	03/29/2005	Application #:	10667603	Filing Dt:	09/23/2003
Publication #:	US20050064686	Pub Dt:	03/24/2005
Title:	STRAINED SILICON ON RELAXED SIGE FILM WITH UNIFORM MISFIT DISLOCATION DENSITY

Patent #:	6985645	Issue Dt:	01/10/2006	Application #:	10669944	Filing Dt:	09/24/2003
Publication #:	US20050063634	Pub Dt:	03/24/2005
Title:	APPARATUS AND METHODS FOR INTEGRALLY PACKAGING OPTOELECTRONIC DEVICES, IC CHIPS AND OPTICAL TRANSMISSION LINES

Patent #:	7078341	Issue Dt:	07/18/2006	Application #:	10673648	Filing Dt:	09/30/2003
Publication #:	US20050079708	Pub Dt:	04/14/2005
Title:	METHOD OF DEPOSITING METAL LAYERS FROM METAL-CARBONYL PRECURSORS

Patent #:	7355872	Issue Dt:	04/08/2008	Application #:	10673801	Filing Dt:	09/29/2003
Publication #:	US20050071544	Pub Dt:	03/31/2005
Title:	SEGMENTED CONTENT ADDRESSABLE MEMORY ARCHITECTURE FOR IMPROVED CYCLE TIME AND REDUCED POWER CONSUMPTION

Patent #:	6995438	Issue Dt:	02/07/2006	Application #:	10674478	Filing Dt:	10/01/2003
Title:	SEMICONDUCTOR DEVICE WITH FULLY SILICIDED SOURCE/DRAIN AND DAMASCENE METAL GATE

Patent #:	6855989	Issue Dt:	02/15/2005	Application #:	10674520	Filing Dt:	10/01/2003
Title:	DAMASCENE FINFET GATE WITH SELECTIVE METAL INTERDIFFUSION

Patent #:	6821826	Issue Dt:	11/23/2004	Application #:	10674644	Filing Dt:	09/30/2003
Title:	THREE DIMENSIONAL CMOS INTEGRATED CIRCUITS HAVING DEVICE LAYERS BUILT ON DIFFERENT CRYSTAL ORIENTED WAFERS

Patent #:	7052958	Issue Dt:	05/30/2006	Application #:	10675625	Filing Dt:	09/30/2003
Title:	FINFET CMOS WITH NVRAM CAPABILITY

Patent #:	6787427	Issue Dt:	09/07/2004	Application #:	10676171	Filing Dt:	10/01/2003
Publication #:	US20040063293	Pub Dt:	04/01/2004
Title:	METHOD TO FABRICATE SIGE HBTS WITH CONTROLLED CURRENT GAIN AND IMPROVED BREAKDOWN VOLTAGE CHARACTERISTICS

Patent #:	7133969	Issue Dt:	11/07/2006	Application #:	10676437	Filing Dt:	10/01/2003
Publication #:	US20050076180	Pub Dt:	04/07/2005
Title:	SYSTEM AND METHOD FOR HANDLING EXCEPTIONAL INSTRUCTIONS IN A TRACE CACHE BASED PROCESSOR

Patent #:	7069155	Issue Dt:	06/27/2006	Application #:	10676455	Filing Dt:	10/01/2003
Title:	REAL TIME ANALYTICAL MONITOR FOR SOFT DEFECTS ON RETICLE DURING RETICLE INSPECTION

Patent #:	7165172	Issue Dt:	01/16/2007	Application #:	10676600	Filing Dt:	10/01/2003
Title:	FACILITATING COLD RESET AND WARM RESET TASKING IN A COMPUTER SYSTEM

Patent #:	7043626	Issue Dt:	05/09/2006	Application #:	10676636	Filing Dt:	10/01/2003
Title:	Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

Patent #:	7056646	Issue Dt:	06/06/2006	Application #:	10676749	Filing Dt:	10/01/2003
Title:	USE OF BASE DEVELOPERS AS IMMERSION LITHOGRAPHY FLUID

Patent #:	6967363	Issue Dt:	11/22/2005	Application #:	10676904	Filing Dt:	10/01/2003
Title:	LATERAL DIODE WITH MULTIPLE SPACERS

Patent #:	6927454	Issue Dt:	08/09/2005	Application #:	10680820	Filing Dt:	10/07/2003
Publication #:	US20050073014	Pub Dt:	04/07/2005
Title:	SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK

Patent #:	6956296	Issue Dt:	10/18/2005	Application #:	10681513	Filing Dt:	10/08/2003
Publication #:	US20040071805	Pub Dt:	04/15/2004
Title:	TRANSFER MOLDING OF INTEGRATED CIRCUIT PACKAGES

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100

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Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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