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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 15 of 85
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Patent #:	7306983	Issue Dt:	12/11/2007	Application #:	10905024	Filing Dt:	12/10/2004
Publication #:	US20060128086	Pub Dt:	06/15/2006
Title:	METHOD FOR FORMING DUAL ETCH STOP LINER AND PROTECTIVE LAYER IN A SEMICONDUCTOR DEVICE

Patent #:	7348635	Issue Dt:	03/25/2008	Application #:	10905025	Filing Dt:	12/10/2004
Publication #:	US20060128091	Pub Dt:	06/15/2006
Title:	DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS

Patent #:	7262087	Issue Dt:	08/28/2007	Application #:	10905062	Filing Dt:	12/14/2004
Publication #:	US20060125008	Pub Dt:	06/15/2006
Title:	DUAL STRESSED SOI SUBSTRATES

Patent #:	7326651	Issue Dt:	02/05/2008	Application #:	10905068	Filing Dt:	12/14/2004
Publication #:	US20050079701	Pub Dt:	04/14/2005
Title:	METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL

Patent #:	7193262	Issue Dt:	03/20/2007	Application #:	10905094	Filing Dt:	12/15/2004
Publication #:	US20060124982	Pub Dt:	06/15/2006
Title:	LOW-COST DEEP TRENCH DECOUPLING CAPACITOR DEVICE AND PROCESS OF MANUFACTURE

Patent #:	7518215	Issue Dt:	04/14/2009	Application #:	10905486	Filing Dt:	01/06/2005
Publication #:	US20060145300	Pub Dt:	07/06/2006
Title:	ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT

Patent #:	7271442	Issue Dt:	09/18/2007	Application #:	10905586	Filing Dt:	01/12/2005
Publication #:	US20060151833	Pub Dt:	07/13/2006
Title:	TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS

Patent #:	7345370	Issue Dt:	03/18/2008	Application #:	10905590	Filing Dt:	01/12/2005
Publication #:	US20060154463	Pub Dt:	07/13/2006
Title:	WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING

Patent #:	7153737	Issue Dt:	12/26/2006	Application #:	10905684	Filing Dt:	01/17/2005
Publication #:	US20060160298	Pub Dt:	07/20/2006
Title:	SELF-ALIGNED, SILICIDED, TRENCH-BASED, DRAM/EDRAM PROCESSES WITH IMPROVED RETENTION

Patent #:	7071530	Issue Dt:	07/04/2006	Application #:	10905934	Filing Dt:	01/27/2005
Publication #:	US20060163688	Pub Dt:	07/27/2006
Title:	MULTIPLE LAYER STRUCTURE FOR SUBSTRATE NOISE ISOLATION

Patent #:	7091542	Issue Dt:	08/15/2006	Application #:	10905973	Filing Dt:	01/28/2005
Publication #:	US20060170024	Pub Dt:	08/03/2006
Title:	METHOD OF FORMING A MIM CAPACITOR FOR CU BEOL APPLICATION

Patent #:	7535016	Issue Dt:	05/19/2009	Application #:	10906016	Filing Dt:	01/31/2005
Publication #:	US20060169972	Pub Dt:	08/03/2006
Title:	VERTICAL CARBON NANOTUBE TRANSISTOR INTEGRATION

Patent #:	7439568	Issue Dt:	10/21/2008	Application #:	10906238	Filing Dt:	02/10/2005
Publication #:	US20060175660	Pub Dt:	08/10/2006
Title:	VERTICAL BODY-CONTACTED SOI TRANSISTOR

Patent #:	7531444	Issue Dt:	05/12/2009	Application #:	10906267	Filing Dt:	02/11/2005
Publication #:	US20060183315	Pub Dt:	08/17/2006
Title:	METHOD TO CREATE AIR GAPS USING NON-PLASMA PROCESSES TO DAMAGE ILD MATERIALS

Patent #:	7224033	Issue Dt:	05/29/2007	Application #:	10906335	Filing Dt:	02/15/2005
Publication #:	US20060180866	Pub Dt:	08/17/2006
Title:	STRUCTURE AND METHOD FOR MANUFACTURING STRAINED FINFET

Patent #:	7271700	Issue Dt:	09/18/2007	Application #:	10906365	Filing Dt:	02/16/2005
Publication #:	US20060181388	Pub Dt:	08/17/2006
Title:	THIN FILM RESISTOR WITH CURRENT DENSITY ENHANCING LAYER (CDEL)

Patent #:	7288805	Issue Dt:	10/30/2007	Application #:	10906547	Filing Dt:	02/24/2005
Publication #:	US20060197147	Pub Dt:	09/07/2006
Title:	IMPROVED DOUBLE GATE ISOLATION

Patent #:	7227207	Issue Dt:	06/05/2007	Application #:	10906718	Filing Dt:	03/03/2005
Publication #:	US20060197179	Pub Dt:	09/07/2006
Title:	DENSE SEMICONDUCTOR FUSE ARRAY

Patent #:	8053823	Issue Dt:	11/08/2011	Application #:	10906808	Filing Dt:	03/08/2005
Publication #:	US20060202249	Pub Dt:	09/14/2006
Title:	SIMPLIFIED BURIED PLATE STRUCTURE AND PROCESS FOR SEMICONDUCTOR-ON-INSULATOR CHIP

Patent #:	7049209	Issue Dt:	05/23/2006	Application #:	10907463	Filing Dt:	04/01/2005
Title:	DE-FLUORINATION OF WAFER SURFACE AND RELATED STRUCTURE

Patent #:	7259625	Issue Dt:	08/21/2007	Application #:	10907537	Filing Dt:	04/05/2005
Publication #:	US20060220737	Pub Dt:	10/05/2006
Title:	HIGH Q MONOLITHIC INDUCTORS FOR USE IN DIFFERENTIAL CIRCUITS

Patent #:	7451070	Issue Dt:	11/11/2008	Application #:	10907628	Filing Dt:	04/08/2005
Publication #:	US20060229858	Pub Dt:	10/12/2006
Title:	OPTIMAL BUS OPERATION PERFORMANCE IN A LOGIC SIMULATION ENVIRONMENT

Patent #:	7816728	Issue Dt:	10/19/2010	Application #:	10907686	Filing Dt:	04/12/2005
Publication #:	US20060226474	Pub Dt:	10/12/2006
Title:	STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS

Patent #:	7091551	Issue Dt:	08/15/2006	Application #:	10907712	Filing Dt:	04/13/2005
Title:	FOUR-BIT FINFET NVRAM MEMORY DEVICE

Patent #:	7166913	Issue Dt:	01/23/2007	Application #:	10907873	Filing Dt:	04/19/2005
Publication #:	US20060231945	Pub Dt:	10/19/2006
Title:	HEAT DISSIPATION FOR HEAT GENERATING ELEMENT OF SEMICONDUCTOR DEVICE AND RELATED METHOD

Patent #:	7504700	Issue Dt:	03/17/2009	Application #:	10907935	Filing Dt:	04/21/2005
Publication #:	US20060237803	Pub Dt:	10/26/2006
Title:	METHOD OF FORMING AN ULTRA-THIN [[HFSIO]] METAL SILCATE FILM FOR HIGH PERFORMANCE CMOS APPLICATIONS AND SEMICONDUCTOR STRUCTURE FORMED IN SAID METHOD

Patent #:	7102181	Issue Dt:	09/05/2006	Application #:	10907971	Filing Dt:	04/22/2005
Title:	STRUCTURE AND METHOD FOR DUAL-GATE FET WITH SOI SUBSTRATE

Patent #:	7329951	Issue Dt:	02/12/2008	Application #:	10908083	Filing Dt:	04/27/2005
Publication #:	US20060244139	Pub Dt:	11/02/2006
Title:	SOLDER BUMPS IN FLIP-CHIP TECHNOLOGIES

Patent #:	7418689	Issue Dt:	08/26/2008	Application #:	10908102	Filing Dt:	04/27/2005
Publication #:	US20060248488	Pub Dt:	11/02/2006
Title:	METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION

Patent #:	7288482	Issue Dt:	10/30/2007	Application #:	10908252	Filing Dt:	05/04/2005
Publication #:	US20060252269	Pub Dt:	11/09/2006
Title:	SILICON NITRIDE ETCHING METHODS

Patent #:	7361993	Issue Dt:	04/22/2008	Application #:	10908346	Filing Dt:	05/09/2005
Publication #:	US20060249848	Pub Dt:	11/09/2006
Title:	TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME

Patent #:	7122898	Issue Dt:	10/17/2006	Application #:	10908360	Filing Dt:	05/09/2005
Publication #:	US20060249846	Pub Dt:	11/09/2006
Title:	ELECTRICAL PROGRAMMABLE METAL RESISTOR

Patent #:	7446350	Issue Dt:	11/04/2008	Application #:	10908394	Filing Dt:	05/10/2005
Publication #:	US20060255330	Pub Dt:	11/16/2006
Title:	EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER

Patent #:	7132322	Issue Dt:	11/07/2006	Application #:	10908411	Filing Dt:	05/11/2005
Publication #:	US20060258073	Pub Dt:	11/16/2006
Title:	METHOD FOR FORMING A SIGE OR SIGEC GATE SELECTIVELY IN A COMPLEMENTARY MIS/MOS FET DEVICE

Patent #:	7101763	Issue Dt:	09/05/2006	Application #:	10908556	Filing Dt:	05/17/2005
Title:	LOW CAPACITANCE JUNCTION-ISOLATION FOR BULK FINFET TECHNOLOGY

Patent #:	7087966	Issue Dt:	08/08/2006	Application #:	10908583	Filing Dt:	05/18/2005
Title:	DOUBLE-GATE FETS (FIELD EFFECT TRANSISTORS)

Patent #:	7308669	Issue Dt:	12/11/2007	Application #:	10908593	Filing Dt:	05/18/2005
Publication #:	US20060265684	Pub Dt:	11/23/2006
Title:	THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT

Patent #:	7295161	Issue Dt:	11/13/2007	Application #:	10912959	Filing Dt:	08/06/2004
Publication #:	US20060028378	Pub Dt:	02/09/2006
Title:	APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING WIRE BONDS AS RADIATING ELEMENTS

Patent #:	7179692	Issue Dt:	02/20/2007	Application #:	10913409	Filing Dt:	08/09/2004
Publication #:	US20050006666	Pub Dt:	01/13/2005
Title:	METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE

Patent #:	7129548	Issue Dt:	10/31/2006	Application #:	10916201	Filing Dt:	08/11/2004
Publication #:	US20060033165	Pub Dt:	02/16/2006
Title:	MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS

Patent #:	7312487	Issue Dt:	12/25/2007	Application #:	10919121	Filing Dt:	08/16/2004
Publication #:	US20060033110	Pub Dt:	02/16/2006
Title:	THREE DIMENSIONAL INTEGRATED CIRCUIT

Patent #:	7561541	Issue Dt:	07/14/2009	Application #:	10925112	Filing Dt:	08/24/2004
Publication #:	US20050190709	Pub Dt:	09/01/2005
Title:	DEEP SLEEP MODE FOR WLAN COMMUNICATION SYSTEMS

Patent #:	7340473	Issue Dt:	03/04/2008	Application #:	10926587	Filing Dt:	08/26/2004
Publication #:	US20060047680	Pub Dt:	03/02/2006
Title:	METHOD AND SYSTEM FOR BUILDING BINARY DECISION DIAGRAMS EFFICIENTLY IN A STRUCTURAL NETWORK REPRESENTATION OF A DIGITAL CIRCUIT

Patent #:	6962872	Issue Dt:	11/08/2005	Application #:	10930304	Filing Dt:	08/31/2004
Publication #:	US20050023664	Pub Dt:	02/03/2005
Title:	HIGH DENSITY CHIP CARRIER WITH INTEGRATED PASSIVE DEVICES

Patent #:	7227205	Issue Dt:	06/05/2007	Application #:	10930404	Filing Dt:	08/31/2004
Publication #:	US20050285187	Pub Dt:	12/29/2005
Title:	STRAINED-SILICON CMOS DEVICE AND METHOD

Patent #:	7799517	Issue Dt:	09/21/2010	Application #:	10930432	Filing Dt:	08/31/2004
Title:	SINGLE/DOUBLE DIPOLE MASK FOR CONTACT HOLES

Patent #:	7102205	Issue Dt:	09/05/2006	Application #:	10931660	Filing Dt:	09/01/2004
Publication #:	US20060043529	Pub Dt:	03/02/2006
Title:	BIPOLAR TRANSISTOR WITH EXTRINSIC STRESS LAYER

Patent #:	7098508	Issue Dt:	08/29/2006	Application #:	10932982	Filing Dt:	09/02/2004
Publication #:	US20050045995	Pub Dt:	03/03/2005
Title:	ULTRA-THIN SILICON-ON-INSULATOR AND STRAINED-SILICON-DIRECT-ON-INSULATOR WITH HYBRID CRYSTAL ORIENTATIONS

Patent #:	7558687	Issue Dt:	07/07/2009	Application #:	10932999	Filing Dt:	09/02/2004
Title:	METHOD AND APPARATUS FOR DYNAMIC ADJUSTMENT OF A SENSOR SAMPLING RATE

Patent #:	7434308	Issue Dt:	10/14/2008	Application #:	10933051	Filing Dt:	09/02/2004
Publication #:	US20060042825	Pub Dt:	03/02/2006
Title:	COOLING OF SUBSTRATE USING INTERPOSER CHANNELS

Patent #:	7052921	Issue Dt:	05/30/2006	Application #:	10934192	Filing Dt:	09/03/2004
Title:	SYSTEM AND METHOD USING IN SITU SCATTEROMETRY TO DETECT PHOTORESIST PATTERN INTEGRITY DURING THE PHOTOLITHOGRAPHY PROCESS

Patent #:	7235812	Issue Dt:	06/26/2007	Application #:	10939736	Filing Dt:	09/13/2004
Publication #:	US20060054891	Pub Dt:	03/16/2006
Title:	METHOD OF CREATING DEFECT FREE HIGH GE CONTENT (>25%) SIGE-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES

Patent #:	6989601	Issue Dt:	01/24/2006	Application #:	10946071	Filing Dt:	09/22/2004
Title:	COPPER DAMASCENE WITH LOW-K CAPPING LAYER AND IMPROVED ELECTROMIGRATION RELIABILITY

Patent #:	7783037	Issue Dt:	08/24/2010	Application #:	10946653	Filing Dt:	09/20/2004
Title:	MULTI-GIGABIT PER SECOND COMPUTING OF THE RIJNDAEL INVERSE CIPHER

Patent #:	7191305	Issue Dt:	03/13/2007	Application #:	10952269	Filing Dt:	09/28/2004
Publication #:	US20050044337	Pub Dt:	02/24/2005
Title:	METHOD AND APPARATUS FOR ADDRESS DECODING OF EMBEDDED DRAM DEVICES

Patent #:	7173274	Issue Dt:	02/06/2007	Application #:	10953378	Filing Dt:	09/29/2004
Publication #:	US20050054171	Pub Dt:	03/10/2005
Title:	INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY

Patent #:	7296167	Issue Dt:	11/13/2007	Application #:	10956537	Filing Dt:	10/01/2004
Title:	COMBINED SYSTEM RESPONSES IN A CHIP MULTIPROCESSOR

Patent #:	7257678	Issue Dt:	08/14/2007	Application #:	10956560	Filing Dt:	10/01/2004
Publication #:	US20060075192	Pub Dt:	04/06/2006
Title:	DYNAMIC RECONFIGURATION OF CACHE MEMORY

Patent #:	7472224	Issue Dt:	12/30/2008	Application #:	10956561	Filing Dt:	10/01/2004
Title:	RECONFIGURABLE PROCESSING NODE INCLUDING FIRST AND SECOND PROCESSOR CORES

Patent #:	7253065	Issue Dt:	08/07/2007	Application #:	10956851	Filing Dt:	10/01/2004
Publication #:	US20050056826	Pub Dt:	03/17/2005
Title:	SELF-ALIGNED NANOTUBE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME

Patent #:	7383423	Issue Dt:	06/03/2008	Application #:	10957250	Filing Dt:	10/01/2004
Title:	SHARED RESOURCES IN A CHIP MULTIPROCESSOR

Patent #:	7799514	Issue Dt:	09/21/2010	Application #:	10957367	Filing Dt:	10/01/2004
Title:	SURFACE TREATMENT WITH AN ACIDIC COMPOSITION TO PREVENT SUBSTRATE AND ENVIRONMENTAL CONTAMINATION

Patent #:	8187772	Issue Dt:	05/29/2012	Application #:	10961347	Filing Dt:	10/08/2004
Publication #:	US20060078637	Pub Dt:	04/13/2006
Title:	SOLID IMMERSION LENS LITHOGRAPHY

Patent #:	7480840	Issue Dt:	01/20/2009	Application #:	10963475	Filing Dt:	10/12/2004
Publication #:	US20060085699	Pub Dt:	04/20/2006
Title:	APPARATUS, SYSTEM, AND METHOD FOR FACILITATING PORT TESTING OF A MULTI-PORT HOST ADAPTER

Patent #:	6999254	Issue Dt:	02/14/2006	Application #:	10967845	Filing Dt:	10/18/2004
Title:	REFRACTIVE INDEX SYSTEM MONITOR AND CONTROL FOR IMMERSION LITHOGRAPHY

Patent #:	7050762	Issue Dt:	05/23/2006	Application #:	10970266	Filing Dt:	10/21/2004
Publication #:	US20050265401	Pub Dt:	12/01/2005
Title:	DIGITALLY CONTROLLED FILTER TUNING FOR WLAN COMMUNICATION DEVICES

Patent #:	7142064	Issue Dt:	11/28/2006	Application #:	10973366	Filing Dt:	10/26/2004
Publication #:	US20060097802	Pub Dt:	05/11/2006
Title:	SRAM RING OSCILLATOR

Patent #:	6975555	Issue Dt:	12/13/2005	Application #:	10976598	Filing Dt:	10/29/2004
Publication #:	US20050094445	Pub Dt:	05/05/2005
Title:	MAGNETIC RANDOM ACCESS MEMORY USING MEMORY CELLS WITH ROTATED MAGNETIC STORAGE ELEMENTS

Patent #:	7290203	Issue Dt:	10/30/2007	Application #:	10977432	Filing Dt:	10/29/2004
Publication #:	US20060107090	Pub Dt:	05/18/2006
Title:	DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA

Patent #:	7126370	Issue Dt:	10/24/2006	Application #:	10978067	Filing Dt:	10/28/2004
Publication #:	US20060091913	Pub Dt:	05/04/2006
Title:	POWER GATING TECHNIQUES ABLE TO HAVE DATA RETENTION AND VARIABILITY IMMUNITY PROPERTIES

Patent #:	7724059	Issue Dt:	05/25/2010	Application #:	10978183	Filing Dt:	10/29/2004
Publication #:	US20060091928	Pub Dt:	05/04/2006
Title:	CLOCK SCALING CIRCUIT

Patent #:	7320855	Issue Dt:	01/22/2008	Application #:	10980365	Filing Dt:	11/03/2004
Publication #:	US20060093959	Pub Dt:	05/04/2006
Title:	SILICON CONTAINING TARC / BARRIER LAYER

Patent #:	7335980	Issue Dt:	02/26/2008	Application #:	10981233	Filing Dt:	11/04/2004
Publication #:	US20060091559	Pub Dt:	05/04/2006
Title:	HARDMASK FOR RELIABILITY OF SILICON BASED DIELECTRICS

Patent #:	7196014	Issue Dt:	03/27/2007	Application #:	10983345	Filing Dt:	11/08/2004
Publication #:	US20060099816	Pub Dt:	05/11/2006
Title:	SYSTEM AND METHOD FOR PLASMA INDUCED MODIFICATION AND IMPROVEMENT OF CRITICAL DIMENSION UNIFORMITY

Patent #:	7031178	Issue Dt:	04/18/2006	Application #:	10984055	Filing Dt:	11/09/2004
Publication #:	US20050094427	Pub Dt:	05/05/2005
Title:	MAGNETIC SHIFT REGISTER WITH SHIFTABLE MAGNETIC DOMAINS BETWEEN TWO REGIONS, AND METHOD OF USING THE SAME

Patent #:	6987289	Issue Dt:	01/17/2006	Application #:	10984578	Filing Dt:	11/09/2004
Publication #:	US20050082578	Pub Dt:	04/21/2005
Title:	HIGH-DENSITY FINFET INTEGRATION SCHEME

Patent #:	7351360	Issue Dt:	04/01/2008	Application #:	10986665	Filing Dt:	11/12/2004
Publication #:	US20060112857	Pub Dt:	06/01/2006
Title:	SELF ORIENTING MICRO PLATES OF THERMALLY CONDUCTING MATERIAL AS COMPONENT IN THERMAL PASTE OR ADHESIVE

Patent #:	8557667	Issue Dt:	10/15/2013	Application #:	10987484	Filing Dt:	11/12/2004
Publication #:	US20050136606	Pub Dt:	06/23/2005
Title:	SPACER FOR A GATE ELECTRODE HAVING TENSILE STRESS AND A METHOD OF FORMING THE SAME

Patent #:	7130212	Issue Dt:	10/31/2006	Application #:	10987749	Filing Dt:	11/12/2004
Publication #:	US20050111252	Pub Dt:	05/26/2005
Title:	FIELD EFFECT DEVICE WITH A CHANNEL WITH A SWITCHABLE CONDUCTIVITY

Patent #:	7064717	Issue Dt:	06/20/2006	Application #:	10987778	Filing Dt:	11/12/2004
Publication #:	US20050140551	Pub Dt:	06/30/2005
Title:	HIGH PERFORMANCE LOW COST MONOPOLE ANTENNA FOR WIRELESS APPLICATIONS

Patent #:	7198542	Issue Dt:	04/03/2007	Application #:	10987804	Filing Dt:	11/12/2004
Publication #:	US20050142987	Pub Dt:	06/30/2005
Title:	METHOD AND SYSTEM FOR CONTROLLING THE CHEMICAL MECHANICAL POLISHING BY USING A SEISMIC SIGNAL OF A SEISMIC SENSOR

Patent #:	7109086	Issue Dt:	09/19/2006	Application #:	10987827	Filing Dt:	11/12/2004
Publication #:	US20050142828	Pub Dt:	06/30/2005
Title:	TECHNIQUE FOR FORMING A SPACER FOR A LINE ELEMENT BY USING AN ETCH STOP LAYER DEPOSITED BY A HIGHLY DIRECTIONAL DEPOSITION TECHNIQUE

Patent #:	7230334	Issue Dt:	06/12/2007	Application #:	10987985	Filing Dt:	11/12/2004
Publication #:	US20060103011	Pub Dt:	05/18/2006
Title:	SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES HAVING INTEGRATED MICROCHANNEL COOLING MODULES

Patent #:	7544883	Issue Dt:	06/09/2009	Application #:	10988015	Filing Dt:	11/12/2004
Publication #:	US20060102223	Pub Dt:	05/18/2006
Title:	INTEGRATED THERMOELECTRIC COOLING DEVICES AND METHODS FOR FABRICATING SAME

Patent #:	7128135	Issue Dt:	10/31/2006	Application #:	10988215	Filing Dt:	11/12/2004
Publication #:	US20060102324	Pub Dt:	05/18/2006
Title:	COOLING DEVICE USING MULTIPLE FANS AND HEAT SINKS

Patent #:	7458413	Issue Dt:	12/02/2008	Application #:	10988219	Filing Dt:	11/12/2004
Publication #:	US20060102318	Pub Dt:	05/18/2006
Title:	SEMICONDUCTOR CHIP HEAT TRANSFER DEVICE

Patent #:	7613368	Issue Dt:	11/03/2009	Application #:	10988220	Filing Dt:	11/12/2004
Publication #:	US20060105607	Pub Dt:	05/18/2006
Title:	MIXED ELECTRICAL AND OPTICAL LGA INTERPOSER FOR FACILITATING CHIP TO BOARD COMMUNICATIONS BY DUAL SIGNAL TYPES

Patent #:	7098070	Issue Dt:	08/29/2006	Application #:	10990252	Filing Dt:	11/16/2004
Publication #:	US20060105496	Pub Dt:	05/18/2006
Title:	DEVICE AND METHOD FOR FABRICATING DOUBLE-SIDED SOI WAFER SCALE PACKAGE WITH THROUGH VIA CONNECTIONS

Patent #:	7313013	Issue Dt:	12/25/2007	Application #:	10990401	Filing Dt:	11/18/2004
Publication #:	US20060104110	Pub Dt:	05/18/2006
Title:	SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT

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100

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Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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