|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
11161628
|
Filing Dt:
|
08/10/2005
|
Title:
|
DRAM WITH SELF-RESETTING DATA PATH FOR REDUCED POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11161962
|
Filing Dt:
|
08/24/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11162660
|
Filing Dt:
|
09/19/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
ASYMMETRICALLY STRESSED CMOS FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
11162661
|
Filing Dt:
|
09/19/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11162666
|
Filing Dt:
|
09/19/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
METHOD OF FORMING AN INTERCONNECT INCLUDING A DIELECTRIC CAP HAVING A TENSILE STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11162776
|
Filing Dt:
|
09/22/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11162953
|
Filing Dt:
|
09/29/2005
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11163165
|
Filing Dt:
|
10/07/2005
|
Publication #:
|
|
Pub Dt:
|
04/12/2007
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11163687
|
Filing Dt:
|
10/27/2005
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
STRUCTURE AND METHOD OF FABRICATING FINFET WITH BURIED CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11163908
|
Filing Dt:
|
11/03/2005
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
GATE ELECTRODE STRESS CONTROL FOR FINFET PERFORMANCE ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11163948
|
Filing Dt:
|
11/04/2005
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11164214
|
Filing Dt:
|
11/15/2005
|
Publication #:
|
|
Pub Dt:
|
05/17/2007
| | | | |
Title:
|
SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11164216
|
Filing Dt:
|
11/15/2005
|
Publication #:
|
|
Pub Dt:
|
05/17/2007
| | | | |
Title:
|
CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
11164224
|
Filing Dt:
|
11/15/2005
|
Title:
|
METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11164513
|
Filing Dt:
|
11/28/2005
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
VERTICAL SOI TRENCH SONOS CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
11164765
|
Filing Dt:
|
12/05/2005
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
SUSPENDED TRANSMISSION LINE STRUCTURES IN BACK END OF LINE PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
11172473
|
Filing Dt:
|
06/30/2005
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
Title:
|
NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
11174400
|
Filing Dt:
|
07/01/2005
|
Title:
|
SRAM DEVICES UTILIZING TENSILE-STRESSED STRAIN FILMS AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
11179282
|
Filing Dt:
|
07/12/2005
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATE LAYER CONFIGURED FOR INDUCEMENT OF COMPRESSIVE OR EXPANSIVE FORCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
11180416
|
Filing Dt:
|
07/13/2005
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
METHOD FOR ENABLING SCAN OF DEFECTIVE RAM PRIOR TO REPAIR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11180788
|
Filing Dt:
|
07/14/2005
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
ANTIREFLECTIVE COMPOSITION AND PROCESS OF MAKING A LITHOGRAPHIC STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11181152
|
Filing Dt:
|
07/14/2005
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
LOW-IF MULTIPLE MODE TRANSMITTER FRONT END AND CORRESPONDING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11182558
|
Filing Dt:
|
07/15/2005
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
Title:
|
OPTICAL DEVICES HAVING TRANSMISSION ENHANCED BY SURFACE PLASMON MODE RESONANCE, AND THEIR USE IN DATA RECORDING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11183647
|
Filing Dt:
|
07/18/2005
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
METHOD AND STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11184244
|
Filing Dt:
|
07/19/2005
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
POWER GATING SCHEMES IN SOI CIRCUITS IN HYBRID SOI-EPITAXIAL CMOS STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11190360
|
Filing Dt:
|
07/27/2005
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11192153
|
Filing Dt:
|
07/28/2005
|
Title:
|
USING A SHUFFLE UNIT TO IMPLEMENT SHIFT OPERATIONS IN A PROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2009
|
Application #:
|
11192259
|
Filing Dt:
|
07/28/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
VERIFIED COMPUTING ENVIRONMENT FOR PERSONAL INTERNET COMMUNICATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2009
|
Application #:
|
11193660
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11193711
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
METHODOLOGY FOR LAYOUT-BASED MODULATION AND OPTIMIZATION OF NITRIDE LINER STRESS EFFECT IN COMPACT MODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11193868
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
METHODS AND APPARATUS FOR CLOCK SYNCHRONIZATION AND DATA RECOVERY IN A RECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11193878
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
WRITE OPERATIONS FOR PHASE-CHANGE-MATERIAL MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11194233
|
Filing Dt:
|
08/01/2005
|
Title:
|
METHOD AND APPARATUS FOR MODIFYING PROCESS SELECTIVITIES BASED ON PROCESS STATE INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11195426
|
Filing Dt:
|
08/02/2005
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11195566
|
Filing Dt:
|
08/02/2005
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
LOW REFRACTIVE INDEX POLYMERS AS UNDERLAYERS FOR SILICON-CONTAINING PHOTORESISTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
11196073
|
Filing Dt:
|
08/03/2005
|
Title:
|
END OF LINE PERFORMANCE PREDICTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11196434
|
Filing Dt:
|
08/04/2005
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
SONOS MEMORY CELL HAVING HIGH-K DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11199526
|
Filing Dt:
|
08/08/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
TECHNIQUE FOR ENHANCING PROCESS FLEXIBILITY DURING THE FORMATION OF VIAS AND TRENCHES IN LOW-K INTERLAYER DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11200271
|
Filing Dt:
|
08/09/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
PLANAR SUBSTRATE DEVICES INTEGRATED WITH FINFETS AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
11201970
|
Filing Dt:
|
08/11/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR REMOVING BUBBLES FROM A PROCESS LIQUID
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11205713
|
Filing Dt:
|
08/17/2005
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROVIDING ERROR CORRECTION CAPABILITY TO LONGITUDINAL POSITION DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
11205719
|
Filing Dt:
|
08/17/2005
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11208359
|
Filing Dt:
|
08/19/2005
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
RELAXED, LOW-DEFECT SGOI FOR STRAINED SI CMOS APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11209871
|
Filing Dt:
|
08/23/2005
|
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11213231
|
Filing Dt:
|
08/26/2005
|
Publication #:
|
|
Pub Dt:
|
12/22/2005
| | | | |
Title:
|
METHOD OF FABRICATING A FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11216198
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
11216862
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
Title:
|
FORMATION OF CAPACITOR HAVING A FIN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11218198
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR MAKING COPLANAR DIELECTRICALLY-ISOLATED REGIONS OF DIFFERENT SEMICONDUCTOR MATERIALS ON A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11220436
|
Filing Dt:
|
09/07/2005
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING A ROOT CAUSE OF A STATISTICAL PROCESS CONTROL FAILURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11220878
|
Filing Dt:
|
09/06/2005
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR DEPLOYING A LIQUID METAL THERMAL INTERFACE FOR CHIP COOLING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11221118
|
Filing Dt:
|
09/07/2005
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
METHOD OF FORMING A DUAL GATED FINFET GAIN CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
11226534
|
Filing Dt:
|
09/13/2005
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
CIRCUITS AND METHODS FOR IMPLEMENTING TRANSFORMER-COUPLED AMPLIFIERS AT MILLIMETER WAVE FREQUENCIES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
11229188
|
Filing Dt:
|
09/15/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
MULTI-SILICIDE SYSTEM IN INTEGRATED CIRCUIT TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11231647
|
Filing Dt:
|
09/21/2005
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11231919
|
Filing Dt:
|
09/21/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
APPARATUS AND METHODS FOR PACKAGING ANTENNAS WITH INTEGRATED CIRCUIT CHIPS FOR MILLIMETER WAVE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
11233423
|
Filing Dt:
|
09/22/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
METHODS AND APPARATUS FOR MANAGING CLOCK SKEW
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
11234637
|
Filing Dt:
|
09/22/2005
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
BOOT PERFORMANCE OPTIMIZATION FOR HARD DRIVE FOR PERSONAL INTERNET COMMUNICATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2011
|
Application #:
|
11240311
|
Filing Dt:
|
09/30/2005
|
Title:
|
SYSTEM AND METHOD FOR CONTROLLING NETWORK ACCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11240468
|
Filing Dt:
|
10/03/2005
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
Title:
|
CONTACT SPACER FORMATION USING ATOMIC LAYER DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11242723
|
Filing Dt:
|
10/03/2005
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
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Title:
|
RENESTING INTERACTION MAP INTO DESIGN FOR EFFICIENT LONG RANGE CALCULATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
11243360
|
Filing Dt:
|
10/03/2005
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
DATA STORAGE DEVICE AND ASSOCIATED METHOD FOR WRITING DATA TO, AND READING DATA FROM AN UNPATTERNED MAGNETIC LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11244291
|
Filing Dt:
|
10/06/2005
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
HIGH MOBILITY CMOS CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11245824
|
Filing Dt:
|
10/07/2005
|
Publication #:
|
|
Pub Dt:
|
04/12/2007
| | | | |
Title:
|
PROCESS MARGIN USING DISCRETE ASSIST FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
11246830
|
Filing Dt:
|
10/07/2005
|
Publication #:
|
|
Pub Dt:
|
04/12/2007
| | | | |
Title:
|
METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING A MANDREL AND SEMICONDUCTOR STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11248719
|
Filing Dt:
|
10/12/2005
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
CONTROL OF LINER THICKNESS FOR IMPROVING THERMAL CYCLE RELIABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11252384
|
Filing Dt:
|
10/17/2005
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
Title:
|
METHOD OF FABRICATING A MAGNETIC SHIFT REGISTER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11255971
|
Filing Dt:
|
10/24/2005
|
Title:
|
METHOD FOR FORMING SOLDER JOINTS FOR A FLIP CHIP ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11258209
|
Filing Dt:
|
10/26/2005
|
Title:
|
ISOLATION REGION BIRD'S BEAK SUPPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
11259572
|
Filing Dt:
|
10/26/2005
|
Title:
|
SYSTEM FOR CHARACTERIZATION OF LOW-K DIELECTRIC MATERIAL DAMAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11263189
|
Filing Dt:
|
10/31/2005
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
APPARATUS, SYSTEM, AND METHOD FOR ADAPTIVE ASYNCHRONOUS EQUALIZATION USING LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11264446
|
Filing Dt:
|
11/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11266741
|
Filing Dt:
|
11/03/2005
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
METHOD FOR FABRICATING AND BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS FORMATION OF HIGH-K AND LOW-K DIELECTRIC REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11268106
|
Filing Dt:
|
11/07/2005
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
LOW K AND ULTRA LOW K SICOH DIELECTRIC FILMS AND METHODS TO FORM THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11270029
|
Filing Dt:
|
11/08/2005
|
Title:
|
PROTECTION ELEMENT AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11275417
|
Filing Dt:
|
12/30/2005
|
Publication #:
|
|
Pub Dt:
|
07/05/2007
| | | | |
Title:
|
PIXEL ARRAY, IMAGING SENSOR INCLUDING THE PIXEL ARRAY AND DIGITAL CAMERA INCLUDING THE IMAGING SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11275604
|
Filing Dt:
|
01/19/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11276366
|
Filing Dt:
|
02/27/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
MULTI-ORIENTATION SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE, AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11277677
|
Filing Dt:
|
03/28/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11278262
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11278840
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
TIME WEIGHTED MOVING AVERAGE FILTER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11278910
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
PROTECTING SILICON GERMANIUM SIDEWALL WITH SILICON FOR STRAINED SILICON/SILICON MOSFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11278924
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11279283
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GRID CONSTRAINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
11279981
|
Filing Dt:
|
04/17/2006
|
Title:
|
COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11281032
|
Filing Dt:
|
11/17/2005
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
DEPOSITION OF HAFNIUM OXIDE AND/OR ZIRCONIUM OXIDE AND FABRICATION OF PASSIVATED ELECTRONIC STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11286454
|
Filing Dt:
|
11/23/2005
|
Title:
|
DELAY-LOCKED LOOP HAVING A PLURALITY OF LOCK MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11289066
|
Filing Dt:
|
11/29/2005
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
GENERATION OF HARDWARE THERMAL PROFILES FOR A SET OF PROCESSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11290787
|
Filing Dt:
|
11/30/2005
|
Title:
|
THIN FILM GERMANIUM DIODE WITH LOW REVERSE BREAKDOWN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11293774
|
Filing Dt:
|
12/02/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11297856
|
Filing Dt:
|
12/09/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
MEMORY ACCESS REQUEST ARBITRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
11299071
|
Filing Dt:
|
12/09/2005
|
Title:
|
THERMAL THROTTLING OF PERIPHERAL COMPONENTS IN A PROCESSING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11303103
|
Filing Dt:
|
12/16/2005
|
Title:
|
METHOD AND APPARATUS FOR HIERARCHICAL PROCESS CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2009
|
Application #:
|
11303715
|
Filing Dt:
|
12/16/2005
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
DUAL METAL GATE SELF-ALIGNED INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11306709
|
Filing Dt:
|
01/09/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11306746
|
Filing Dt:
|
01/10/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT COMB CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
11306827
|
Filing Dt:
|
01/12/2006
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
Title:
|
METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11306930
|
Filing Dt:
|
01/17/2006
|
Publication #:
|
|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
METHOD OF MAKING A SEMICONDUCTOR STRUCTURE WITH A PLATING ENHANCEMENT LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11307404
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11307481
|
Filing Dt:
|
02/09/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11307642
|
Filing Dt:
|
02/15/2006
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
STRUCTURE AND METHOD OF CHEMICALLY FORMED ANCHORED METALLIC VIAS
|
|