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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 3 of 85
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Patent #:	6553559	Issue Dt:	04/22/2003	Application #:	09754910	Filing Dt:	01/05/2001
Publication #:	US20020091985	Pub Dt:	07/11/2002
Title:	METHOD TO DETERMINE OPTICAL PROXIMITY CORRECTION AND ASSIST FEATURE RULES WHICH ACCOUNT FOR VARIATIONS IN MASK DIMENSIONS

Patent #:	6621281	Issue Dt:	09/16/2003	Application #:	09755012	Filing Dt:	01/05/2001
Title:	SOI DIE ANALYSIS OF CIRCUITRY LOGIC STATES VIA COUPLING THROUGH THE INSULATOR

Patent #:	6831339	Issue Dt:	12/14/2004	Application #:	09755164	Filing Dt:	01/08/2001
Publication #:	US20020090773	Pub Dt:	07/11/2002
Title:	ALUMINUM NITRIDE AND ALUMINUM OXIDE/ALUMINUM NITRIDE HETEROSTRUCTURE GATE DIELECTRIC STACK BASED FIELD EFFECT TRANSISTORS AND METHOD FOR FORMING SAME

Patent #:	6472912	Issue Dt:	10/29/2002	Application #:	09755216	Filing Dt:	01/04/2001
Title:	DEVICE FOR POWER SUPPLY DETECTION AND POWER ON RESET

Patent #:	6657261	Issue Dt:	12/02/2003	Application #:	09757317	Filing Dt:	01/09/2001
Publication #:	US20020090768	Pub Dt:	07/11/2002
Title:	GROUND-PLANE DEVICE WITH BACK OXIDE TOPOGRAPHY

Patent #:	6849871	Issue Dt:	02/01/2005	Application #:	09757965	Filing Dt:	01/10/2001
Publication #:	US20020089038	Pub Dt:	07/11/2002
Title:	FULLY-DEPLETED-COLLECTOR SILICON-ON-INSULATOR (SOI) BIPOLAR TRANSISTOR USEFUL ALONE OR IN SOI BICMOS

Patent #:	6334230	Issue Dt:	01/01/2002	Application #:	09758989	Filing Dt:	01/12/2001
Title:	Wafer cleaning apparatus

Patent #:	6578190	Issue Dt:	06/10/2003	Application #:	09759013	Filing Dt:	01/11/2001
Publication #:	US20020091986	Pub Dt:	07/11/2002
Title:	PROCESS WINDOW BASED OPTICAL PROXIMITY CORRECTION OF LITHOGRAPHIC IMAGES

Patent #:	6403500	Issue Dt:	06/11/2002	Application #:	09760241	Filing Dt:	01/12/2001
Title:	CROSS-SHAPED RESIST DISPENSING SYSTEM AND METHOD

Patent #:	6479898	Issue Dt:	11/12/2002	Application #:	09760421	Filing Dt:	01/11/2001
Title:	DIELECTRIC TREATMENT IN INTEGRATED CIRCUIT INTERCONNECTS

Patent #:	7039146	Issue Dt:	05/02/2006	Application #:	09760560	Filing Dt:	01/16/2001
Publication #:	US20020135408	Pub Dt:	09/26/2002
Title:	METHOD AND INTERFACE FOR GLITCH-FREE CLOCK SWITCHING

Patent #:	6478212	Issue Dt:	11/12/2002	Application #:	09760955	Filing Dt:	01/16/2001
Title:	BOND PAD STRUCTURE AND METHOD FOR REDUCED DOWNWARD FORCE WIREBONDING

Patent #:	6486415	Issue Dt:	11/26/2002	Application #:	09761124	Filing Dt:	01/16/2001
Publication #:	US20020092676	Pub Dt:	07/18/2002
Title:	COMPLIANT LAYER FOR ENCAPSULATED CLOUMNS

Patent #:	6523159	Issue Dt:	02/18/2003	Application #:	09761464	Filing Dt:	01/16/2001
Publication #:	US20020095647	Pub Dt:	07/18/2002
Title:	METHOD FOR ADDING DECOUPLING CAPACITANCE DURING INTEGRATED CIRCUIT DESIGN

Patent #:	6545869	Issue Dt:	04/08/2003	Application #:	09764048	Filing Dt:	01/17/2001
Publication #:	US20020141160	Pub Dt:	10/03/2002
Title:	ADJUSTING FILLET GEOMETRY TO COUPLE A HEAT SPREADER TO A CHIP CARRIER

Patent #:	6512675	Issue Dt:	01/28/2003	Application #:	09764132	Filing Dt:	01/19/2001
Title:	HEAT SINK GROUNDED TO A GROUNDED PACKAGE LID

Patent #:	6541349	Issue Dt:	04/01/2003	Application #:	09764674	Filing Dt:	01/18/2001
Publication #:	US20020094649	Pub Dt:	07/18/2002
Title:	METHOD OF FORMING A SHALLOW TRENCH ISOLATION USING NON-CONFORMAL DIELECTRIC MATERIAL AND PLANARIZATRION

Patent #:	6541166	Issue Dt:	04/01/2003	Application #:	09766005	Filing Dt:	01/18/2001
Publication #:	US20020094482	Pub Dt:	07/18/2002
Title:	METHOD AND APPARATUS FOR LITHOGRAPHICALLY PRINTING TIGHTLY NESTED AND ISOLATED DEVICE FEATURES USING MULTIPLE MASK EXPOSURES

Patent #:	6534995	Issue Dt:	03/18/2003	Application #:	09766481	Filing Dt:	01/19/2001
Title:	CIRCUIT FOR DETECTING A COOLING DEVICE IN A COMPUTER SYSTEM

Patent #:	6365422	Issue Dt:	04/02/2002	Application #:	09766737	Filing Dt:	01/22/2001
Title:	Automated variation of stepper exposure dose based upon across wafer variations in device characteristics, and system for accomplishing same

Patent #:	6434076	Issue Dt:	08/13/2002	Application #:	09766799	Filing Dt:	01/22/2001
Publication #:	US20020097624	Pub Dt:	07/25/2002
Title:	REFRESH CONTROL CIRCUIT FOR LOW-POWER SRAM APPLICATIONS

Patent #:	6648979	Issue Dt:	11/18/2003	Application #:	09768833	Filing Dt:	01/24/2001
Publication #:	US20020096191	Pub Dt:	07/25/2002
Title:	APPARATUS AND METHOD FOR WAFER CLEANING

Patent #:	6774010	Issue Dt:	08/10/2004	Application #:	09769170	Filing Dt:	01/25/2001
Publication #:	US20020096717	Pub Dt:	07/25/2002
Title:	TRANSFERABLE DEVICE-CONTAINING LAYER FOR SILICON-ON-INSULATOR APPLICATIONS

Patent #:	6674102	Issue Dt:	01/06/2004	Application #:	09769640	Filing Dt:	01/25/2001
Publication #:	US20020096693	Pub Dt:	07/25/2002
Title:	STI PULL-DOWN TO CONTROL SIGE FACET GROWTH

Patent #:	6465870	Issue Dt:	10/15/2002	Application #:	09769667	Filing Dt:	01/25/2001
Publication #:	US20020096742	Pub Dt:	07/25/2002
Title:	ESD ROBUST SILICON GERMANIUM TRANSISTOR WITH EMITTER NP-BLOCK MASK EXTRINSIC BASE BALLASTING RESISTOR WITH DOPED FACET REGION

Patent #:	6424221	Issue Dt:	07/23/2002	Application #:	09770065	Filing Dt:	01/25/2001
Publication #:	US20020024385	Pub Dt:	02/28/2002
Title:	PROGRAMMABLE GAIN AMPLIFIER FOR USE IN DATA NETWORK

Patent #:	6448654	Issue Dt:	09/10/2002	Application #:	09770468	Filing Dt:	01/29/2001
Title:	ULTRA THIN ETCH STOP LAYER FOR DAMASCENE PROCESS

Patent #:	6472231	Issue Dt:	10/29/2002	Application #:	09770469	Filing Dt:	01/29/2001
Title:	DIELECTRIC LAYER WITH TREATED TOP SURFACE FORMING AN ETCH STOP LAYER AND METHOD OF MAKING THE SAME

Patent #:	6623893	Issue Dt:	09/23/2003	Application #:	09770730	Filing Dt:	01/26/2001
Title:	PELLICLE FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A PELLICLE

Patent #:	6544693	Issue Dt:	04/08/2003	Application #:	09770733	Filing Dt:	01/26/2001
Publication #:	US20020127477	Pub Dt:	09/12/2002
Title:	PELLICLE FOR USE IN SMALL WAVELENGTH LITHOGRAPHY AND A METHOD FOR MAKING SUCH A PELLICLE

Patent #:	6713791	Issue Dt:	03/30/2004	Application #:	09770788	Filing Dt:	01/26/2001
Publication #:	US20020100918	Pub Dt:	08/01/2002
Title:	T-RAM ARRAY HAVING A PLANAR CELL STRUCTURE AND METHOD FOR FABRICATING THE SAME

Patent #:	6509134	Issue Dt:	01/21/2003	Application #:	09771149	Filing Dt:	01/26/2001
Publication #:	US20020146638	Pub Dt:	10/10/2002
Title:	NORBORNENE FLUOROACRYLATE COPOLYMERS AND PROCESS FOR USE THEREOF

Patent #:	6593035	Issue Dt:	07/15/2003	Application #:	09771236	Filing Dt:	01/26/2001
Title:	PELLICLE FOR USE IN SMALL WAVELENGTH LITHOGRAPHY AND A METHOD FOR MAKING SUCH A PELLICLE USING A SILICON LAYER

Patent #:	6730452	Issue Dt:	05/04/2004	Application #:	09771261	Filing Dt:	01/26/2001
Publication #:	US20020146639	Pub Dt:	10/10/2002
Title:	LITHOGRAPHIC PHOTORESIST COMPOSITION AND PROCESS FOR ITS USE

Patent #:	6548219	Issue Dt:	04/15/2003	Application #:	09771262	Filing Dt:	01/26/2001
Publication #:	US20020102490	Pub Dt:	08/01/2002
Title:	SUBSTITUTED NORBORNENE FLUOROACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS

Patent #:	6589713	Issue Dt:	07/08/2003	Application #:	09771820	Filing Dt:	01/29/2001
Title:	PROCESS FOR REDUCING THE PITCH OF CONTACT HOLES, VIAS, AND TRENCH STRUCTURES IN INTEGRATED CIRCUITS

Patent #:	6500751	Issue Dt:	12/31/2002	Application #:	09772205	Filing Dt:	01/29/2001
Publication #:	US20020146900	Pub Dt:	10/10/2002
Title:	METHOD OF FORMING RECESSED THIN FILM LANDING PAD STRUCTURE

Patent #:	6580136	Issue Dt:	06/17/2003	Application #:	09772345	Filing Dt:	01/30/2001
Publication #:	US20020100945	Pub Dt:	08/01/2002
Title:	METHOD FOR DELINEATION OF EDRAM SUPPORT DEVICE NOTCHED GATE

Patent #:	6566680	Issue Dt:	05/20/2003	Application #:	09772610	Filing Dt:	01/30/2001
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR

Patent #:	6538307	Issue Dt:	03/25/2003	Application #:	09772889	Filing Dt:	01/31/2001
Title:	PACKAGING SUBSTRATE COMPRISING STAGGERED VIAS

Patent #:	6510120	Issue Dt:	01/21/2003	Application #:	09773323	Filing Dt:	01/31/2001
Publication #:	US20020101795	Pub Dt:	08/01/2002
Title:	METHOD FOR WRITING AND/OR ERASING HIGH DENSITY DATA ON A MEDIA

Patent #:	6599839	Issue Dt:	07/29/2003	Application #:	09773906	Filing Dt:	02/02/2001
Title:	PLASMA ETCH PROCESS FOR NONHOMOGENOUS FILM

Patent #:	6501555	Issue Dt:	12/31/2002	Application #:	09773954	Filing Dt:	02/01/2001
Title:	OPTICAL TECHNIQUE TO DETECT ETCH PROCESS TERMINATION

Patent #:	6426265	Issue Dt:	07/30/2002	Application #:	09774126	Filing Dt:	01/30/2001
Publication #:	US20020100917	Pub Dt:	08/01/2002
Title:	INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY

Patent #:	6380589	Issue Dt:	04/30/2002	Application #:	09774138	Filing Dt:	01/30/2001
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR SRAM CELL

Patent #:	6501171	Issue Dt:	12/31/2002	Application #:	09774152	Filing Dt:	01/30/2001
Publication #:	US20020100969	Pub Dt:	08/01/2002
Title:	FLIP CHIP PACKAGE WITH IMPROVED CAP DESIGN AND PROCESS FOR MAKING THEREOF

Patent #:	6738535	Issue Dt:	05/18/2004	Application #:	09774489	Filing Dt:	01/31/2001
Publication #:	US20020138249	Pub Dt:	09/26/2002
Title:	HEAD-MOUNTED DISPLAY CONTENT TRANSFORMER

Patent #:	6475929	Issue Dt:	11/05/2002	Application #:	09774708	Filing Dt:	02/01/2001
Title:	METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE WITH TREATMENT TO SACRIFICIAL STOP LAYER PRODUCING DIFFUSION TO AN ADJACENT LOW-K DIELECTRIC LAYER LOWERING THE CONSTANT

Patent #:	6365466	Issue Dt:	04/02/2002	Application #:	09774939	Filing Dt:	01/31/2001
Title:	Dual gate process using self-assembled molecular layer

Patent #:	6920088	Issue Dt:	07/19/2005	Application #:	09774943	Filing Dt:	01/31/2001
Publication #:	US20020101673	Pub Dt:	08/01/2002
Title:	ASSEMBLY FOR WRITING AND / OR ERASING HIGH DENSITY DATA ON A MEDIA

Patent #:	6920289	Issue Dt:	07/19/2005	Application #:	09775374	Filing Dt:	02/01/2001
Publication #:	US20020101638	Pub Dt:	08/01/2002
Title:	SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES

Patent #:	6738522	Issue Dt:	05/18/2004	Application #:	09776077	Filing Dt:	02/01/2001
Title:	EFFICIENT SIMD QUANTIZATION METHOD

Patent #:	6701406	Issue Dt:	03/02/2004	Application #:	09776339	Filing Dt:	02/02/2001
Title:	PCI AND MII COMPATIBLE HOME PHONELINE NETWORKING ALLIANCE (HPNA) INTERFACE DEVICE

Patent #:	6525391	Issue Dt:	02/25/2003	Application #:	09776748	Filing Dt:	02/06/2001
Title:	NICKEL SILICIDE PROCESS USING STARVED SILICON DIFFUSION BARRIER

Patent #:	6579149	Issue Dt:	06/17/2003	Application #:	09777548	Filing Dt:	02/06/2001
Publication #:	US20020106972	Pub Dt:	08/08/2002
Title:	SUPPORT AND ALIGNMENT DEVICE FOR ENABLING CHEMICAL MECHANICAL POLISHING RINSE AND FILM MEASUREMENTS

Patent #:	6495402	Issue Dt:	12/17/2002	Application #:	09777637	Filing Dt:	02/06/2001
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE HAVING SOURCE/DRAIN SILICON-GERMANIUM REGIONS AND METHOD OF MANUFACTURE

Patent #:	6656830	Issue Dt:	12/02/2003	Application #:	09777695	Filing Dt:	02/07/2001
Title:	DUAL DAMASCENE WITH SILICON CARBIDE MIDDLE ETCH STOP LAYER/ARC

Patent #:	6465889	Issue Dt:	10/15/2002	Application #:	09778109	Filing Dt:	02/07/2001
Title:	SILICON CARBIDE BARC IN DUAL DAMASCENE PROCESSING

Patent #:	6686630	Issue Dt:	02/03/2004	Application #:	09778335	Filing Dt:	02/07/2001
Publication #:	US20020105039	Pub Dt:	08/08/2002
Title:	DAMASCENE DOUBLE-GATE MOSFET STRUCTURE AND ITS FABRICATION METHOD

Patent #:	6581023	Issue Dt:	06/17/2003	Application #:	09778529	Filing Dt:	02/07/2001
Title:	ACCURATE CONTACT CRITICAL DIMENSION MEASUREMENT USING VARIABLE THRESHOLD METHOD

Patent #:	6576376	Issue Dt:	06/10/2003	Application #:	09778586	Filing Dt:	02/07/2001
Title:	TRI-TONE MASK PROCESS FOR DENSE AND ISOLATED PATTERNS

Patent #:	6551885	Issue Dt:	04/22/2003	Application #:	09779986	Filing Dt:	02/09/2001
Title:	LOW TEMPERATURE PROCESS FOR A THIN FILM TRANSISTOR

Patent #:	6403434	Issue Dt:	06/11/2002	Application #:	09779987	Filing Dt:	02/09/2001
Title:	PROCESS FOR MANUFACTURING MOS TRANSISTORS HAVING ELEVATED SOURCE AND DRAIN REGIONS AND A HIGH-K GATE DIELECTRIC

Patent #:	6673524	Issue Dt:	01/06/2004	Application #:	09780275	Filing Dt:	02/09/2001
Publication #:	US20020146648	Pub Dt:	10/10/2002
Title:	ATTENUATING EXTREME ULTRAVIOLET (EUV) PHASE-SHIFTING MASK FABRICATION METHOD

Patent #:	6458679	Issue Dt:	10/01/2002	Application #:	09780454	Filing Dt:	02/12/2001
Title:	METHOD OF MAKING A SILICIDE STOP LAYER IN A DAMASCENE SEMICONDUCTOR STRUCTURE

Patent #:	6795951	Issue Dt:	09/21/2004	Application #:	09780558	Filing Dt:	02/09/2001
Publication #:	US20020112195	Pub Dt:	08/15/2002
Title:	METHOD AND SYSTEM FOR FAULT-TOLERANT STATIC TIMING ANALYSIS

Patent #:	6534843	Issue Dt:	03/18/2003	Application #:	09781014	Filing Dt:	02/10/2001
Publication #:	US20020109204	Pub Dt:	08/15/2002
Title:	HIGH Q INDUCTOR WITH FARADAY SHIELD AND DIELECTRIC WELL BURIED IN SUBSTRATE

Patent #:	6495437	Issue Dt:	12/17/2002	Application #:	09781039	Filing Dt:	02/09/2001
Title:	LOW TEMPERATURE PROCESS TO LOCALLY FORM HIGH-K GATE DIELECTRICS

Patent #:	6534863	Issue Dt:	03/18/2003	Application #:	09781121	Filing Dt:	02/09/2001
Publication #:	US20020111010	Pub Dt:	08/15/2002
Title:	COMMON BALL-LIMITING METALLURGY FOR I/O SITES

Patent #:	6380057	Issue Dt:	04/30/2002	Application #:	09781225	Filing Dt:	02/13/2001
Title:	ENHANCEMENT OF NICKEL SILICIDE FORMATION BY USE OF NICKEL PRE-AMORPHIZING IMPLANT

Patent #:	6372673	Issue Dt:	04/16/2002	Application #:	09781256	Filing Dt:	02/13/2001
Title:	SILICON-STARVED NITRIDE SPACER DEPOSITION

Patent #:	6380043	Issue Dt:	04/30/2002	Application #:	09781357	Filing Dt:	02/12/2001
Title:	LOW TEMPERATURE PROCESS TO FORM ELEVATED DRAIN AND SOURCE OF A FIELD EFFECT TRANSISTOR HAVING HIGH-K GATE DIELECTRIC

Patent #:	6406951	Issue Dt:	06/18/2002	Application #:	09781364	Filing Dt:	02/12/2001
Title:	FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN IN SOI TECHNOLOGY

Patent #:	6395589	Issue Dt:	05/28/2002	Application #:	09781783	Filing Dt:	02/12/2001
Title:	FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH HIGH-K GATE DIELECTRIC IN SOI TECHNOLOGY

Patent #:	6641747	Issue Dt:	11/04/2003	Application #:	09783204	Filing Dt:	02/15/2001
Title:	METHOD AND APPARATUS FOR DETERMINING AN ETCH ENDPOINT

Patent #:	6727558	Issue Dt:	04/27/2004	Application #:	09784790	Filing Dt:	02/15/2001
Title:	CHANNEL ISOLATION USING DIELECTRIC ISOLATION STRUCTURES

Patent #:	6440826	Issue Dt:	08/27/2002	Application #:	09785176	Filing Dt:	02/20/2001
Title:	NISI CONTACTING EXTENSIONS OF ACTIVE REGIONS

Patent #:	6498372	Issue Dt:	12/24/2002	Application #:	09785432	Filing Dt:	02/16/2001
Publication #:	US20020113267	Pub Dt:	08/22/2002
Title:	CONDUCTIVE COUPLING OF ELECTRICAL STRUCTURES TO A SEMICONDUCTOR DEVICE LOCATED UNDER A BURIED OXIDE LAYER

Patent #:	6465361	Issue Dt:	10/15/2002	Application #:	09785444	Filing Dt:	02/20/2001
Title:	METHOD FOR PREVENTING DAMAGE OF LOW-K DIELECTRICS DURING PATTERNING

Patent #:	6653045	Issue Dt:	11/25/2003	Application #:	09785609	Filing Dt:	02/16/2001
Publication #:	US20020115017	Pub Dt:	08/22/2002
Title:	RADIATION SENSITIVE SILICON-CONTAINING NEGATIVE RESISTS AND USE THEREOF

Patent #:	6727922	Issue Dt:	04/27/2004	Application #:	09788635	Filing Dt:	02/21/2001
Publication #:	US20020145630	Pub Dt:	10/10/2002
Title:	GUI FOR REPRESENTING ENTITY MATCHES UTILIZING GRAPHICAL TRANSITIONS PERFORMED DIRECTLY ON THE MATCHING OBJECT

Patent #:	6745373	Issue Dt:	06/01/2004	Application #:	09788925	Filing Dt:	02/20/2001
Publication #:	US20020116690	Pub Dt:	08/22/2002
Title:	METHOD FOR INSERTION OF TEST POINTS INTO INTEGRATED CIRCUIT LOGIC DESIGNS

Patent #:	6551114	Issue Dt:	04/22/2003	Application #:	09789141	Filing Dt:	02/20/2001
Publication #:	US20020115325	Pub Dt:	08/22/2002
Title:	SEMICONDUCTOR DEVICE HAVING SIGNAL CONTACTS AND HIGH CURRENT POWER CONTACTS

Patent #:	6372644	Issue Dt:	04/16/2002	Application #:	09789765	Filing Dt:	02/22/2001
Title:	HYDROGEN PASSIVATED SILICON NITRIDE SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING

Patent #:	6615098	Issue Dt:	09/02/2003	Application #:	09789871	Filing Dt:	02/21/2001
Title:	METHOD AND APPARATUS FOR CONTROLLING A TOOL USING A BASELINE CONTROL SCRIPT

Patent #:	6475890	Issue Dt:	11/05/2002	Application #:	09789939	Filing Dt:	02/12/2001
Title:	FABRICATION OF A FIELD EFFECT TRANSISTOR WITH AN UPSIDE DOWN T-SHAPED SEMICONDUCTOR PILLAR IN SOI TECHNOLOGY

Patent #:	6444578	Issue Dt:	09/03/2002	Application #:	09791024	Filing Dt:	02/21/2001
Publication #:	US20020115262	Pub Dt:	08/22/2002
Title:	SELF-ALIGNED SILICIDE PROCESS FOR REDUCTION OF SI CONSUMPTION IN SHALLOW JUNCTION AND THIN SOI ELECTRONIC DEVICES

Patent #:	6785586	Issue Dt:	08/31/2004	Application #:	09791981	Filing Dt:	02/23/2001
Title:	METHOD AND APPARATUS FOR ADAPTIVELY SCHEDULING TOOL MAINTENANCE

Patent #:	6380590	Issue Dt:	04/30/2002	Application #:	09792139	Filing Dt:	02/22/2001
Title:	SOI CHIP HAVING MULTIPLE THRESHOLD VOLTAGE MOSFETS BY USING MULTIPLE CHANNEL MATERIALS AND METHOD OF FABRICATING SAME

Patent #:	6462381	Issue Dt:	10/08/2002	Application #:	09792146	Filing Dt:	02/22/2001
Title:	SILICON-ON-INSULATOR (SOI) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE WITH BACKSIDE CONTACT OPENING

Patent #:	6376350	Issue Dt:	04/23/2002	Application #:	09792766	Filing Dt:	02/23/2001
Title:	Method of forming low resistance gate electrode

Patent #:	6475869	Issue Dt:	11/05/2002	Application #:	09793055	Filing Dt:	02/26/2001
Title:	METHOD OF FORMING A DOUBLE GATE TRANSISTOR HAVING AN EPITAXIAL SILICON/GERMANIUM CHANNEL REGION

Patent #:	6610456	Issue Dt:	08/26/2003	Application #:	09794466	Filing Dt:	02/26/2001
Publication #:	US20020164538	Pub Dt:	11/07/2002
Title:	FLUORINE-CONTAINING STYRENE ACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS

Patent #:	6410371	Issue Dt:	06/25/2002	Application #:	09794884	Filing Dt:	02/26/2001
Title:	METHOD OF FABRICATION OF SEMICONDUCTOR-ON-INSULATOR (SOI) WAFER HAVING A SI/SIGE/SI ACTIVE LAYER

Patent #:	6445016	Issue Dt:	09/03/2002	Application #:	09795159	Filing Dt:	02/28/2001
Title:	SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION

Patent #:	6677680	Issue Dt:	01/13/2004	Application #:	09795429	Filing Dt:	02/28/2001
Publication #:	US20020117754	Pub Dt:	08/29/2002
Title:	HYBRID LOW-K INTERCONNECT STRUCTURE COMPRISED OF 2 SPIN-ON DIELECTRIC MATERIALS

Patent #:	6710450	Issue Dt:	03/23/2004	Application #:	09795430	Filing Dt:	02/28/2001
Publication #:	US20020117737	Pub Dt:	08/29/2002
Title:	INTERCONNECT STRUCTURE WITH PRECISE CONDUCTOR RESISTANCE AND METHOD TO FORM SAME

Patent #:	6512295	Issue Dt:	01/28/2003	Application #:	09797078	Filing Dt:	03/01/2001
Publication #:	US20020121694	Pub Dt:	09/05/2002
Title:	COUPLED-CAP FLIP CHIP BGA PACKAGE WITH IMPROVED CAP DESIGN FOR REDUCED INTERFACIAL STRESSES

Patent #:	6577515	Issue Dt:	06/10/2003	Application #:	09798550	Filing Dt:	03/02/2001
Publication #:	US20030031036	Pub Dt:	02/13/2003
Title:	ASYMMETRIC POWER SUPPLY INCLUDING A FAST RESPONSE CONVERTER

100

Patent #:	6573480	Issue Dt:	06/03/2003	Application #:	09800166	Filing Dt:	03/06/2001
Title:	USE OF THERMAL FLOW TO REMOVE SIDE LOBES

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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