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13111741
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Filing Dt:
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05/19/2011
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11/22/2012
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Title:
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FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
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08/12/2014
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13112356
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05/20/2011
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10/06/2011
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HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS
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03/04/2014
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13113698
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05/23/2011
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12/01/2011
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TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN DIAMOND-SHAPED CAVITIES BASED ON A PRE-AMORPHIZATION
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12/03/2013
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13113901
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05/23/2011
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11/29/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
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07/16/2013
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13114116
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05/24/2011
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01/05/2012
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Title:
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SEMICONDUCTOR DEVICE COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND PRECISION EFUSES FORMED IN THE ACTIVE SEMICONDUCTOR MATERIAL
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10/08/2013
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13114283
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05/24/2011
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11/29/2012
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Title:
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STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY
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10/01/2013
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13114543
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05/24/2011
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11/29/2012
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Title:
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DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE
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12/17/2013
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13115192
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05/25/2011
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02/02/2012
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Title:
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INCREASED STABILITY OF A COMPLEX MATERIAL STACK IN A SEMICONDUCTOR DEVICE BY PROVIDING FLUORINE ENRICHED INTERFACES
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05/13/2014
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13115270
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05/25/2011
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Pub Dt:
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11/29/2012
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Title:
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METHOD OF PROTECTING STI STRUCTURES FROM EROSION DURING PROCESSING OPERATIONS
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09/09/2014
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13115428
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05/25/2011
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11/29/2012
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Title:
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PMOS THRESHOLD VOLTAGE CONTROL BY GERMANIUM IMPLANTATION
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08/20/2013
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13115823
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05/25/2011
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11/29/2012
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Title:
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TECHNIQUE FOR VERIFYING THE MICROSTRUCTURE OF LEAD-FREE INTERCONNECTS IN SEMICONDUCTOR ASSEMBLIES
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05/05/2015
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13116672
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05/26/2011
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11/29/2012
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Title:
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METHOD OF FORMING CONTACTS FOR DEVICES WITH MULTIPLE STRESS LINERS
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10/01/2013
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13116961
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05/26/2011
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11/29/2012
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Title:
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SEMICONDUCTOR-BASED TEST DEVICE THAT IMPLEMENTS RANDOM LOGIC FUNCTIONS
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06/04/2013
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13117249
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05/27/2011
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Pub Dt:
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02/02/2012
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Title:
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TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS FORMED IN A LATE STAGE
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09/09/2014
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13118881
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05/31/2011
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12/06/2012
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Title:
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HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY
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06/17/2014
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13126546
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06/06/2011
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Pub Dt:
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11/10/2011
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Title:
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METHOD, DEVICE, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A REPRESENTATION OF A SIGNAL
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04/16/2013
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13149108
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05/31/2011
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Pub Dt:
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12/06/2012
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Title:
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ELECTRICALLY PROGRAMMABLE METAL FUSE
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01/07/2014
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13149797
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05/31/2011
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12/06/2012
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Title:
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BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH
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12/03/2013
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13150612
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06/01/2011
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12/06/2012
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Title:
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STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE
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01/15/2013
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13150705
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06/01/2011
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09/22/2011
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Title:
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POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL
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02/19/2013
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13151295
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06/02/2011
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Pub Dt:
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12/06/2012
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Title:
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METHOD FOR PERFORMING A PARALLEL STATIC TIMING ANALYSIS USING THREAD-SPECIFIC SUB-GRAPHS
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02/19/2013
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13151313
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06/02/2011
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12/06/2012
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Title:
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METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION
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12/02/2014
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13151525
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06/02/2011
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Pub Dt:
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09/22/2011
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Title:
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HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
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10/22/2013
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13151898
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06/02/2011
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12/06/2012
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INTEGRATED CIRCUIT HAVING ELECTROSTATIC DISCHARGE PROTECTION
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08/13/2013
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13152350
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06/03/2011
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Pub Dt:
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09/22/2011
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Title:
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DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
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02/21/2012
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13153051
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06/03/2011
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Pub Dt:
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10/20/2011
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Title:
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SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
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12/31/2013
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13153381
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06/03/2011
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Pub Dt:
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03/22/2012
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Title:
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ANNEALING THIN FILMS
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07/01/2014
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13153806
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06/06/2011
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09/29/2011
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Title:
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EMBEDDED DRAM INTEGRATED CIRCUITS WITH EXTREMELY THIN SILICON-ON-INSULATOR PASS TRANSISTORS
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04/15/2014
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13154521
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06/07/2011
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12/13/2012
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Title:
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Method of Removing Gate Cap Materials While Protecting Active Area
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01/27/2015
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13154548
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06/07/2011
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12/13/2012
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BURIED SUBLEVEL METALLIZATIONS FOR IMPROVED TRANSISTOR DENSITY
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03/04/2014
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13154578
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06/07/2011
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12/13/2012
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Metal Gate Stack Formation for Replacement Gate Technology
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05/13/2014
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13154754
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06/07/2011
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02/02/2012
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Title:
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REDUCED TOPOGRAPHY IN ISOLATION REGIONS OF A SEMICONDUCTOR DEVICE BY APPLYING A DEPOSITION/ETCH SEQUENCE PRIOR TO FORMING THE INTERLAYER DIELECTRIC
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07/29/2014
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13154905
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06/07/2011
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12/13/2012
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Title:
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METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
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09/17/2013
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13155878
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06/08/2011
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12/13/2012
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FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION
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02/24/2015
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13156935
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06/09/2011
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Pub Dt:
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12/13/2012
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Title:
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ON-CHIP SLOW-WAVE THROUGH-SILICON VIA COPLANAR WAVEGUIDE STRUCTURES, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
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07/08/2014
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13157968
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06/10/2011
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12/13/2012
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Title:
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TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY
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01/28/2014
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13157980
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06/10/2011
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12/13/2012
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Title:
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Rapid Estimation of Temperature Rise in Wires Due to Joule Heating
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03/26/2013
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13158048
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06/10/2011
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10/06/2011
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Title:
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CHIP PACKAGE WITH CHANNEL STIFFENER FRAME
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10/08/2013
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13158079
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06/10/2011
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12/13/2012
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Title:
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PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR
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03/04/2014
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13158114
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06/10/2011
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12/13/2012
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Title:
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COPPER INTERCONNECT WITH METAL HARDMASK REMOVAL
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Issue Dt:
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09/10/2013
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13158419
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06/12/2011
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Pub Dt:
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12/13/2012
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Title:
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COMPLEMENTARY BIPOLAR INVERTER
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09/03/2013
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13158420
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06/12/2011
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12/13/2012
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Title:
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COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A LOW-VOLTAGE CMOS PLATFORM
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01/29/2013
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13158562
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06/13/2011
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12/13/2012
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Title:
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SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE
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