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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 35 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
Issue Dt:
06/03/2014
Application #:
13076881
Filing Dt:
03/31/2011
Publication #:
Pub Dt:
10/04/2012
Title:
CONTROLLED ELECTROPLATED SOLDER BUMPS
2
Patent #:
Issue Dt:
05/17/2016
Application #:
13077765
Filing Dt:
03/31/2011
Publication #:
Pub Dt:
10/04/2012
Title:
MULTI-CORE FIBER OPTICAL COUPLING ELEMENTS
3
Patent #:
Issue Dt:
01/07/2014
Application #:
13079341
Filing Dt:
04/04/2011
Publication #:
Pub Dt:
11/03/2011
Title:
Reduced STI Loss for Superior Surface Planarity of Embedded Stressors in Densely Packed Semiconductor Devices
4
Patent #:
Issue Dt:
07/09/2013
Application #:
13080084
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
10/11/2012
Title:
Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure
5
Patent #:
Issue Dt:
10/30/2012
Application #:
13080326
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
07/28/2011
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
6
Patent #:
Issue Dt:
10/07/2014
Application #:
13080390
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
10/11/2012
Title:
SEMICONDUCTOR NANOWIRE STRUCTURE REUSING SUSPENSION PADS
7
Patent #:
Issue Dt:
07/31/2012
Application #:
13080716
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
07/28/2011
Title:
METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
8
Patent #:
Issue Dt:
05/07/2013
Application #:
13080962
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
07/28/2011
Title:
DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS
9
Patent #:
Issue Dt:
05/27/2014
Application #:
13082298
Filing Dt:
04/07/2011
Publication #:
Pub Dt:
10/11/2012
Title:
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
10
Patent #:
Issue Dt:
05/28/2013
Application #:
13083803
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
10/11/2012
Title:
THERMAL EXPANSION CONTROL EMPLOYING PLATELET FILLERS
11
Patent #:
Issue Dt:
12/11/2012
Application #:
13084088
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
08/04/2011
Title:
PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR
12
Patent #:
Issue Dt:
02/25/2014
Application #:
13084435
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
10/11/2012
Title:
ROBOTIC DEVICE FOR SUBSTRATE TRANSFER APPLICATIONS
13
Patent #:
Issue Dt:
10/08/2013
Application #:
13085154
Filing Dt:
04/12/2011
Publication #:
Pub Dt:
10/18/2012
Title:
BIODEGRADABLE SMART SENSOR FOR MESH NETWORK APPLICATIONS
14
Patent #:
Issue Dt:
09/16/2014
Application #:
13085511
Filing Dt:
04/13/2011
Publication #:
Pub Dt:
10/18/2012
Title:
Method And Structure For Compound Semiconductor Contact
15
Patent #:
Issue Dt:
08/27/2013
Application #:
13085717
Filing Dt:
04/13/2011
Publication #:
Pub Dt:
08/04/2011
Title:
OPTICAL COUPLING METHOD
16
Patent #:
Issue Dt:
04/08/2014
Application #:
13086459
Filing Dt:
04/14/2011
Publication #:
Pub Dt:
10/18/2012
Title:
MOSFET with Recessed channel FILM and Abrupt Junctions
17
Patent #:
Issue Dt:
09/24/2013
Application #:
13087464
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
BONDING CONTROLLER GUIDED ASSESSMENT AND OPTIMIZATIONFOR CHIP-TO-CHIP STACKING
18
Patent #:
Issue Dt:
06/09/2015
Application #:
13088054
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL
19
Patent #:
Issue Dt:
12/02/2014
Application #:
13088083
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
METHOD FOR FORMING SELF-ALIGNED AIRGAP INTERCONNECT STRUCTURES
20
Patent #:
Issue Dt:
03/06/2012
Application #:
13088339
Filing Dt:
04/16/2011
Publication #:
Pub Dt:
08/11/2011
Title:
TECHNIQUES FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION
21
Patent #:
Issue Dt:
09/03/2013
Application #:
13088376
Filing Dt:
04/17/2011
Publication #:
Pub Dt:
10/18/2012
Title:
SOI DEVICE WITH DTI AND STI
22
Patent #:
Issue Dt:
02/04/2014
Application #:
13088766
Filing Dt:
04/18/2011
Publication #:
Pub Dt:
10/18/2012
Title:
GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SIC FINS OR NANOWIRE TEMPLATES
23
Patent #:
Issue Dt:
09/03/2013
Application #:
13091292
Filing Dt:
04/21/2011
Publication #:
Pub Dt:
10/25/2012
Title:
EDRAM HAVING DYNAMIC RETENTION AND PERFORMANCE TRADEOFF
24
Patent #:
Issue Dt:
12/10/2013
Application #:
13092247
Filing Dt:
04/22/2011
Publication #:
Pub Dt:
10/25/2012
Title:
RESONANCE NANOELECTROMECHANICAL SYSTEMS
25
Patent #:
Issue Dt:
08/27/2013
Application #:
13092424
Filing Dt:
04/22/2011
Publication #:
Pub Dt:
10/25/2012
Title:
SELF-SEALED FLUIDIC CHANNELS FOR NANOPORE ARRAY
26
Patent #:
Issue Dt:
06/10/2014
Application #:
13092815
Filing Dt:
04/22/2011
Publication #:
Pub Dt:
10/25/2012
Title:
IN-SITU MEASUREMENT OF FEATURE DIMENSIONS
27
Patent #:
Issue Dt:
12/11/2012
Application #:
13096511
Filing Dt:
04/28/2011
Publication #:
Pub Dt:
08/18/2011
Title:
METHOD TO REDUCE MOL DAMAGE ON NISI
28
Patent #:
Issue Dt:
02/11/2014
Application #:
13096850
Filing Dt:
04/28/2011
Publication #:
Pub Dt:
11/01/2012
Title:
TAPERED VIA AND MIM CAPACITOR
29
Patent #:
Issue Dt:
11/05/2013
Application #:
13097402
Filing Dt:
04/29/2011
Publication #:
Pub Dt:
12/01/2011
Title:
DATA ENCODING IN SOLID-STATE STORAGE DEVICES
30
Patent #:
Issue Dt:
04/09/2013
Application #:
13097459
Filing Dt:
04/29/2011
Publication #:
Pub Dt:
11/01/2012
Title:
METHOD OF FORMING SILICIDE CONTACTS OF DIFFERENT SHAPES SELECTIVELY ON REGIONS OF A SEMICONDUCTOR DEVICE
31
Patent #:
Issue Dt:
06/24/2014
Application #:
13097490
Filing Dt:
04/29/2011
Publication #:
Pub Dt:
12/01/2011
Title:
SEMICONDUCTOR DEVICE COMPRISING A STACKED DIE CONFIGURATION INCLUDING AN INTEGRATED PELTIER ELEMENT
32
Patent #:
Issue Dt:
10/15/2013
Application #:
13097712
Filing Dt:
04/29/2011
Publication #:
Pub Dt:
11/01/2012
Title:
Nanostructured Organosilicates from Thermally Curable Block Copolymers
33
Patent #:
Issue Dt:
08/20/2013
Application #:
13098816
Filing Dt:
05/02/2011
Publication #:
Pub Dt:
11/08/2012
Title:
BUFFER PAD IN SOLDER BUMP CONNECTIONS AND METHODS OF MANUFACTURE
34
Patent #:
Issue Dt:
12/17/2013
Application #:
13099692
Filing Dt:
05/03/2011
Publication #:
Pub Dt:
11/08/2012
Title:
SEMICONDUCTOR DEVICE WITH DRAM BIT LINES MADE FROM SAME MATERIAL AS GATE ELECTRODES IN NON-MEMORY REGIONS OF THE DEVICE, AND METHODS OF MAKING SAME
35
Patent #:
Issue Dt:
07/02/2013
Application #:
13099767
Filing Dt:
05/03/2011
Publication #:
Pub Dt:
11/08/2012
Title:
DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS
36
Patent #:
Issue Dt:
02/05/2013
Application #:
13099790
Filing Dt:
05/03/2011
Publication #:
Pub Dt:
08/25/2011
Title:
SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC
37
Patent #:
Issue Dt:
12/10/2013
Application #:
13099827
Filing Dt:
05/03/2011
Publication #:
Pub Dt:
11/08/2012
Title:
TRANSPARENT PHOTODETECTOR
38
Patent #:
Issue Dt:
10/02/2012
Application #:
13100456
Filing Dt:
05/04/2011
Publication #:
Pub Dt:
08/25/2011
Title:
REPROGRAMMABLE FUSE STRUCTURE AND METHOD
39
Patent #:
Issue Dt:
04/01/2014
Application #:
13100798
Filing Dt:
05/04/2011
Publication #:
Pub Dt:
11/08/2012
Title:
METHOD OF FORMING METAL GATES AND METAL CONTACTS IN A COMMON FILL PROCESS
40
Patent #:
Issue Dt:
03/12/2013
Application #:
13101260
Filing Dt:
05/05/2011
Publication #:
Pub Dt:
11/08/2012
Title:
CAVITY-FREE INTERFACE BETWEEN EXTENSION REGIONS AND EMBEDDED SILICON-CARBON ALLOY SOURCE/DRAIN REGIONS
41
Patent #:
Issue Dt:
09/03/2013
Application #:
13101267
Filing Dt:
05/05/2011
Publication #:
Pub Dt:
08/25/2011
Title:
METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR
42
Patent #:
Issue Dt:
10/07/2014
Application #:
13101268
Filing Dt:
05/05/2011
Publication #:
Pub Dt:
11/08/2012
Title:
3-D Integration using Multi Stage Vias
43
Patent #:
Issue Dt:
11/05/2013
Application #:
13101659
Filing Dt:
05/05/2011
Publication #:
Pub Dt:
11/08/2012
Title:
METHOD OF INCREASING THE GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND SEMICONDUCTOR DEVICE COMPRISING SAME
44
Patent #:
Issue Dt:
08/20/2013
Application #:
13101764
Filing Dt:
05/05/2011
Publication #:
Pub Dt:
11/08/2012
Title:
REDUCED THRESHOLD VOLTAGE-WIDTH DEPENDENCY AND REDUCED SURFACE TOPOGRAPHY IN TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES BY A LATE CARBON INCORPORATION
45
Patent #:
Issue Dt:
09/17/2013
Application #:
13102411
Filing Dt:
05/06/2011
Publication #:
Pub Dt:
12/01/2011
Title:
SELECTIVE SHRINKAGE OF CONTACT ELEMENTS IN A SEMICONDUCTOR DEVICE
46
Patent #:
Issue Dt:
07/23/2013
Application #:
13102550
Filing Dt:
05/06/2011
Publication #:
Pub Dt:
09/01/2011
Title:
CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL
47
Patent #:
Issue Dt:
04/22/2014
Application #:
13102680
Filing Dt:
05/06/2011
Publication #:
Pub Dt:
11/08/2012
Title:
Process Flow to Reduce Hole Defects in P-Active Regions and to Reduce Across-Wafer Threshold Voltage Scatter
48
Patent #:
Issue Dt:
02/26/2013
Application #:
13102776
Filing Dt:
05/06/2011
Publication #:
Pub Dt:
11/08/2012
Title:
TIMING DRIVEN ROUTING IN INTEGRATED CIRCUIT DESIGN
49
Patent #:
Issue Dt:
04/16/2013
Application #:
13103569
Filing Dt:
05/09/2011
Publication #:
Pub Dt:
08/25/2011
Title:
DENSE PITCH BULK FINFET PROCESS BY SELECTIVE EPI AND ETCH
50
Patent #:
Issue Dt:
07/09/2013
Application #:
13104542
Filing Dt:
05/10/2011
Publication #:
Pub Dt:
11/15/2012
Title:
INTEGRATED CIRCUIT DIODE
51
Patent #:
Issue Dt:
06/25/2013
Application #:
13104591
Filing Dt:
05/10/2011
Publication #:
Pub Dt:
11/15/2012
Title:
CARBON FIELD EFFECT TRANSISTORS HAVING CHARGED MONOLAYERS TO REDUCE PARASITIC RESISTANCE
52
Patent #:
Issue Dt:
08/14/2012
Application #:
13107087
Filing Dt:
05/13/2011
Publication #:
Pub Dt:
09/08/2011
Title:
PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL
53
Patent #:
Issue Dt:
08/13/2013
Application #:
13108282
Filing Dt:
05/16/2011
Publication #:
Pub Dt:
11/22/2012
Title:
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) FET WITH A BACK GATE AND REDUCED PARASITIC CAPACITANCE
54
Patent #:
Issue Dt:
12/31/2013
Application #:
13108305
Filing Dt:
05/16/2011
Publication #:
Pub Dt:
11/22/2012
Title:
JUNCTION GATE FIELD EFFECT TRANSISTOR STRUCRURE HAVING N-CHANNEL
55
Patent #:
Issue Dt:
03/24/2015
Application #:
13108363
Filing Dt:
05/16/2011
Publication #:
Pub Dt:
11/22/2012
Title:
METHOD OF FORMING SPACERS THAT PROVIDE ENHANCED PROTECTION FOR GATE ELECTRODE STRUCTURES
56
Patent #:
Issue Dt:
01/28/2014
Application #:
13108721
Filing Dt:
05/16/2011
Publication #:
Pub Dt:
11/22/2012
Title:
SOFT ERROR RATE DETECTOR
57
Patent #:
Issue Dt:
09/17/2013
Application #:
13109869
Filing Dt:
05/17/2011
Publication #:
Pub Dt:
11/22/2012
Title:
SEMICONDUCTOR DEVICES HAVING ENCAPSULATED ISOLATION REGIONS AND RELATED FABRICATION METHODS
58
Patent #:
Issue Dt:
06/04/2013
Application #:
13111741
Filing Dt:
05/19/2011
Publication #:
Pub Dt:
11/22/2012
Title:
FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
59
Patent #:
Issue Dt:
08/12/2014
Application #:
13112356
Filing Dt:
05/20/2011
Publication #:
Pub Dt:
10/06/2011
Title:
HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS
60
Patent #:
Issue Dt:
03/04/2014
Application #:
13113698
Filing Dt:
05/23/2011
Publication #:
Pub Dt:
12/01/2011
Title:
TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN DIAMOND-SHAPED CAVITIES BASED ON A PRE-AMORPHIZATION
61
Patent #:
Issue Dt:
12/03/2013
Application #:
13113901
Filing Dt:
05/23/2011
Publication #:
Pub Dt:
11/29/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
62
Patent #:
Issue Dt:
07/16/2013
Application #:
13114116
Filing Dt:
05/24/2011
Publication #:
Pub Dt:
01/05/2012
Title:
SEMICONDUCTOR DEVICE COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND PRECISION EFUSES FORMED IN THE ACTIVE SEMICONDUCTOR MATERIAL
63
Patent #:
Issue Dt:
10/08/2013
Application #:
13114283
Filing Dt:
05/24/2011
Publication #:
Pub Dt:
11/29/2012
Title:
STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY
64
Patent #:
Issue Dt:
10/01/2013
Application #:
13114543
Filing Dt:
05/24/2011
Publication #:
Pub Dt:
11/29/2012
Title:
DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE
65
Patent #:
Issue Dt:
12/17/2013
Application #:
13115192
Filing Dt:
05/25/2011
Publication #:
Pub Dt:
02/02/2012
Title:
INCREASED STABILITY OF A COMPLEX MATERIAL STACK IN A SEMICONDUCTOR DEVICE BY PROVIDING FLUORINE ENRICHED INTERFACES
66
Patent #:
Issue Dt:
05/13/2014
Application #:
13115270
Filing Dt:
05/25/2011
Publication #:
Pub Dt:
11/29/2012
Title:
METHOD OF PROTECTING STI STRUCTURES FROM EROSION DURING PROCESSING OPERATIONS
67
Patent #:
Issue Dt:
09/09/2014
Application #:
13115428
Filing Dt:
05/25/2011
Publication #:
Pub Dt:
11/29/2012
Title:
PMOS THRESHOLD VOLTAGE CONTROL BY GERMANIUM IMPLANTATION
68
Patent #:
Issue Dt:
08/20/2013
Application #:
13115823
Filing Dt:
05/25/2011
Publication #:
Pub Dt:
11/29/2012
Title:
TECHNIQUE FOR VERIFYING THE MICROSTRUCTURE OF LEAD-FREE INTERCONNECTS IN SEMICONDUCTOR ASSEMBLIES
69
Patent #:
Issue Dt:
05/05/2015
Application #:
13116672
Filing Dt:
05/26/2011
Publication #:
Pub Dt:
11/29/2012
Title:
METHOD OF FORMING CONTACTS FOR DEVICES WITH MULTIPLE STRESS LINERS
70
Patent #:
Issue Dt:
10/01/2013
Application #:
13116961
Filing Dt:
05/26/2011
Publication #:
Pub Dt:
11/29/2012
Title:
SEMICONDUCTOR-BASED TEST DEVICE THAT IMPLEMENTS RANDOM LOGIC FUNCTIONS
71
Patent #:
Issue Dt:
06/04/2013
Application #:
13117249
Filing Dt:
05/27/2011
Publication #:
Pub Dt:
02/02/2012
Title:
TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS FORMED IN A LATE STAGE
72
Patent #:
Issue Dt:
09/09/2014
Application #:
13118881
Filing Dt:
05/31/2011
Publication #:
Pub Dt:
12/06/2012
Title:
HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY
73
Patent #:
Issue Dt:
06/17/2014
Application #:
13126546
Filing Dt:
06/06/2011
Publication #:
Pub Dt:
11/10/2011
Title:
METHOD, DEVICE, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A REPRESENTATION OF A SIGNAL
74
Patent #:
Issue Dt:
04/16/2013
Application #:
13149108
Filing Dt:
05/31/2011
Publication #:
Pub Dt:
12/06/2012
Title:
ELECTRICALLY PROGRAMMABLE METAL FUSE
75
Patent #:
Issue Dt:
01/07/2014
Application #:
13149797
Filing Dt:
05/31/2011
Publication #:
Pub Dt:
12/06/2012
Title:
BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH
76
Patent #:
Issue Dt:
12/03/2013
Application #:
13150612
Filing Dt:
06/01/2011
Publication #:
Pub Dt:
12/06/2012
Title:
STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE
77
Patent #:
Issue Dt:
01/15/2013
Application #:
13150705
Filing Dt:
06/01/2011
Publication #:
Pub Dt:
09/22/2011
Title:
POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL
78
Patent #:
Issue Dt:
02/19/2013
Application #:
13151295
Filing Dt:
06/02/2011
Publication #:
Pub Dt:
12/06/2012
Title:
METHOD FOR PERFORMING A PARALLEL STATIC TIMING ANALYSIS USING THREAD-SPECIFIC SUB-GRAPHS
79
Patent #:
Issue Dt:
02/19/2013
Application #:
13151313
Filing Dt:
06/02/2011
Publication #:
Pub Dt:
12/06/2012
Title:
METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION
80
Patent #:
Issue Dt:
12/02/2014
Application #:
13151525
Filing Dt:
06/02/2011
Publication #:
Pub Dt:
09/22/2011
Title:
HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
81
Patent #:
Issue Dt:
10/22/2013
Application #:
13151898
Filing Dt:
06/02/2011
Publication #:
Pub Dt:
12/06/2012
Title:
INTEGRATED CIRCUIT HAVING ELECTROSTATIC DISCHARGE PROTECTION
82
Patent #:
Issue Dt:
08/13/2013
Application #:
13152350
Filing Dt:
06/03/2011
Publication #:
Pub Dt:
09/22/2011
Title:
DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
83
Patent #:
Issue Dt:
02/21/2012
Application #:
13153051
Filing Dt:
06/03/2011
Publication #:
Pub Dt:
10/20/2011
Title:
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
84
Patent #:
Issue Dt:
12/31/2013
Application #:
13153381
Filing Dt:
06/03/2011
Publication #:
Pub Dt:
03/22/2012
Title:
ANNEALING THIN FILMS
85
Patent #:
Issue Dt:
07/01/2014
Application #:
13153806
Filing Dt:
06/06/2011
Publication #:
Pub Dt:
09/29/2011
Title:
EMBEDDED DRAM INTEGRATED CIRCUITS WITH EXTREMELY THIN SILICON-ON-INSULATOR PASS TRANSISTORS
86
Patent #:
Issue Dt:
04/15/2014
Application #:
13154521
Filing Dt:
06/07/2011
Publication #:
Pub Dt:
12/13/2012
Title:
Method of Removing Gate Cap Materials While Protecting Active Area
87
Patent #:
Issue Dt:
01/27/2015
Application #:
13154548
Filing Dt:
06/07/2011
Publication #:
Pub Dt:
12/13/2012
Title:
BURIED SUBLEVEL METALLIZATIONS FOR IMPROVED TRANSISTOR DENSITY
88
Patent #:
Issue Dt:
03/04/2014
Application #:
13154578
Filing Dt:
06/07/2011
Publication #:
Pub Dt:
12/13/2012
Title:
Metal Gate Stack Formation for Replacement Gate Technology
89
Patent #:
Issue Dt:
05/13/2014
Application #:
13154754
Filing Dt:
06/07/2011
Publication #:
Pub Dt:
02/02/2012
Title:
REDUCED TOPOGRAPHY IN ISOLATION REGIONS OF A SEMICONDUCTOR DEVICE BY APPLYING A DEPOSITION/ETCH SEQUENCE PRIOR TO FORMING THE INTERLAYER DIELECTRIC
90
Patent #:
Issue Dt:
07/29/2014
Application #:
13154905
Filing Dt:
06/07/2011
Publication #:
Pub Dt:
12/13/2012
Title:
METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
91
Patent #:
Issue Dt:
09/17/2013
Application #:
13155878
Filing Dt:
06/08/2011
Publication #:
Pub Dt:
12/13/2012
Title:
FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION
92
Patent #:
Issue Dt:
02/24/2015
Application #:
13156935
Filing Dt:
06/09/2011
Publication #:
Pub Dt:
12/13/2012
Title:
ON-CHIP SLOW-WAVE THROUGH-SILICON VIA COPLANAR WAVEGUIDE STRUCTURES, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
93
Patent #:
Issue Dt:
07/08/2014
Application #:
13157968
Filing Dt:
06/10/2011
Publication #:
Pub Dt:
12/13/2012
Title:
TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY
94
Patent #:
Issue Dt:
01/28/2014
Application #:
13157980
Filing Dt:
06/10/2011
Publication #:
Pub Dt:
12/13/2012
Title:
Rapid Estimation of Temperature Rise in Wires Due to Joule Heating
95
Patent #:
Issue Dt:
03/26/2013
Application #:
13158048
Filing Dt:
06/10/2011
Publication #:
Pub Dt:
10/06/2011
Title:
CHIP PACKAGE WITH CHANNEL STIFFENER FRAME
96
Patent #:
Issue Dt:
10/08/2013
Application #:
13158079
Filing Dt:
06/10/2011
Publication #:
Pub Dt:
12/13/2012
Title:
PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR
97
Patent #:
Issue Dt:
03/04/2014
Application #:
13158114
Filing Dt:
06/10/2011
Publication #:
Pub Dt:
12/13/2012
Title:
COPPER INTERCONNECT WITH METAL HARDMASK REMOVAL
98
Patent #:
Issue Dt:
09/10/2013
Application #:
13158419
Filing Dt:
06/12/2011
Publication #:
Pub Dt:
12/13/2012
Title:
COMPLEMENTARY BIPOLAR INVERTER
99
Patent #:
Issue Dt:
09/03/2013
Application #:
13158420
Filing Dt:
06/12/2011
Publication #:
Pub Dt:
12/13/2012
Title:
COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A LOW-VOLTAGE CMOS PLATFORM
100
Patent #:
Issue Dt:
01/29/2013
Application #:
13158562
Filing Dt:
06/13/2011
Publication #:
Pub Dt:
12/13/2012
Title:
SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE
Assignor
1
Exec Dt:
10/22/2020
Assignee
1
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
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