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09/23/2014
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12/20/2012
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04/29/2014
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06/14/2011
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12/20/2012
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02/25/2014
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12/20/2012
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10/08/2013
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12/20/2012
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01/14/2014
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12/20/2012
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12/20/2012
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11/26/2013
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12/20/2012
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06/25/2013
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12/20/2012
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05/19/2015
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12/20/2012
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07/23/2013
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12/27/2012
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03/04/2014
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12/23/2014
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12/27/2012
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07/16/2013
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06/23/2011
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12/27/2012
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05/27/2014
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12/27/2012
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10/29/2013
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12/27/2012
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03/26/2013
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12/27/2012
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11/19/2013
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12/27/2012
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04/30/2013
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06/28/2011
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01/03/2013
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10/29/2013
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01/03/2013
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11/19/2013
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01/03/2013
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06/29/2011
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01/03/2013
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06/10/2014
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11/25/2014
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01/03/2013
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01/10/2013
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07/11/2011
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09/26/2017
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07/23/2013
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12/30/2014
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07/23/2013
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01/31/2013
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04/22/2014
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13190566
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07/26/2011
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01/31/2013
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07/30/2013
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13191090
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07/26/2011
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11/24/2011
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NOBLE METAL CAP FOR INTERCONNECT STRUCTURES
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02/26/2013
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13191540
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07/27/2011
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01/31/2013
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BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES
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12/04/2012
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07/27/2011
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02/02/2012
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ASSESSING PRINTABILITY OF A VERY-LARGE-SCALE INTEGRATION DESIGN
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08/26/2014
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13191917
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07/27/2011
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01/31/2013
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02/25/2014
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13191985
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07/27/2011
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01/31/2013
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Method to Transfer Lithographic Patterns Into Inorganic Substrates
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06/10/2014
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13191993
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07/27/2011
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06/21/2012
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Semiconductor Devices Comprising a Channel Semiconductor Alloy Formed with Reduced STI Topography
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09/03/2013
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13191999
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07/27/2011
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01/31/2013
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HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME
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07/15/2014
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13192164
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07/27/2011
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06/21/2012
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METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES COMPRISING A COPPER/SILICON COMPOUND AS A BARRIER MATERIAL
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05/27/2014
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07/27/2011
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01/31/2013
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11/19/2013
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07/27/2011
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01/31/2013
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04/29/2014
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07/28/2011
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06/21/2012
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SACRIFICIAL SPACER APPROACH FOR DIFFERENTIAL SOURCE/DRAIN IMPLANTATION SPACERS IN TRANSISTORS COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE
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03/04/2014
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07/28/2011
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06/21/2012
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LOW-DIFFUSION DRAIN AND SOURCE REGIONS IN CMOS TRANSISTORS FOR LOW POWER/HIGH PERFORMANCE APPLICATIONS
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04/08/2014
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13194214
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07/29/2011
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01/31/2013
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TSV PILLAR AS AN INTERCONNECTING STRUCTURE
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02/03/2015
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07/29/2011
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01/31/2013
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MODELING GATE TRANSCONDUCTANCE IN A SUB-CIRCUIT TRANSISTOR MODEL
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06/26/2012
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08/01/2011
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11/24/2011
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OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME
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09/17/2013
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13197239
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08/03/2011
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06/21/2012
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DIFFERENTIAL THRESHOLD VOLTAGE ADJUSTMENT IN PMOS TRANSISTORS BY DIFFERENTIAL FORMATION OF A CHANNEL SEMICONDUCTOR MATERIAL
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03/18/2014
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13197387
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08/03/2011
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06/21/2012
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FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY A NITRIDE HARD MASK LAYER AND AN OXIDE MASK
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10/30/2012
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13197414
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08/03/2011
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11/24/2011
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SELF-ALIGNED SCHOTTKY DIODE
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09/23/2014
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13197631
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08/03/2011
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02/07/2013
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SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES
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07/07/2015
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13198152
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08/04/2011
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02/07/2013
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EPITAXIAL EXTENSION CMOS TRANSISTOR
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01/01/2013
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13198209
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08/04/2011
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06/28/2012
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METHOD FOR FORMING A TRANSISTOR COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES INCLUDING A POLYCRYSTALLINE SEMICONDUCTOR MATERIAL AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS
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07/30/2013
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13204271
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08/05/2011
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02/07/2013
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TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS
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09/03/2013
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13204283
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08/05/2011
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02/07/2013
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FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH
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09/03/2013
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13206586
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08/10/2011
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02/14/2013
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SEMICONDUCTOR STRUCTURE HAVING A WETTING LAYER
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07/03/2012
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13207480
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08/11/2011
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12/01/2011
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BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES
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10/22/2013
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13208697
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08/12/2011
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06/28/2012
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SHRINKAGE OF CONTACT ELEMENTS AND VIAS IN A SEMICONDUCTOR DEVICE BY INCORPORATING ADDITIONAL TAPERING MATERIAL
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09/17/2013
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13208835
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08/12/2011
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06/28/2012
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Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions
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11/04/2014
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13208972
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08/12/2011
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06/28/2012
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Embedding Metal Silicide Contact Regions Reliably Into Highly Doped Drain and Source Regions by a Stop Implantation
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05/13/2014
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13209057
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08/12/2011
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06/28/2012
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SELF-ALIGNED FIN TRANSISTOR FORMED ON A BULK SUBSTRATE BY LATE FIN ETCH
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10/28/2014
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13209405
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08/14/2011
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02/14/2013
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3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE
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09/09/2014
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13209569
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08/15/2011
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02/21/2013
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LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS
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09/23/2014
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13212489
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08/18/2011
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02/21/2013
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METHOD FOR FORMING CORELESS FLIP CHIP BALL GRID ARRAY (FCBGA) SUBSTRATES AND SUCH SUBSTRATES FORMED BY THE METHOD
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09/09/2014
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13213740
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08/19/2011
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02/21/2013
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HOMOGENEOUS MODIFICATION OF POROUS FILMS
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01/28/2014
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13214157
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08/19/2011
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02/21/2013
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PROCESS TO FORM AN ADHESION LAYER AND MULTIPHASE ULTRA-LOW K DIELECTRIC MATERIAL USING PECVD
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03/18/2014
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13214818
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08/22/2011
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02/28/2013
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TECHNIQUES FOR RECOVERY OF WIRELESS SERVICES FOLLOWING POWER FAILURES
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13215568
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08/23/2011
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02/28/2013
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Semiconductor Device with DRAM Word Lines and Gate Electrodes in Non-Memory Regions of the Device Comprised of a Metal, and Methods of Making Same
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05/06/2014
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13215635
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08/23/2011
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02/28/2013
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REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL
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03/25/2014
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08/23/2011
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02/28/2013
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FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS
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06/25/2013
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13216708
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08/24/2011
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02/28/2013
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PARASITIC CAPACITANCE REDUCTION IN MOSFET BY AIRGAP ILD
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07/02/2013
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13216791
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08/24/2011
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02/28/2013
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METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN REGIONS, AND A SEMICONDUCTOR DEVICE COMPRISING SAME
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02/11/2014
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13216862
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08/24/2011
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02/28/2013
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IMPLANTATION OF HYDROGEN TO IMPROVE GATE INSULATION LAYER-SUBSTRATE INTERFACE
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09/17/2013
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13216921
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08/24/2011
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02/28/2013
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METHODS OF FORMING STRESSED SILICON-CARBON AREAS IN AN NMOS TRANSISTOR
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11/12/2013
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13217009
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08/24/2011
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02/28/2013
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THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION
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06/24/2014
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13217061
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08/24/2011
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02/28/2013
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ELECTRONIC DEVICE HAVING PLURAL FIN-FETS WITH DIFFERENT FIN HEIGHTS AND PLANAR FETS ON THE SAME SUBSTRATE
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09/03/2013
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13217335
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08/25/2011
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02/28/2013
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SYNCHRONIZING GLOBAL CLOCKS IN 3D STACKS OF INTEGRATED CIRCUITS BY SHORTING THE CLOCK NETWORK
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11/05/2013
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13217349
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08/25/2011
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02/28/2013
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3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING
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