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Patent #:
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Issue Dt:
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04/24/2018
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Application #:
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14162948
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Filing Dt:
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01/24/2014
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Publication #:
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Pub Dt:
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07/30/2015
| | | | |
Title:
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MULTIWIDTH FINFET WITH CHANNEL CLADDING
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Patent #:
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Issue Dt:
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03/22/2016
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Application #:
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14163511
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Filing Dt:
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01/24/2014
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Publication #:
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Pub Dt:
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07/30/2015
| | | | |
Title:
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METHOD AND APPARATUS FOR MODIFIED CELL ARCHITECTURE AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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07/19/2016
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Application #:
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14164582
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Filing Dt:
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01/27/2014
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Publication #:
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Pub Dt:
|
07/30/2015
| | | | |
Title:
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METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS
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Patent #:
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Issue Dt:
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12/01/2015
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Application #:
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14164687
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Filing Dt:
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01/27/2014
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Publication #:
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Pub Dt:
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07/31/2014
| | | | |
Title:
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LEVEL-ESTIMATION IN MULTI-LEVEL CELL MEMORY
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Patent #:
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NONE
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Application #:
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14165107
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Filing Dt:
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01/27/2014
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Publication #:
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Pub Dt:
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07/30/2015
| | | | |
Title:
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LOW LEAKAGE PMOS TRANSISTOR
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Patent #:
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Issue Dt:
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02/23/2016
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Application #:
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14165209
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Filing Dt:
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01/27/2014
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Publication #:
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Pub Dt:
|
07/30/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH FEROOELECTRIC HAFNIUM OXIDE AND METHOD FOR FORMING SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/22/2015
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Application #:
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14165621
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Filing Dt:
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01/28/2014
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Publication #:
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Pub Dt:
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01/08/2015
| | | | |
Title:
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BALL GRID ARRAY CONFIGURATION FOR RELIABLE TESTING
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Patent #:
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Issue Dt:
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03/07/2017
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14166078
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Filing Dt:
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01/28/2014
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Publication #:
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Pub Dt:
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04/23/2015
| | | | |
Title:
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PROXIMITY BASED DUAL AUTHENTICATION FOR A WIRELESS NETWORK
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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14166219
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Filing Dt:
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01/28/2014
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
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LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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14166274
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Filing Dt:
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01/28/2014
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
Title:
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DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
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Patent #:
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Issue Dt:
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11/03/2015
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Application #:
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14166660
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Filing Dt:
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01/28/2014
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Publication #:
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Pub Dt:
|
07/30/2015
| | | | |
Title:
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INTEGRATED CIRCUITS WITH METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACT STRUCTURES AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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01/19/2016
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Application #:
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14167499
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Filing Dt:
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01/29/2014
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
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JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE
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Patent #:
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Issue Dt:
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03/22/2016
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Application #:
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14167778
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Filing Dt:
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01/29/2014
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Publication #:
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Pub Dt:
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07/30/2015
| | | | |
Title:
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IINTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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06/30/2015
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Application #:
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14168208
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Filing Dt:
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01/30/2014
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
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INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR
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Patent #:
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Issue Dt:
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11/24/2015
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Application #:
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14168396
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Filing Dt:
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01/30/2014
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Publication #:
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Pub Dt:
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07/30/2015
| | | | |
Title:
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MASK STRUCTURES AND METHODS OF MANUFACTURING
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Patent #:
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Issue Dt:
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03/03/2015
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Application #:
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14168471
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Filing Dt:
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01/30/2014
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
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FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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14169318
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Filing Dt:
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01/31/2014
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Publication #:
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Pub Dt:
|
08/06/2015
| | | | |
Title:
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SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14172362
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Filing Dt:
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02/04/2014
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Publication #:
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Pub Dt:
|
08/06/2015
| | | | |
Title:
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FINFET WITH ISOLATED SOURCE AND DRAIN
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Patent #:
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Issue Dt:
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06/21/2016
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Application #:
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14175113
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Filing Dt:
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02/07/2014
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Publication #:
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Pub Dt:
|
08/13/2015
| | | | |
Title:
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METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
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12/11/2018
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Application #:
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14175215
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Filing Dt:
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02/07/2014
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Publication #:
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Pub Dt:
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08/13/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH FINS INCLUDING SIDEWALL RECESSES
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Patent #:
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Issue Dt:
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06/07/2016
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Application #:
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14175827
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Filing Dt:
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02/07/2014
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Publication #:
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Pub Dt:
|
08/13/2015
| | | | |
Title:
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FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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04/19/2016
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Application #:
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14176208
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Filing Dt:
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02/10/2014
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Publication #:
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Pub Dt:
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01/15/2015
| | | | |
Title:
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COMPLEX CIRCUIT ELEMENT AND CAPACITOR UTILIZING CMOS COMPATIBLE ANTIFERROELECTRIC HIGH-K MATERIALS
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Patent #:
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Issue Dt:
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09/23/2014
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Application #:
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14176460
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Filing Dt:
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02/10/2014
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
Title:
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TAPERED VIA AND MIM CAPACITOR
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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14176526
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Filing Dt:
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02/10/2014
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Title:
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TOUGHNESS, ADHESION AND SMOOTH METAL LINES OF POROUS LOW K DIELECTRIC INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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14176552
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Filing Dt:
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02/10/2014
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Title:
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SILICON WAVEGUIDE ON BULK SILICON SUBSTRATE AND METHODS OF FORMING
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Patent #:
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Issue Dt:
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09/22/2015
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Application #:
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14176767
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Filing Dt:
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02/10/2014
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
Title:
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FINFET DEVICES HAVING A BODY CONTACT AND METHODS OF FORMING THE SAME
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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14177481
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Filing Dt:
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02/11/2014
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Publication #:
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Pub Dt:
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08/13/2015
| | | | |
Title:
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SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS
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Patent #:
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Issue Dt:
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01/05/2016
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Application #:
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14179121
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Filing Dt:
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02/12/2014
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Publication #:
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Pub Dt:
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08/13/2015
| | | | |
Title:
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MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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08/19/2014
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14179707
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02/13/2014
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Publication #:
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Pub Dt:
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06/19/2014
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Title:
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SMALL FOOTPRINT PHASE CHANGE MEMORY CELL
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Patent #:
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Issue Dt:
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05/17/2016
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Application #:
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14181616
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Filing Dt:
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02/14/2014
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Publication #:
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Pub Dt:
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08/20/2015
| | | | |
Title:
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UNIVERSAL SOLDER JOINTS FOR 3D PACKAGING
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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14181832
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02/17/2014
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Publication #:
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Pub Dt:
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08/20/2015
| | | | |
Title:
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GRAPHENE TRANSISTOR WITH A SUBLITHOGRAPHIC CHANNEL WIDTH
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Patent #:
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Issue Dt:
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02/23/2016
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Application #:
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14184826
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Filing Dt:
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02/20/2014
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Publication #:
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Pub Dt:
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09/18/2014
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Title:
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METHODS FOR FORMING PROTECTION LAYERS ON SIDEWALLS OF CONTACT ETCH STOP LAYERS
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Patent #:
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Issue Dt:
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01/12/2016
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14184830
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Filing Dt:
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02/20/2014
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Publication #:
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Pub Dt:
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08/20/2015
| | | | |
Title:
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METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS
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Patent #:
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Issue Dt:
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02/09/2016
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14185398
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Filing Dt:
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02/20/2014
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Publication #:
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Pub Dt:
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08/20/2015
| | | | |
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING DENSIFYING INTERLEVEL DIELECTRIC LAYERS
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Patent #:
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Issue Dt:
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04/12/2016
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14185440
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Filing Dt:
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02/20/2014
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Publication #:
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Pub Dt:
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08/20/2015
| | | | |
Title:
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MASK THAT PROVIDES IMPROVED FOCUS CONTROL USING ORTHOGONAL EDGES
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Patent #:
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Issue Dt:
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05/23/2017
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Application #:
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14186360
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Filing Dt:
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02/21/2014
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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NEW PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION
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Patent #:
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Issue Dt:
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03/15/2016
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14186396
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Filing Dt:
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02/21/2014
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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METHODS OF PATTERNING LINE-TYPE FEATURES USING A MULTIPLE PATTERNING PROCESS THAT ENABLES THE USE OF TIGHTER CONTACT ENCLOSURE SPACING RULES
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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14186512
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Filing Dt:
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02/21/2014
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Publication #:
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Pub Dt:
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06/19/2014
| | | | |
Title:
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LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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14187392
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Filing Dt:
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02/24/2014
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Publication #:
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Pub Dt:
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06/19/2014
| | | | |
Title:
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LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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14188778
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Filing Dt:
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02/25/2014
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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INTEGRATED CIRCUITS WITH VARYING GATE STRUCTURES AND FABRICATION METHODS
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Patent #:
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Issue Dt:
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06/07/2016
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Application #:
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14189085
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Filing Dt:
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02/25/2014
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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14189108
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Filing Dt:
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02/25/2014
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Publication #:
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Pub Dt:
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06/19/2014
| | | | |
Title:
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Thick On-Chip High-Performance Wiring Structures
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Patent #:
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Issue Dt:
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12/08/2015
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Application #:
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14189465
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Filing Dt:
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02/25/2014
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING GENERATING PHOTOMASKS FOR DIRECTED SELF-ASSEMBLY
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