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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 56 of 85
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Patent #:	10546856	Issue Dt:	01/28/2020	Application #:	14189509	Filing Dt:	02/25/2014
Publication #:	US20150243660	Pub Dt:	08/27/2015
Title:	CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD

Patent #:	8809967	Issue Dt:	08/19/2014	Application #:	14191626	Filing Dt:	02/27/2014
Publication #:	US20140175550	Pub Dt:	06/26/2014
Title:	DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES

Patent #:	9230989	Issue Dt:	01/05/2016	Application #:	14194762	Filing Dt:	03/02/2014
Publication #:	US20140175374	Pub Dt:	06/26/2014
Title:	HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE

Patent #:	9053981	Issue Dt:	06/09/2015	Application #:	14194766	Filing Dt:	03/02/2014
Publication #:	US20140175375	Pub Dt:	06/26/2014
Title:	HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE

Patent #:	9147730	Issue Dt:	09/29/2015	Application #:	14195344	Filing Dt:	03/03/2014
Publication #:	US20150249127	Pub Dt:	09/03/2015
Title:	METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND SELECTIVELY REMOVING SOME OF THE FINS BY PERFORMING A CYCLICAL FIN CUTTING PROCESS

Patent #:	9536877	Issue Dt:	01/03/2017	Application #:	14195484	Filing Dt:	03/03/2014
Publication #:	US20150249036	Pub Dt:	09/03/2015
Title:	METHODS OF FORMING DIFFERENT SPACER STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS HAVING DIFFERING GATE PITCH DIMENSIONS AND THE RESULTING PRODUCTS

Patent #:	9171800	Issue Dt:	10/27/2015	Application #:	14195952	Filing Dt:	03/04/2014
Publication #:	US20150255393	Pub Dt:	09/10/2015
Title:	ELECTRICAL FUSE WITH BOTTOM CONTACTS

Patent #:	9478509	Issue Dt:	10/25/2016	Application #:	14198711	Filing Dt:	03/06/2014
Publication #:	US20150255410	Pub Dt:	09/10/2015
Title:	MECHANICALLY ANCHORED BACKSIDE C4 PAD

Patent #:	9171935	Issue Dt:	10/27/2015	Application #:	14200104	Filing Dt:	03/07/2014
Publication #:	US20150255569	Pub Dt:	09/10/2015
Title:	FINFET FORMATION WITH LATE FIN REVEAL

Patent #:	9082698	Issue Dt:	07/14/2015	Application #:	14201122	Filing Dt:	03/07/2014
Title:	METHODS TO IMPROVE FINFET SEMICONDUCTOR DEVICE BEHAVIOR USING CO-IMPLANTATION UNDER THE CHANNEL REGION

Patent #:	9236299	Issue Dt:	01/12/2016	Application #:	14201255	Filing Dt:	03/07/2014
Publication #:	US20150255339	Pub Dt:	09/10/2015
Title:	METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE

Patent #:	8987083	Issue Dt:	03/24/2015	Application #:	14202985	Filing Dt:	03/10/2014
Title:	UNIFORM GATE HEIGHT FOR SEMICONDUCTOR STRUCTURE WITH N AND P TYPE FINS

Patent #:	NONE	Issue Dt:		Application #:	14206438	Filing Dt:	03/12/2014
Publication #:	US20150006835	Pub Dt:	01/01/2015
Title:	Backup Management for a Plurality of Logical Partitions

Patent #:	NONE	Issue Dt:		Application #:	14207319	Filing Dt:	03/12/2014
Publication #:	US20140190003	Pub Dt:	07/10/2014
Title:	SYSTEM AND METHOD FOR FORMING AN INDUCTOR WITH LAMINATED YOKE

Patent #:	9184288	Issue Dt:	11/10/2015	Application #:	14207822	Filing Dt:	03/13/2014
Publication #:	US20150263169	Pub Dt:	09/17/2015
Title:	SEMICONDUCTOR STRUCTURES WITH BRIDGING FILMS AND METHODS OF FABRICATION

Patent #:	9224811	Issue Dt:	12/29/2015	Application #:	14215398	Filing Dt:	03/17/2014
Publication #:	US20150263088	Pub Dt:	09/17/2015
Title:	STACKED SEMICONDUCTOR DEVICE

Patent #:	9666717	Issue Dt:	05/30/2017	Application #:	14217691	Filing Dt:	03/18/2014
Publication #:	US20150270400	Pub Dt:	09/24/2015
Title:	SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS

Patent #:	10854472	Issue Dt:	12/01/2020	Application #:	14219039	Filing Dt:	03/19/2014
Publication #:	US20150270142	Pub Dt:	09/24/2015
Title:	METHOD FOR FORMING A METAL GATE INCLUDING DE-OXIDATION OF AN OXIDIZED SURFACE OF THE METAL GATE UTILIZING A REDUCING AGENT

Patent #:	9443772	Issue Dt:	09/13/2016	Application #:	14219193	Filing Dt:	03/19/2014
Publication #:	US20150270178	Pub Dt:	09/24/2015
Title:	DIFFUSION-CONTROLLED SEMICONDUCTOR CONTACT CREATION

Patent #:	9553028	Issue Dt:	01/24/2017	Application #:	14219365	Filing Dt:	03/19/2014
Publication #:	US20150270176	Pub Dt:	09/24/2015
Title:	METHODS OF FORMING REDUCED RESISTANCE LOCAL INTERCONNECT STRUCTURES AND THE RESULTING DEVICES

Patent #:	9841773	Issue Dt:	12/12/2017	Application #:	14219460	Filing Dt:	03/19/2014
Publication #:	US20140316605	Pub Dt:	10/23/2014
Title:	Cooling System Management

Patent #:	8963255	Issue Dt:	02/24/2015	Application #:	14219910	Filing Dt:	03/19/2014
Publication #:	US20140203298	Pub Dt:	07/24/2014
Title:	STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS

Patent #:	NONE	Issue Dt:		Application #:	14220464	Filing Dt:	03/20/2014
Publication #:	US20150056967	Pub Dt:	02/26/2015
Title:	SYSTEM AND METHOD FOR COMMUNITY BASED MOBILE DEVICE PROFILING

Patent #:	8828862	Issue Dt:	09/09/2014	Application #:	14222931	Filing Dt:	03/24/2014
Publication #:	US20140203453	Pub Dt:	07/24/2014
Title:	AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION

Patent #:	9263580	Issue Dt:	02/16/2016	Application #:	14223373	Filing Dt:	03/24/2014
Publication #:	US20150270398	Pub Dt:	09/24/2015
Title:	METHODS OF FORMING ISOLATED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9064890	Issue Dt:	06/23/2015	Application #:	14223545	Filing Dt:	03/24/2014
Title:	METHODS OF FORMING ISOLATION MATERIAL ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9236345	Issue Dt:	01/12/2016	Application #:	14223592	Filing Dt:	03/24/2014
Publication #:	US20150270222	Pub Dt:	09/24/2015
Title:	OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION

Patent #:	9436845	Issue Dt:	09/06/2016	Application #:	14224099	Filing Dt:	03/25/2014
Publication #:	US20150278551	Pub Dt:	10/01/2015
Title:	PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY

Patent #:	9378093	Issue Dt:	06/28/2016	Application #:	14224431	Filing Dt:	03/25/2014
Publication #:	US20140325262	Pub Dt:	10/30/2014
Title:	CONTROLLING DATA STORAGE IN AN ARRAY OF STORAGE DEVICES

Patent #:	NONE	Issue Dt:		Application #:	14224654	Filing Dt:	03/25/2014
Publication #:	US20150142886	Pub Dt:	05/21/2015
Title:	SYSTEM AND METHOD FOR IDENTIFYING COLLABORATORS ON A SHARED MOBILE DEVICE

Patent #:	9324854	Issue Dt:	04/26/2016	Application #:	14226176	Filing Dt:	03/26/2014
Publication #:	US20140203339	Pub Dt:	07/24/2014
Title:	SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE

Patent #:	9142651	Issue Dt:	09/22/2015	Application #:	14226488	Filing Dt:	03/26/2014
Publication #:	US20150279963	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE SO AS TO REDUCE PUNCH-THROUGH LEAKAGE CURRENTS AND THE RESULTING DEVICE

Patent #:	9586291	Issue Dt:	03/07/2017	Application #:	14226953	Filing Dt:	03/27/2014
Publication #:	US20150035173	Pub Dt:	02/05/2015
Title:	ADHESIVES FOR BONDING HANDLER WAFERS TO DEVICE WAFERS AND ENABLING MID-WAVELENGTH INFRARED LASER ABLATION RELEASE

Patent #:	8850127	Issue Dt:	09/30/2014	Application #:	14227398	Filing Dt:	03/27/2014
Publication #:	US20140215159	Pub Dt:	07/31/2014
Title:	MANAGING CONCURRENT ACCESSES TO A CACHE

Patent #:	9484367	Issue Dt:	11/01/2016	Application #:	14228106	Filing Dt:	03/27/2014
Publication #:	US20140209985	Pub Dt:	07/31/2014
Title:	GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS

Patent #:	NONE	Issue Dt:		Application #:	14228890	Filing Dt:	03/28/2014
Publication #:	US20140231878	Pub Dt:	08/21/2014
Title:	COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY

Patent #:	8963283	Issue Dt:	02/24/2015	Application #:	14230039	Filing Dt:	03/31/2014
Publication #:	US20140210039	Pub Dt:	07/31/2014
Title:	METHOD OF FABRICATING ISOLATED CAPACITORS AND STRUCTURE THEREOF

Patent #:	9704973	Issue Dt:	07/11/2017	Application #:	14242130	Filing Dt:	04/01/2014
Publication #:	US20150279971	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS

Patent #:	9355936	Issue Dt:	05/31/2016	Application #:	14242203	Filing Dt:	04/01/2014
Publication #:	US20140209908	Pub Dt:	07/31/2014
Title:	FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

Patent #:	9720101	Issue Dt:	08/01/2017	Application #:	14242283	Filing Dt:	04/01/2014
Publication #:	US20150006112	Pub Dt:	01/01/2015
Title:	METHOD OF CONSUMER/PRODUCER RAW MATERIAL SELECTION

Patent #:	9299781	Issue Dt:	03/29/2016	Application #:	14242416	Filing Dt:	04/01/2014
Publication #:	US20150279935	Pub Dt:	10/01/2015
Title:	SEMICONDUCTOR DEVICES WITH CONTACT STRUCTURES AND A GATE STRUCTURE POSITIONED IN TRENCHES FORMED IN A LAYER OF MATERIAL

Patent #:	9245980	Issue Dt:	01/26/2016	Application #:	14242472	Filing Dt:	04/01/2014
Publication #:	US20150279973	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING SUBSTANTIALLY DEFECT-FREE, FULLY-STRAINED SILICON-GERMANIUM FINS FOR A FINFET SEMICONDUCTOR DEVICE

Patent #:	9524908	Issue Dt:	12/20/2016	Application #:	14242529	Filing Dt:	04/01/2014
Publication #:	US20150279959	Pub Dt:	10/01/2015
Title:	METHODS OF REMOVING PORTIONS OF FINS BY PREFORMING A SELECTIVELY ETCHABLE MATERIAL IN THE SUBSTRATE

Patent #:	9413169	Issue Dt:	08/09/2016	Application #:	14243295	Filing Dt:	04/02/2014
Publication #:	US20150288174	Pub Dt:	10/08/2015
Title:	ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH A FAIL-SAFE MECHANISM

Patent #:	9582629	Issue Dt:	02/28/2017	Application #:	14245868	Filing Dt:	04/04/2014
Publication #:	US20150286764	Pub Dt:	10/08/2015
Title:	METHODS OF GENERATING CIRCUIT LAYOUTS USING SELF-ALLIGNED DOUBLE PATTERNING (SADP) TECHNIQUES

Patent #:	9472455	Issue Dt:	10/18/2016	Application #:	14246197	Filing Dt:	04/07/2014
Publication #:	US20150287604	Pub Dt:	10/08/2015
Title:	METHODS OF CROSS-COUPLING LINE SEGMENTS ON A WAFER

Patent #:	9804231	Issue Dt:	10/31/2017	Application #:	14246376	Filing Dt:	04/07/2014
Publication #:	US20140316725	Pub Dt:	10/23/2014
Title:	POWER NOISE HISTOGRAM OF A COMPUTER SYSTEM

Patent #:	NONE	Issue Dt:		Application #:	14246459	Filing Dt:	04/07/2014
Publication #:	US20140323155	Pub Dt:	10/30/2014
Title:	RESPONDING TO AN UNAVAILABLE COMMUNICATION TARGET DEVICE

Patent #:	9202751	Issue Dt:	12/01/2015	Application #:	14246476	Filing Dt:	04/07/2014
Publication #:	US20150287636	Pub Dt:	10/08/2015
Title:	TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS

Patent #:	9087952	Issue Dt:	07/21/2015	Application #:	14246546	Filing Dt:	04/07/2014
Publication #:	US20140217485	Pub Dt:	08/07/2014
Title:	STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS

Patent #:	9620589	Issue Dt:	04/11/2017	Application #:	14246983	Filing Dt:	04/07/2014
Publication #:	US20150287782	Pub Dt:	10/08/2015
Title:	INTEGRATED CIRCUITS AND METHODS OF FABRICATION THEREOF

Patent #:	9679161	Issue Dt:	06/13/2017	Application #:	14248814	Filing Dt:	04/09/2014
Publication #:	US20140325212	Pub Dt:	10/30/2014
Title:	DISTRIBUTION OF ENCRYPTED INFORMATION IN MULTIPLE LOCATIONS

Patent #:	8918494	Issue Dt:	12/23/2014	Application #:	14249615	Filing Dt:	04/10/2014
Publication #:	US20140218398	Pub Dt:	08/07/2014
Title:	SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY

Patent #:	9219665	Issue Dt:	12/22/2015	Application #:	14249619	Filing Dt:	04/10/2014
Publication #:	US20140218399	Pub Dt:	08/07/2014
Title:	SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY

Patent #:	9184169	Issue Dt:	11/10/2015	Application #:	14250064	Filing Dt:	04/10/2014
Publication #:	US20150294976	Pub Dt:	10/15/2015
Title:	METHODS OF FORMING FINFET DEVICES IN DIFFERENT REGIONS OF AN INTEGRATED CIRCUIT PRODUCT

Patent #:	9392731	Issue Dt:	07/12/2016	Application #:	14250425	Filing Dt:	04/11/2014
Publication #:	US20150136365	Pub Dt:	05/21/2015
Title:	COOLING APPARATUS WITH DYNAMIC LOAD ADJUSTMENT

Patent #:	9093478	Issue Dt:	07/28/2015	Application #:	14250725	Filing Dt:	04/11/2014
Title:	INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET AND METHODS OF FORMING

Patent #:	9219696	Issue Dt:	12/22/2015	Application #:	14251386	Filing Dt:	04/11/2014
Publication #:	US20150036692	Pub Dt:	02/05/2015
Title:	INCREASED EFFICIENCY OF DATA PAYLOADS TO DATA ARRAYS ACCESSED THROUGH REGISTERS IN A DISTRIBUTED VIRTUAL BRIDGE

Patent #:	9389874	Issue Dt:	07/12/2016	Application #:	14253852	Filing Dt:	04/15/2014
Publication #:	US20150106612	Pub Dt:	04/16/2015
Title:	APPARATUS AND METHODS FOR AUTOMATICALLY REFLECTING CHANGES TO A COMPUTING SOLUTION IN AN IMAGE FOR THE COMPUTING SOLUTION

Patent #:	9299775	Issue Dt:	03/29/2016	Application #:	14254866	Filing Dt:	04/16/2014
Publication #:	US20150303249	Pub Dt:	10/22/2015
Title:	METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES

Patent #:	8889542	Issue Dt:	11/18/2014	Application #:	14255067	Filing Dt:	04/17/2014
Publication #:	US20140227870	Pub Dt:	08/14/2014
Title:	METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA

Patent #:	9240406	Issue Dt:	01/19/2016	Application #:	14257143	Filing Dt:	04/21/2014
Publication #:	US20150303191	Pub Dt:	10/22/2015
Title:	PRECISION TRENCH CAPACITOR

Patent #:	9461850	Issue Dt:	10/04/2016	Application #:	14257236	Filing Dt:	04/21/2014
Publication #:	US20140321582	Pub Dt:	10/30/2014
Title:	PARALLEL DATA PROCESSING

Patent #:	9337334	Issue Dt:	05/10/2016	Application #:	14257395	Filing Dt:	04/21/2014
Publication #:	US20150303313	Pub Dt:	10/22/2015
Title:	SEMICONDUCTOR MEMORY DEVICE EMPLOYING A FERROMAGNETIC GATE

Patent #:	9466868	Issue Dt:	10/11/2016	Application #:	14257464	Filing Dt:	04/21/2014
Publication #:	US20150303548	Pub Dt:	10/22/2015
Title:	RECONFIGURABLE BRANCH LINE COUPLER

Patent #:	8932949	Issue Dt:	01/13/2015	Application #:	14258063	Filing Dt:	04/22/2014
Publication #:	US20140217504	Pub Dt:	08/07/2014
Title:	FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE

Patent #:	9236269	Issue Dt:	01/12/2016	Application #:	14259179	Filing Dt:	04/23/2014
Publication #:	US20150311085	Pub Dt:	10/29/2015
Title:	FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH A PLANAR BLOCK AREA TO ENABLE VARIALBLE FIN PITCH AND WIDTH

Patent #:	9419082	Issue Dt:	08/16/2016	Application #:	14259726	Filing Dt:	04/23/2014
Publication #:	US20150311293	Pub Dt:	10/29/2015
Title:	SOURCE/DRAIN PROFILE ENGINEERING FOR ENHANCED P-MOSFET

Patent #:	NONE	Issue Dt:		Application #:	14259852	Filing Dt:	04/23/2014
Publication #:	US20140356670	Pub Dt:	12/04/2014
Title:	BATTERY SYSTEM FOR ELECTRICAL DEVICES

Patent #:	9196696	Issue Dt:	11/24/2015	Application #:	14260913	Filing Dt:	04/24/2014
Publication #:	US20140231920	Pub Dt:	08/21/2014
Title:	INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME

Patent #:	9530770	Issue Dt:	12/27/2016	Application #:	14261021	Filing Dt:	04/24/2014
Publication #:	US20150311272	Pub Dt:	10/29/2015
Title:	INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM GATE METAL AND METHODS FOR FABRICATING SAME

Patent #:	9311442	Issue Dt:	04/12/2016	Application #:	14261632	Filing Dt:	04/25/2014
Publication #:	US20150310155	Pub Dt:	10/29/2015
Title:	NET-VOLTAGE-AWARE OPTICAL PROXIMITY CORRECTION (OPC)

Patent #:	9735057	Issue Dt:	08/15/2017	Application #:	14262882	Filing Dt:	04/28/2014
Publication #:	US20150311120	Pub Dt:	10/29/2015
Title:	FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS

Patent #:	9479179	Issue Dt:	10/25/2016	Application #:	14263329	Filing Dt:	04/28/2014
Publication #:	US20150309113	Pub Dt:	10/29/2015
Title:	MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY

Patent #:	8921172	Issue Dt:	12/30/2014	Application #:	14264125	Filing Dt:	04/29/2014
Publication #:	US20140235021	Pub Dt:	08/21/2014
Title:	JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE

Patent #:	10700170	Issue Dt:	06/30/2020	Application #:	14264240	Filing Dt:	04/29/2014
Publication #:	US20150311199	Pub Dt:	10/29/2015
Title:	MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE

Patent #:	9324430	Issue Dt:	04/26/2016	Application #:	14265409	Filing Dt:	04/30/2014
Publication #:	US20150318043	Pub Dt:	11/05/2015
Title:	Method For Defining A Default State of a Charge Trap Based Memory Cell

Patent #:	9136321	Issue Dt:	09/15/2015	Application #:	14265410	Filing Dt:	04/30/2014
Title:	LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION

Patent #:	9312388	Issue Dt:	04/12/2016	Application #:	14267216	Filing Dt:	05/01/2014
Publication #:	US20150318398	Pub Dt:	11/05/2015
Title:	METHODS OF FORMING EPITAXIAL SEMICONDUCTOR MATERIAL IN TRENCHES LOCATED ABOVE THE SOURCE AND DRAIN REGIONS OF A SEMICONDUCTOR DEVICE

Patent #:	9793358	Issue Dt:	10/17/2017	Application #:	14267541	Filing Dt:	05/01/2014
Publication #:	US20150318351	Pub Dt:	11/05/2015
Title:	Non-Planar Semiconductor Device with Multiple-Head Epitaxial Structure on Fin

Patent #:	NONE	Issue Dt:		Application #:	14267634	Filing Dt:	05/01/2014
Publication #:	US20150318169	Pub Dt:	11/05/2015
Title:	METHODS OF FORMING EPITAXIAL SEMICONDUCTOR CLADDING MATERIAL ON FINS OF A FINFET SEMICONDUCTOR DEVICE

Patent #:	9209038	Issue Dt:	12/08/2015	Application #:	14267959	Filing Dt:	05/02/2014
Publication #:	US20150318181	Pub Dt:	11/05/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING

Patent #:	9263340	Issue Dt:	02/16/2016	Application #:	14268415	Filing Dt:	05/02/2014
Publication #:	US20150318215	Pub Dt:	11/05/2015
Title:	METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES

Patent #:	9064932	Issue Dt:	06/23/2015	Application #:	14268478	Filing Dt:	05/02/2014
Title:	METHODS OF FORMING GATE STRUCTURES BY A GATE-CUT-LAST PROCESS AND THE RESULTING STRUCTURES

Patent #:	10050118	Issue Dt:	08/14/2018	Application #:	14269566	Filing Dt:	05/05/2014
Publication #:	US20150318345	Pub Dt:	11/05/2015
Title:	SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING

Patent #:	9472572	Issue Dt:	10/18/2016	Application #:	14270833	Filing Dt:	05/06/2014
Publication #:	US20150325692	Pub Dt:	11/12/2015
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100

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Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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