USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 63 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Patent #:	9601495	Issue Dt:	03/21/2017	Application #:	14814322	Filing Dt:	07/30/2015
Publication #:	US20170033113	Pub Dt:	02/02/2017
Title:	THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH CO-FABRICATED ADJACENT CAPACITOR

Patent #:	9608112	Issue Dt:	03/28/2017	Application #:	14816337	Filing Dt:	08/03/2015
Publication #:	US20170040450	Pub Dt:	02/09/2017
Title:	BULEX CONTACTS IN ADVANCED FDSOI TECHNIQUES

Patent #:	10121711	Issue Dt:	11/06/2018	Application #:	14816708	Filing Dt:	08/03/2015
Publication #:	US20150340296	Pub Dt:	11/26/2015
Title:	PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE

Patent #:	9548388	Issue Dt:	01/17/2017	Application #:	14817504	Filing Dt:	08/04/2015
Publication #:	US20170040453	Pub Dt:	02/09/2017
Title:	FORMING FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9362403	Issue Dt:	06/07/2016	Application #:	14817628	Filing Dt:	08/04/2015
Publication #:	US20150340452	Pub Dt:	11/26/2015
Title:	BURIED FIN CONTACT STRUCTURES ON FINFET SEMICONDUCTOR DEVICES

Patent #:	9881738	Issue Dt:	01/30/2018	Application #:	14818342	Filing Dt:	08/05/2015
Publication #:	US20170040110	Pub Dt:	02/09/2017
Title:	CAPACITOR STRUCTURES WITH EMBEDDED ELECTRODES AND FABRICATION METHODS THEREOF

Patent #:	9460996	Issue Dt:	10/04/2016	Application #:	14818351	Filing Dt:	08/05/2015
Title:	INTEGRATED DEVICE WITH INDUCTIVE AND CAPACITIVE PORTIONS AND FABRICATION METHODS

Patent #:	9613861	Issue Dt:	04/04/2017	Application #:	14818419	Filing Dt:	08/05/2015
Publication #:	US20170040216	Pub Dt:	02/09/2017
Title:	DAMASCENE WIRES WITH TOP VIA STRUCTURES

Patent #:	9478538	Issue Dt:	10/25/2016	Application #:	14820661	Filing Dt:	08/07/2015
Title:	METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

Patent #:	9875940	Issue Dt:	01/23/2018	Application #:	14820701	Filing Dt:	08/07/2015
Publication #:	US20170040220	Pub Dt:	02/09/2017
Title:	METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

Patent #:	9711422	Issue Dt:	07/18/2017	Application #:	14821201	Filing Dt:	08/07/2015
Publication #:	US20150355253	Pub Dt:	12/10/2015
Title:	VISUALLY DETECTING ELECTROSTATIC DISCHARGE EVENTS

Patent #:	9758365	Issue Dt:	09/12/2017	Application #:	14821997	Filing Dt:	08/10/2015
Publication #:	US20150344293	Pub Dt:	12/03/2015
Title:	INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE

Patent #:	9768058	Issue Dt:	09/19/2017	Application #:	14822258	Filing Dt:	08/10/2015
Publication #:	US20170047242	Pub Dt:	02/16/2017
Title:	METHODS OF FORMING AIR GAPS IN METALLIZATION LAYERS ON INTEGRATED CIRCUIT PRODUCTS

Patent #:	9461111	Issue Dt:	10/04/2016	Application #:	14822345	Filing Dt:	08/10/2015
Publication #:	US20150349054	Pub Dt:	12/03/2015
Title:	DOUBLE/MULTIPLE FIN STRUCTURE FOR FINFET DEVICES

Patent #:	9570573	Issue Dt:	02/14/2017	Application #:	14822490	Filing Dt:	08/10/2015
Publication #:	US20170047418	Pub Dt:	02/16/2017
Title:	SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER

Patent #:	NONE	Issue Dt:		Application #:	14822533	Filing Dt:	08/10/2015
Publication #:	US20150348970	Pub Dt:	12/03/2015
Title:	GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS

Patent #:	9595493	Issue Dt:	03/14/2017	Application #:	14822597	Filing Dt:	08/10/2015
Publication #:	US20170047282	Pub Dt:	02/16/2017
Title:	REDUCING LINER CORROSION DURING METALLIZATION OF SEMICONDUCTOR DEVICES

Patent #:	9397049	Issue Dt:	07/19/2016	Application #:	14822654	Filing Dt:	08/10/2015
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	9263516	Issue Dt:	02/16/2016	Application #:	14823319	Filing Dt:	08/11/2015
Publication #:	US20160049468	Pub Dt:	02/18/2016
Title:	PRODUCT COMPRISED OF FINFET DEVICES WITH SINGLE DIFFUSION BREAK ISOLATION STRUCTURES

Patent #:	9613909	Issue Dt:	04/04/2017	Application #:	14824181	Filing Dt:	08/12/2015
Publication #:	US20170047290	Pub Dt:	02/16/2017
Title:	METHODS AND DEVICES FOR METAL FILLING PROCESSES

Patent #:	10158003	Issue Dt:	12/18/2018	Application #:	14824349	Filing Dt:	08/12/2015
Publication #:	US20170047411	Pub Dt:	02/16/2017
Title:	EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS

Patent #:	9837277	Issue Dt:	12/05/2017	Application #:	14824360	Filing Dt:	08/12/2015
Publication #:	US20170047256	Pub Dt:	02/16/2017
Title:	FORMING A CONTACT FOR A TALL FIN TRANSISTOR

Patent #:	9472490	Issue Dt:	10/18/2016	Application #:	14824409	Filing Dt:	08/12/2015
Title:	IC STRUCTURE WITH RECESSED SOLDER BUMP AREA AND METHODS OF FORMING SAME

Patent #:	9466680	Issue Dt:	10/11/2016	Application #:	14825375	Filing Dt:	08/13/2015
Publication #:	US20150349075	Pub Dt:	12/03/2015
Title:	INTEGRATED MULTIPLE GATE LENGTH SEMICONDUCTOR DEVICE INCLUDING SELF-ALIGNED CONTACTS

Patent #:	9577042	Issue Dt:	02/21/2017	Application #:	14825949	Filing Dt:	08/13/2015
Publication #:	US20170047404	Pub Dt:	02/16/2017
Title:	SEMICONDUCTOR STRUCTURE WITH MULTILAYER III-V HETEROSTRUCTURES

Patent #:	9653573	Issue Dt:	05/16/2017	Application #:	14827510	Filing Dt:	08/17/2015
Publication #:	US20150357434	Pub Dt:	12/10/2015
Title:	REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL

Patent #:	9741623	Issue Dt:	08/22/2017	Application #:	14828652	Filing Dt:	08/18/2015
Publication #:	US20170053835	Pub Dt:	02/23/2017
Title:	DUAL LINER CMOS INTEGRATION METHODS FOR FINFET DEVICES

Patent #:	9589658	Issue Dt:	03/07/2017	Application #:	14828770	Filing Dt:	08/18/2015
Publication #:	US20170053705	Pub Dt:	02/23/2017
Title:	DISTURB FREE BITCELL AND ARRAY

Patent #:	9905671	Issue Dt:	02/27/2018	Application #:	14829843	Filing Dt:	08/19/2015
Publication #:	US20170053997	Pub Dt:	02/23/2017
Title:	FORMING A GATE CONTACT IN THE ACTIVE AREA

Patent #:	10134585	Issue Dt:	11/20/2018	Application #:	14830131	Filing Dt:	08/19/2015
Publication #:	US20160056033	Pub Dt:	02/25/2016
Title:	LOW TEMPERATURE ATOMIC LAYER DEPOSITION OF OXIDES ON COMPOUND SEMICONDUCTORS

Patent #:	9735063	Issue Dt:	08/15/2017	Application #:	14830245	Filing Dt:	08/19/2015
Publication #:	US20170053836	Pub Dt:	02/23/2017
Title:	METHODS FOR FORMING FIN STRUCTURES

Patent #:	9647165	Issue Dt:	05/09/2017	Application #:	14830870	Filing Dt:	08/20/2015
Publication #:	US20170054049	Pub Dt:	02/23/2017
Title:	GERMANIUM PHOTODETECTOR WITH SOI DOPING SOURCE

Patent #:	9825093	Issue Dt:	11/21/2017	Application #:	14832108	Filing Dt:	08/21/2015
Publication #:	US20170053966	Pub Dt:	02/23/2017
Title:	FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS

Patent #:	9679959	Issue Dt:	06/13/2017	Application #:	14837288	Filing Dt:	08/27/2015
Publication #:	US20150364540	Pub Dt:	12/17/2015
Title:	CAPACITOR AND CONTACT STRUCTURES, AND FORMATION PROCESSES THEREOF

Patent #:	9589911	Issue Dt:	03/07/2017	Application #:	14837461	Filing Dt:	08/27/2015
Publication #:	US20170062354	Pub Dt:	03/02/2017
Title:	INTEGRATED CIRCUIT STRUCTURE WITH METAL CRACK STOP AND METHODS OF FORMING SAME

Patent #:	9613898	Issue Dt:	04/04/2017	Application #:	14838554	Filing Dt:	08/28/2015
Publication #:	US20170062333	Pub Dt:	03/02/2017
Title:	RAISED E-FUSE

Patent #:	10042969	Issue Dt:	08/07/2018	Application #:	14838705	Filing Dt:	08/28/2015
Publication #:	US20170061062	Pub Dt:	03/02/2017
Title:	RELIABILITY OF AN ELECTRONIC DEVICE

Patent #:	9698101	Issue Dt:	07/04/2017	Application #:	14839108	Filing Dt:	08/28/2015
Publication #:	US20170062325	Pub Dt:	03/02/2017
Title:	SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY

Patent #:	9817927	Issue Dt:	11/14/2017	Application #:	14841037	Filing Dt:	08/31/2015
Publication #:	US20170061044	Pub Dt:	03/02/2017
Title:	HARD MASK ETCH AND DIELECTRIC ETCH AWARE OVERLAP FOR VIA AND METAL LAYERS

Patent #:	9659785	Issue Dt:	05/23/2017	Application #:	14841951	Filing Dt:	09/01/2015
Publication #:	US20170062233	Pub Dt:	03/02/2017
Title:	FIN CUT FOR TAPER DEVICE

Patent #:	9666791	Issue Dt:	05/30/2017	Application #:	14841997	Filing Dt:	09/01/2015
Publication #:	US20160141489	Pub Dt:	05/19/2016
Title:	TOPOLOGICAL METHOD TO BUILD SELF-ALIGNED MTJ WITHOUT A MASK

Patent #:	9263290	Issue Dt:	02/16/2016	Application #:	14843085	Filing Dt:	09/02/2015
Publication #:	US20150380262	Pub Dt:	12/31/2015
Title:	SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH

Patent #:	9613862	Issue Dt:	04/04/2017	Application #:	14843109	Filing Dt:	09/02/2015
Publication #:	US20170062275	Pub Dt:	03/02/2017
Title:	CHAMFERLESS VIA STRUCTURES

Patent #:	9741625	Issue Dt:	08/22/2017	Application #:	14844163	Filing Dt:	09/03/2015
Publication #:	US20170069550	Pub Dt:	03/09/2017
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH STI STRUCTURES ON AN SOI SUBSTRATE

Patent #:	9704759	Issue Dt:	07/11/2017	Application #:	14845543	Filing Dt:	09/04/2015
Publication #:	US20170069547	Pub Dt:	03/09/2017
Title:	METHODS OF FORMING CMOS BASED INTEGRATED CIRCUIT PRODUCTS USING DISPOSABLE SPACERS

Patent #:	10038096	Issue Dt:	07/31/2018	Application #:	14847462	Filing Dt:	09/08/2015
Publication #:	US20170069759	Pub Dt:	03/09/2017
Title:	THREE-DIMENSIONAL FINFET TRANSISTOR WITH PORTION(S) OF THE FIN CHANNEL REMOVED IN GATE-LAST FLOW

Patent #:	9418935	Issue Dt:	08/16/2016	Application #:	14848558	Filing Dt:	09/09/2015
Title:	INTEGRATED CIRCUIT LINE ENDS FORMED USING ADDITIVE PROCESSING

Patent #:	10048311	Issue Dt:	08/14/2018	Application #:	14848804	Filing Dt:	09/09/2015
Publication #:	US20170067955	Pub Dt:	03/09/2017
Title:	DETECTION OF GATE-TO-SOURCE/DRAIN SHORTS

Patent #:	9564358	Issue Dt:	02/07/2017	Application #:	14849269	Filing Dt:	09/09/2015
Title:	FORMING RELIABLE CONTACTS ON TIGHT SEMICONDUCTOR PITCH

Patent #:	9478622	Issue Dt:	10/25/2016	Application #:	14849335	Filing Dt:	09/09/2015
Publication #:	US20150380502	Pub Dt:	12/31/2015
Title:	WRAP-AROUND CONTACT FOR FINFET

Patent #:	9589833	Issue Dt:	03/07/2017	Application #:	14850093	Filing Dt:	09/10/2015
Publication #:	US20170076978	Pub Dt:	03/16/2017
Title:	PREVENTING LEAKAGE INSIDE AIR-GAP SPACER DURING CONTACT FORMATION

Patent #:	9435947	Issue Dt:	09/06/2016	Application #:	14850381	Filing Dt:	09/10/2015
Publication #:	US20150378096	Pub Dt:	12/31/2015
Title:	INTEGRATION OF OPTICAL COMPONENTS IN INTEGRATED CIRCUITS BY SEPARATING TWO SUBSTRATES WITH AN INSULATION LAYER

Patent #:	10020395	Issue Dt:	07/10/2018	Application #:	14853012	Filing Dt:	09/14/2015
Publication #:	US20170077297	Pub Dt:	03/16/2017
Title:	SEMICONDUCTOR DEVICE WITH GATE INSIDE U-SHAPED CHANNEL AND METHODS OF MAKING SUCH A DEVICE

Patent #:	9711644	Issue Dt:	07/18/2017	Application #:	14853073	Filing Dt:	09/14/2015
Publication #:	US20170077301	Pub Dt:	03/16/2017
Title:	METHODS OF MAKING SOURCE/DRAIN REGIONS POSITIONED INSIDE U-SHAPED SEMICONDUCTOR MATERIAL USING SOURCE/DRAIN PLACEHOLDER STRUCTURES

Patent #:	9590118	Issue Dt:	03/07/2017	Application #:	14853146	Filing Dt:	09/14/2015
Publication #:	US20170077314	Pub Dt:	03/16/2017
Title:	WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	14853303	Filing Dt:	09/14/2015
Publication #:	US20170077234	Pub Dt:	03/16/2017
Title:	DEVICES AND METHODS OF CREATING ELASTIC RELAXATION OF EPITAXIALLY GROWN LATTICE MISMATCHED FILMS

Patent #:	10049942	Issue Dt:	08/14/2018	Application #:	14853373	Filing Dt:	09/14/2015
Publication #:	US20170076991	Pub Dt:	03/16/2017
Title:	ASYMMETRIC SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME

Patent #:	9553058	Issue Dt:	01/24/2017	Application #:	14854565	Filing Dt:	09/15/2015
Title:	WAFER BACKSIDE REDISTRIBUTION LAYER WARPAGE CONTROL

Patent #:	9412740	Issue Dt:	08/09/2016	Application #:	14855881	Filing Dt:	09/16/2015
Publication #:	US20160005733	Pub Dt:	01/07/2016
Title:	INTEGRATED CIRCUIT PRODUCT WITH A GATE HEIGHT REGISTRATION STRUCTURE

Patent #:	9903707	Issue Dt:	02/27/2018	Application #:	14857914	Filing Dt:	09/18/2015
Publication #:	US20170082423	Pub Dt:	03/23/2017
Title:	THREE-DIMENSIONAL SCATTEROMETRY FOR MEASURING DIELECTRIC THICKNESS

Patent #:	9508597	Issue Dt:	11/29/2016	Application #:	14858154	Filing Dt:	09/18/2015
Title:	3D FIN TUNNELING FIELD EFFECT TRANSISTOR

Patent #:	9704881	Issue Dt:	07/11/2017	Application #:	14859914	Filing Dt:	09/21/2015
Publication #:	US20170084629	Pub Dt:	03/23/2017
Title:	SEMICONDUCTOR DEVICE WITH REDUCED POLY SPACING EFFECT

Patent #:	9614058	Issue Dt:	04/04/2017	Application #:	14860276	Filing Dt:	09/21/2015
Publication #:	US20160013296	Pub Dt:	01/14/2016
Title:	METHODS OF FORMING LOW DEFECT REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES

Patent #:	9437501	Issue Dt:	09/06/2016	Application #:	14861326	Filing Dt:	09/22/2015
Title:	STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)

Patent #:	9576954	Issue Dt:	02/21/2017	Application #:	14862258	Filing Dt:	09/23/2015
Title:	NEW POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	9435852	Issue Dt:	09/06/2016	Application #:	14862587	Filing Dt:	09/23/2015
Title:	INTEGRATED CIRCUIT (IC) TEST STRUCTURE WITH MONITOR CHAIN AND TEST WIRES

Patent #:	9735111	Issue Dt:	08/15/2017	Application #:	14862894	Filing Dt:	09/23/2015
Publication #:	US20170084537	Pub Dt:	03/23/2017
Title:	DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD

Patent #:	9601428	Issue Dt:	03/21/2017	Application #:	14865589	Filing Dt:	09/25/2015
Publication #:	US20160284643	Pub Dt:	09/29/2016
Title:	SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF

Patent #:	9691897	Issue Dt:	06/27/2017	Application #:	14867193	Filing Dt:	09/28/2015
Publication #:	US20170092764	Pub Dt:	03/30/2017
Title:	THREE-DIMENSIONAL SEMICONDUCTOR TRANSISTOR WITH GATE CONTACT IN ACTIVE REGION

Patent #:	9812393	Issue Dt:	11/07/2017	Application #:	14867341	Filing Dt:	09/28/2015
Publication #:	US20170092583	Pub Dt:	03/30/2017
Title:	PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF

Patent #:	10797188	Issue Dt:	10/06/2020	Application #:	14867675	Filing Dt:	09/28/2015
Publication #:	US20160020353	Pub Dt:	01/21/2016
Title:	OPTICAL SEMICONDUCTOR STRUCTURE FOR EMITTING LIGHT THROUGH APERTURE

Patent #:	9536981	Issue Dt:	01/03/2017	Application #:	14868414	Filing Dt:	09/29/2015
Title:	FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9536750	Issue Dt:	01/03/2017	Application #:	14870932	Filing Dt:	09/30/2015
Title:	METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME

Patent #:	9620587	Issue Dt:	04/11/2017	Application #:	14871181	Filing Dt:	09/30/2015
Publication #:	US20160020204	Pub Dt:	01/21/2016
Title:	THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Patent #:	9972550	Issue Dt:	05/15/2018	Application #:	14873677	Filing Dt:	10/02/2015
Publication #:	US20170098585	Pub Dt:	04/06/2017
Title:	SOURCE/DRAIN EPITAXIAL ELECTRICAL MONITOR

Patent #:	9608096	Issue Dt:	03/28/2017	Application #:	14874039	Filing Dt:	10/02/2015
Publication #:	US20170098699	Pub Dt:	04/06/2017
Title:	IMPLEMENTING STRESS IN A BIPOLAR JUNCTION TRANSISTOR

Patent #:	10128114	Issue Dt:	11/13/2018	Application #:	14874623	Filing Dt:	10/05/2015
Publication #:	US20170098544	Pub Dt:	04/06/2017
Title:	AMORPHIZATION INDUCED METAL-SILICON CONTACT FORMATION

Patent #:	9754911	Issue Dt:	09/05/2017	Application #:	14875032	Filing Dt:	10/05/2015
Publication #:	US20170098623	Pub Dt:	04/06/2017
Title:	IC STRUCTURE WITH ANGLED INTERCONNECT ELEMENTS

Patent #:	9559009	Issue Dt:	01/31/2017	Application #:	14876212	Filing Dt:	10/06/2015
Publication #:	US20160027700	Pub Dt:	01/28/2016
Title:	GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

Patent #:	9691787	Issue Dt:	06/27/2017	Application #:	14878332	Filing Dt:	10/08/2015
Publication #:	US20170104011	Pub Dt:	04/13/2017
Title:	CO-FABRICATED BULK DEVICES AND SEMICONDUCTOR-ON-INSULATOR DEVICES

Patent #:	9478625	Issue Dt:	10/25/2016	Application #:	14878440	Filing Dt:	10/08/2015
Title:	METAL RESISTOR USING FINFET-BASED REPLACEMENT GATE PROCESS

Patent #:	9818873	Issue Dt:	11/14/2017	Application #:	14879220	Filing Dt:	10/09/2015
Publication #:	US20170104100	Pub Dt:	04/13/2017
Title:	FORMING STRESSED EPITAXIAL LAYERS BETWEEN GATES SEPARATED BY DIFFERENT PITCHES

Patent #:	10622457	Issue Dt:	04/14/2020	Application #:	14879968	Filing Dt:	10/09/2015
Publication #:	US20170104082	Pub Dt:	04/13/2017
Title:	FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS

Patent #:	9397175	Issue Dt:	07/19/2016	Application #:	14881766	Filing Dt:	10/13/2015
Publication #:	US20160035841	Pub Dt:	02/04/2016
Title:	MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS

Patent #:	9852954	Issue Dt:	12/26/2017	Application #:	14882640	Filing Dt:	10/14/2015
Publication #:	US20160035630	Pub Dt:	02/04/2016
Title:	METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES

Patent #:	9589806	Issue Dt:	03/07/2017	Application #:	14886424	Filing Dt:	10/19/2015
Title:	INTEGRATED CIRCUIT WITH REPLACEMENT GATE STACKS AND METHOD OF FORMING SAME

Patent #:	9660027	Issue Dt:	05/23/2017	Application #:	14887572	Filing Dt:	10/20/2015
Publication #:	US20170110539	Pub Dt:	04/20/2017
Title:	EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR

Patent #:	9735242	Issue Dt:	08/15/2017	Application #:	14887927	Filing Dt:	10/20/2015
Publication #:	US20170110549	Pub Dt:	04/20/2017
Title:	SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

Patent #:	9711513	Issue Dt:	07/18/2017	Application #:	14918048	Filing Dt:	10/20/2015
Publication #:	US20170047336	Pub Dt:	02/16/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF

Patent #:	10049570	Issue Dt:	08/14/2018	Application #:	14918776	Filing Dt:	10/21/2015
Publication #:	US20170116849	Pub Dt:	04/27/2017
Title:	CONTROLLING RIGHT-OF-WAY FOR PRIORITY VEHICLES

Patent #:	9875905	Issue Dt:	01/23/2018	Application #:	14920179	Filing Dt:	10/22/2015
Publication #:	US20170117156	Pub Dt:	04/27/2017
Title:	FINFET DEVICES HAVING FINS WITH A TAPERED CONFIGURATION AND METHODS OF FABRICATING THE SAME

Patent #:	10032884	Issue Dt:	07/24/2018	Application #:	14920354	Filing Dt:	10/22/2015
Publication #:	US20170117274	Pub Dt:	04/27/2017
Title:	UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING

Patent #:	10228685	Issue Dt:	03/12/2019	Application #:	14920376	Filing Dt:	10/22/2015
Publication #:	US20170115658	Pub Dt:	04/27/2017
Title:	Use of Multivariate Models to Control Manufacturing Operations

Patent #:	9722045	Issue Dt:	08/01/2017	Application #:	14921434	Filing Dt:	10/23/2015
Publication #:	US20170117387	Pub Dt:	04/27/2017
Title:	BUFFER LAYER FOR MODULATING Vt ACROSS DEVICES

Patent #:	10078107	Issue Dt:	09/18/2018	Application #:	14924439	Filing Dt:	10/27/2015
Publication #:	US20170115337	Pub Dt:	04/27/2017
Title:	WAFER LEVEL ELECTRICAL TEST FOR OPTICAL PROXIMITY CORRECTION AND/OR ETCH BIAS

Patent #:	9362284	Issue Dt:	06/07/2016	Application #:	14924486	Filing Dt:	10/27/2015
Publication #:	US20160049400	Pub Dt:	02/18/2016
Title:	THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES

Patent #:	9947774	Issue Dt:	04/17/2018	Application #:	14925630	Filing Dt:	10/28/2015
Publication #:	US20170125551	Pub Dt:	05/04/2017
Title:	FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING

Patent #:	9660040	Issue Dt:	05/23/2017	Application #:	14926657	Filing Dt:	10/29/2015
Publication #:	US20160049481	Pub Dt:	02/18/2016
Title:	TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS

Patent #:	9754903	Issue Dt:	09/05/2017	Application #:	14926880	Filing Dt:	10/29/2015
Publication #:	US20170125361	Pub Dt:	05/04/2017
Title:	SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE

100

Patent #:	9741853	Issue Dt:	08/22/2017	Application #:	14926897	Filing Dt:	10/29/2015
Publication #:	US20170125587	Pub Dt:	05/04/2017
Title:	STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

Search Results as of: 05/11/2024 09:58 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6