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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 65 of 85
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Patent #:	9721949	Issue Dt:	08/01/2017	Application #:	15010189	Filing Dt:	01/29/2016
Publication #:	US20170221888	Pub Dt:	08/03/2017
Title:	METHOD OF FORMING SUPER STEEP RETROGRADE WELLS ON FINFET

Patent #:	10090255	Issue Dt:	10/02/2018	Application #:	15010868	Filing Dt:	01/29/2016
Publication #:	US20170221837	Pub Dt:	08/03/2017
Title:	DICING CHANNELS FOR GLASS INTERPOSERS

Patent #:	9841134	Issue Dt:	12/12/2017	Application #:	15011893	Filing Dt:	02/01/2016
Publication #:	US20170219157	Pub Dt:	08/03/2017
Title:	SYSTEM MANAGING MOBILE SENSORS FOR CONTINUOUS MONITORING OF PIPE NETWORKS

Patent #:	9502507	Issue Dt:	11/22/2016	Application #:	15012107	Filing Dt:	02/01/2016
Title:	METHODS OF FORMING STRAINED CHANNEL REGIONS ON FINFET DEVICES

Patent #:	9647145	Issue Dt:	05/09/2017	Application #:	15012563	Filing Dt:	02/01/2016
Title:	METHOD, APPARATUS, AND SYSTEM FOR INCREASING JUNCTION ELECTRIC FIELD OF HIGH CURRENT DIODE

Patent #:	9508850	Issue Dt:	11/29/2016	Application #:	15012760	Filing Dt:	02/01/2016
Publication #:	US20160163862	Pub Dt:	06/09/2016
Title:	EPITAXIAL BLOCK LAYER FOR A FIN FIELD EFFECT TRANSISTOR DEVICE

Patent #:	10429414	Issue Dt:	10/01/2019	Application #:	15013106	Filing Dt:	02/02/2016
Publication #:	US20170219631	Pub Dt:	08/03/2017
Title:	MULTIPLE CONTACT PROBE HEAD DISASSEMBLY METHOD AND SYSTEM

Patent #:	9748235	Issue Dt:	08/29/2017	Application #:	15013169	Filing Dt:	02/02/2016
Publication #:	US20170221889	Pub Dt:	08/03/2017
Title:	GATE STACK FOR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING SAME

Patent #:	9812447	Issue Dt:	11/07/2017	Application #:	15013393	Filing Dt:	02/02/2016
Publication #:	US20170221887	Pub Dt:	08/03/2017
Title:	BIPOLAR JUNCTION TRANSISTORS WITH EXTRINSIC DEVICE REGIONS FREE OF TRENCH ISOLATION

Patent #:	9721948	Issue Dt:	08/01/2017	Application #:	15013411	Filing Dt:	02/02/2016
Publication #:	US20170221882	Pub Dt:	08/03/2017
Title:	SWITCH IMPROVEMENT USING LAYOUT OPTIMIZATION

Patent #:	9735061	Issue Dt:	08/15/2017	Application #:	15014150	Filing Dt:	02/03/2016
Publication #:	US20170221764	Pub Dt:	08/03/2017
Title:	METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING

Patent #:	9673376	Issue Dt:	06/06/2017	Application #:	15014212	Filing Dt:	02/03/2016
Title:	METHODS TO UTILIZE PIEZOELECTRIC MATERIALS AS GATE DIELECTRIC IN HIGH FREQUENCY RBTs IN AN IC DEVICE

Patent #:	9761526	Issue Dt:	09/12/2017	Application #:	15014759	Filing Dt:	02/03/2016
Publication #:	US20170221831	Pub Dt:	08/03/2017
Title:	INTERCONNECT STRUCTURE HAVING TUNGSTEN CONTACT COPPER WIRING

Patent #:	10056306	Issue Dt:	08/21/2018	Application #:	15015478	Filing Dt:	02/04/2016
Publication #:	US20170229358	Pub Dt:	08/10/2017
Title:	TEST STRUCUTRE FOR MONITORING INTERFACE DELAMINATION

Patent #:	9870936	Issue Dt:	01/16/2018	Application #:	15015578	Filing Dt:	02/04/2016
Publication #:	US20160155654	Pub Dt:	06/02/2016
Title:	WAFER CARRIER PURGE APPARATUSES, AUTOMATED MECHANICAL HANDLING SYSTEMS INCLUDING THE SAME, AND METHODS OF HANDLING A WAFER CARRIER DURING INTEGRATED CIRCUIT FABRICATION

Patent #:	9995692	Issue Dt:	06/12/2018	Application #:	15015614	Filing Dt:	02/04/2016
Publication #:	US20160239012	Pub Dt:	08/18/2016
Title:	SYSTEMS AND METHODS OF CONTROLLING A MANUFACTURING PROCESS FOR A MICROELECTRONIC COMPONENT

Patent #:	9852959	Issue Dt:	12/26/2017	Application #:	15017004	Filing Dt:	02/05/2016
Publication #:	US20170229362	Pub Dt:	08/10/2017
Title:	CORROSION RESISTANT CHIP SIDEWALL CONNECTION WITH CRACKSTOP AND HERMETIC SEAL

Patent #:	9947788	Issue Dt:	04/17/2018	Application #:	15019273	Filing Dt:	02/09/2016
Publication #:	US20170229578	Pub Dt:	08/10/2017
Title:	DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION

Patent #:	10440789	Issue Dt:	10/08/2019	Application #:	15024607	Filing Dt:	03/25/2016
Publication #:	US20160249425	Pub Dt:	08/25/2016
Title:	Event Based Integrated Driver System and Light Emitting Diode (LED) Driver System

Patent #:	9510418	Issue Dt:	11/29/2016	Application #:	15024633	Filing Dt:	03/25/2016
Publication #:	US20160242253	Pub Dt:	08/18/2016
Title:	LIGHT EMITTING DIODE (LED) DIMMER CIRCUIT AND DIMMING METHOD FOR LEDS

Patent #:	9798852	Issue Dt:	10/24/2017	Application #:	15040235	Filing Dt:	02/10/2016
Publication #:	US20160378906	Pub Dt:	12/29/2016
Title:	METHODS OF DESIGN RULE CHECKING OF CIRCUIT DESIGNS

Patent #:	9954002	Issue Dt:	04/24/2018	Application #:	15040307	Filing Dt:	02/10/2016
Publication #:	US20160163739	Pub Dt:	06/09/2016
Title:	MULTI-GATE FIELD EFFECT TRANSISTOR (FET) INCLUDING ISOLATED FIN BODY

Patent #:	9898573	Issue Dt:	02/20/2018	Application #:	15040453	Filing Dt:	02/10/2016
Publication #:	US20170228491	Pub Dt:	08/10/2017
Title:	DESIGN RULE AND PROCESS ASSUMPTION CO-OPTIMIZATION USING FEATURE-SPECIFIC LAYOUT-BASED STATISTICAL ANALYSES

Patent #:	9601490	Issue Dt:	03/21/2017	Application #:	15040953	Filing Dt:	02/10/2016
Publication #:	US20160163705	Pub Dt:	06/09/2016
Title:	FINFET WORK FUNCTION METAL FORMATION

Patent #:	9703036	Issue Dt:	07/11/2017	Application #:	15041103	Filing Dt:	02/11/2016
Publication #:	US20160170140	Pub Dt:	06/16/2016
Title:	OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES

Patent #:	9791771	Issue Dt:	10/17/2017	Application #:	15041476	Filing Dt:	02/11/2016
Publication #:	US20170235217	Pub Dt:	08/17/2017
Title:	A PHOTOMASK STRUCTURE WITH AN ETCH STOP LAYER THAT ENABLES REPAIRS OF DETECTED DEFECTS THEREIN AND EXTREME ULTRAVIOLET (EUV) PHOTOLITHOGRAPHY METHODS USING THE PHOTOMASK STRUCTURE

Patent #:	9536992	Issue Dt:	01/03/2017	Application #:	15041581	Filing Dt:	02/11/2016
Publication #:	US20160163821	Pub Dt:	06/09/2016
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF

Patent #:	9698179	Issue Dt:	07/04/2017	Application #:	15042547	Filing Dt:	02/12/2016
Publication #:	US20170040354	Pub Dt:	02/09/2017
Title:	CAPACITOR STRUCTURE AND METHOD OF FORMING A CAPACITOR STRUCTURE

Patent #:	10114919	Issue Dt:	10/30/2018	Application #:	15042815	Filing Dt:	02/12/2016
Publication #:	US20170235865	Pub Dt:	08/17/2017
Title:	PLACING AND ROUTING METHOD FOR IMPLEMENTING BACK BIAS IN FDSOI

Patent #:	9786765	Issue Dt:	10/10/2017	Application #:	15044431	Filing Dt:	02/16/2016
Publication #:	US20170236917	Pub Dt:	08/17/2017
Title:	FINFET HAVING NOTCHED FINS AND METHOD OF FORMING SAME

Patent #:	9898572	Issue Dt:	02/20/2018	Application #:	15045466	Filing Dt:	02/17/2016
Publication #:	US20170235867	Pub Dt:	08/17/2017
Title:	METAL LINE LAYOUT BASED ON LINE SHIFTING

Patent #:	9589847	Issue Dt:	03/07/2017	Application #:	15046916	Filing Dt:	02/18/2016
Title:	METAL LAYER TIP TO TIP SHORT

Patent #:	9761480	Issue Dt:	09/12/2017	Application #:	15047137	Filing Dt:	02/18/2016
Publication #:	US20170243782	Pub Dt:	08/24/2017
Title:	METHODS OF FORMING FIELD EFFECT TRANSISTOR (FET) AND NON-FET CIRCUIT ELEMENTS ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE

Patent #:	9704600	Issue Dt:	07/11/2017	Application #:	15047271	Filing Dt:	02/18/2016
Title:	METHOD, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF WRITE-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY

Patent #:	9916212	Issue Dt:	03/13/2018	Application #:	15047395	Filing Dt:	02/18/2016
Publication #:	US20170242759	Pub Dt:	08/24/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR TARGETED HEALING OF WRITE FAILS THROUGH BIAS TEMPERATURE INSTABILITY

Patent #:	9842184	Issue Dt:	12/12/2017	Application #:	15047878	Filing Dt:	02/19/2016
Publication #:	US20170076031	Pub Dt:	03/16/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN FOR SOI TECHNOLOGY

Patent #:	10177091	Issue Dt:	01/08/2019	Application #:	15048114	Filing Dt:	02/19/2016
Publication #:	US20170243827	Pub Dt:	08/24/2017
Title:	INTERCONNECT STRUCTURE AND METHOD OF FORMING

Patent #:	10340177	Issue Dt:	07/02/2019	Application #:	15048493	Filing Dt:	02/19/2016
Publication #:	US20170243783	Pub Dt:	08/24/2017
Title:	DEVICES AND METHODS OF REDUCING DAMAGE DURING BEOL M1 INTEGRATION

Patent #:	9817063	Issue Dt:	11/14/2017	Application #:	15048704	Filing Dt:	02/19/2016
Publication #:	US20170242067	Pub Dt:	08/24/2017
Title:	INTERCONNECT RELIABILITY STRUCTURES

Patent #:	9773811	Issue Dt:	09/26/2017	Application #:	15049572	Filing Dt:	02/22/2016
Publication #:	US20170243894	Pub Dt:	08/24/2017
Title:	REDUCING ANTENNA EFFECTS IN SOI DEVICES

Patent #:	9761495	Issue Dt:	09/12/2017	Application #:	15050540	Filing Dt:	02/23/2016
Publication #:	US20170243790	Pub Dt:	08/24/2017
Title:	METHODS OF PERFORMING CONCURRENT FIN AND GATE CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9847333	Issue Dt:	12/19/2017	Application #:	15051420	Filing Dt:	02/23/2016
Publication #:	US20160268260	Pub Dt:	09/15/2016
Title:	REDUCING RISK OF PUNCH-THROUGH IN FINFET SEMICONDUCTOR STRUCTURE

Patent #:	9660075	Issue Dt:	05/23/2017	Application #:	15051734	Filing Dt:	02/24/2016
Publication #:	US20160172493	Pub Dt:	06/16/2016
Title:	INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME

Patent #:	9972548	Issue Dt:	05/15/2018	Application #:	15051791	Filing Dt:	02/24/2016
Publication #:	US20170030849	Pub Dt:	02/02/2017
Title:	FINFET ELECTRICAL CHARACTERIZATION WITH ENHANCED HALL EFFECT AND PROBE

Patent #:	9972537	Issue Dt:	05/15/2018	Application #:	15052098	Filing Dt:	02/24/2016
Publication #:	US20170243791	Pub Dt:	08/24/2017
Title:	METHODS OF FORMING GRAPHENE CONTACTS ON SOURCE/DRAIN REGIONS OF FINFET DEVICES

Patent #:	9640608	Issue Dt:	05/02/2017	Application #:	15052961	Filing Dt:	02/25/2016
Title:	SERIAL CAPACITOR DEVICE WITH MIDDLE ELECTRODE CONTACT AND METHODS OF MAKING SAME

Patent #:	9748259	Issue Dt:	08/29/2017	Application #:	15053485	Filing Dt:	02/25/2016
Publication #:	US20170250191	Pub Dt:	08/31/2017
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	9779943	Issue Dt:	10/03/2017	Application #:	15053818	Filing Dt:	02/25/2016
Publication #:	US20170250080	Pub Dt:	08/31/2017
Title:	COMPENSATING FOR LITHOGRAPHIC LIMITATIONS IN FABRICATING SEMICONDUCTOR INTERCONNECT STRUCTURES

Patent #:	9748392	Issue Dt:	08/29/2017	Application #:	15053867	Filing Dt:	02/25/2016
Publication #:	US20170250284	Pub Dt:	08/31/2017
Title:	FORMATION OF WORK-FUNCTION LAYERS FOR GATE ELECTRODE USING A GAS CLUSTER ION BEAM

Patent #:	9929159	Issue Dt:	03/27/2018	Application #:	15053984	Filing Dt:	02/25/2016
Publication #:	US20170250183	Pub Dt:	08/31/2017
Title:	METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH SILICON AND SILICON GERMANIUM FINS

Patent #:	9748236	Issue Dt:	08/29/2017	Application #:	15054355	Filing Dt:	02/26/2016
Publication #:	US20170250181	Pub Dt:	08/31/2017
Title:	FINFET DEVICE WITH ENLARGED CHANNEL REGIONS

Patent #:	9466616	Issue Dt:	10/11/2016	Application #:	15054951	Filing Dt:	02/26/2016
Publication #:	US20160181285	Pub Dt:	06/23/2016
Title:	UNIFORM JUNCTION FORMATION IN FINFETS

Patent #:	10170482	Issue Dt:	01/01/2019	Application #:	15055571	Filing Dt:	02/27/2016
Publication #:	US20170162582	Pub Dt:	06/08/2017
Title:	STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

Patent #:	9627535	Issue Dt:	04/18/2017	Application #:	15055805	Filing Dt:	02/29/2016
Publication #:	US20160181426	Pub Dt:	06/23/2016
Title:	Semiconductor Devices with an Etch Stop Layer on Gate End-Portions Located above an Isolation Region

Patent #:	9748145	Issue Dt:	08/29/2017	Application #:	15055826	Filing Dt:	02/29/2016
Publication #:	US20170250117	Pub Dt:	08/31/2017
Title:	SEMICONDUCTOR DEVICES WITH VARYING THRESHOLD VOLTAGE AND FABRICATION METHODS THEREOF

Patent #:	9754792	Issue Dt:	09/05/2017	Application #:	15056513	Filing Dt:	02/29/2016
Publication #:	US20170250088	Pub Dt:	08/31/2017
Title:	FIN CUTTING PROCESS FOR MANUFACTURING FINFET SEMICONDUCTOR DEVICES

Patent #:	9748335	Issue Dt:	08/29/2017	Application #:	15056966	Filing Dt:	02/29/2016
Publication #:	US20170250250	Pub Dt:	08/31/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS

Patent #:	9905668	Issue Dt:	02/27/2018	Application #:	15057791	Filing Dt:	03/01/2016
Publication #:	US20160181393	Pub Dt:	06/23/2016
Title:	BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATION

Patent #:	9978588	Issue Dt:	05/22/2018	Application #:	15058669	Filing Dt:	03/02/2016
Publication #:	US20160181092	Pub Dt:	06/23/2016
Title:	NITRIDE SPACER FOR PROTECTING A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE

Patent #:	9698269	Issue Dt:	07/04/2017	Application #:	15059793	Filing Dt:	03/03/2016
Publication #:	US20160190324	Pub Dt:	06/30/2016
Title:	CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS

Patent #:	9514942	Issue Dt:	12/06/2016	Application #:	15060009	Filing Dt:	03/03/2016
Title:	METHOD OF FORMING A GATE MASK FOR FABRICATING A STRUCTURE OF GATE LINES

Patent #:	9871057	Issue Dt:	01/16/2018	Application #:	15060067	Filing Dt:	03/03/2016
Publication #:	US20170256565	Pub Dt:	09/07/2017
Title:	FIELD-EFFECT TRANSISTORS WITH A NON-RELAXED STRAINED CHANNEL

Patent #:	9472464	Issue Dt:	10/18/2016	Application #:	15060691	Filing Dt:	03/04/2016
Title:	METHODS TO UTILIZE MERGED SPACERS FOR USE IN FIN GENERATION IN TAPERED IC DEVICES

Patent #:	9812543	Issue Dt:	11/07/2017	Application #:	15060761	Filing Dt:	03/04/2016
Publication #:	US20170256624	Pub Dt:	09/07/2017
Title:	COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIGHTS AND METHODS OF MANUFACTURING SAME

Patent #:	9647124	Issue Dt:	05/09/2017	Application #:	15060806	Filing Dt:	03/04/2016
Publication #:	US20160190344	Pub Dt:	06/30/2016
Title:	SEMICONDUCTOR DEVICES WITH GRAPHENE NANORIBBONS

Patent #:	9859177	Issue Dt:	01/02/2018	Application #:	15062484	Filing Dt:	03/07/2016
Publication #:	US20170256468	Pub Dt:	09/07/2017
Title:	TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE METALIZATION

Patent #:	9634003	Issue Dt:	04/25/2017	Application #:	15063563	Filing Dt:	03/08/2016
Publication #:	US20160225763	Pub Dt:	08/04/2016
Title:	SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS

Patent #:	9478662	Issue Dt:	10/25/2016	Application #:	15063604	Filing Dt:	03/08/2016
Publication #:	US20160268415	Pub Dt:	09/15/2016
Title:	GATE AND SOURCE/DRAIN CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE

Patent #:	10014279	Issue Dt:	07/03/2018	Application #:	15064755	Filing Dt:	03/09/2016
Publication #:	US20160190104	Pub Dt:	06/30/2016
Title:	METHODS OF FORMING 3-D INTEGRATED SEMICONDUCTOR DEVICES HAVING INTERMEDIATE HEAT SPREADING CAPABILITIES

Patent #:	9673220	Issue Dt:	06/06/2017	Application #:	15065331	Filing Dt:	03/09/2016
Title:	CHIP STRUCTURES WITH DISTRIBUTED WIRING

Patent #:	9786606	Issue Dt:	10/10/2017	Application #:	15066374	Filing Dt:	03/10/2016
Publication #:	US20160190067	Pub Dt:	06/30/2016
Title:	SEMICONDUCTOR STRUCTURES WITH ISOLATED OHMIC TRENCHES AND STAND-ALONE ISOLATION TRENCHES AND RELATED METHOD

Patent #:	9589836	Issue Dt:	03/07/2017	Application #:	15067365	Filing Dt:	03/11/2016
Title:	METHODS OF FORMING RUTHENIUM CONDUCTIVE STRUCTURES IN A METALLIZATION LAYER

Patent #:	9536991	Issue Dt:	01/03/2017	Application #:	15067435	Filing Dt:	03/11/2016
Title:	SINGLE DIFFUSION BREAK STRUCTURE

Patent #:	10236350	Issue Dt:	03/19/2019	Application #:	15067540	Filing Dt:	03/11/2016
Publication #:	US20170263715	Pub Dt:	09/14/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW

Patent #:	9818651	Issue Dt:	11/14/2017	Application #:	15067953	Filing Dt:	03/11/2016
Publication #:	US20170263506	Pub Dt:	09/14/2017
Title:	METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

Patent #:	9933577	Issue Dt:	04/03/2018	Application #:	15068059	Filing Dt:	03/11/2016
Publication #:	US20170261693	Pub Dt:	09/14/2017
Title:	PHOTONICS CHIP

Patent #:	9478462	Issue Dt:	10/25/2016	Application #:	15071255	Filing Dt:	03/16/2016
Title:	SAV USING SELECTIVE SAQP/SADP

Patent #:	9698241	Issue Dt:	07/04/2017	Application #:	15071600	Filing Dt:	03/16/2016
Title:	INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATES AND METHODS FOR FABRICATING THE SAME

Patent #:	9716136	Issue Dt:	07/25/2017	Application #:	15071641	Filing Dt:	03/16/2016
Title:	EMBEDDED POLYSILICON RESISTORS WITH CRYSTALLIZATION BARRIERS

Patent #:	9864831	Issue Dt:	01/09/2018	Application #:	15071890	Filing Dt:	03/16/2016
Publication #:	US20160196381	Pub Dt:	07/07/2016
Title:	METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF

Patent #:	9859125	Issue Dt:	01/02/2018	Application #:	15072626	Filing Dt:	03/17/2016
Publication #:	US20170271163	Pub Dt:	09/21/2017
Title:	BLOCK PATTERNING METHOD ENABLING MERGED SPACE IN SRAM WITH HETEROGENEOUS MANDREL

Patent #:	9406767	Issue Dt:	08/02/2016	Application #:	15073050	Filing Dt:	03/17/2016
Title:	POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	9647093	Issue Dt:	05/09/2017	Application #:	15073065	Filing Dt:	03/17/2016
Publication #:	US20170062590	Pub Dt:	03/02/2017
Title:	FIN CUT FOR TAPER DEVICE

Patent #:	9620505	Issue Dt:	04/11/2017	Application #:	15073100	Filing Dt:	03/17/2016
Publication #:	US20160197072	Pub Dt:	07/07/2016
Title:	SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS

Patent #:	9966457	Issue Dt:	05/08/2018	Application #:	15073740	Filing Dt:	03/18/2016
Publication #:	US20170271483	Pub Dt:	09/21/2017
Title:	TRANSISTOR STRUCTURE WITH VARIED GATE CROSS-SECTIONAL AREA

Patent #:	9508853	Issue Dt:	11/29/2016	Application #:	15073936	Filing Dt:	03/18/2016
Publication #:	US20160204261	Pub Dt:	07/14/2016
Title:	CHANNEL CLADDING LAST PROCESS FLOW FOR FORMING A CHANNEL REGION ON A FINFET DEVICE HAVING A REDUCED SIZE FIN IN THE CHANNEL REGION

Patent #:	9711624	Issue Dt:	07/18/2017	Application #:	15074235	Filing Dt:	03/18/2016
Title:	METHODS FOR DIRECT MEASUREMENT OF PITCH-WALKING IN LITHOGRAPHIC MULTIPLE PATTERNING

Patent #:	9881841	Issue Dt:	01/30/2018	Application #:	15074483	Filing Dt:	03/18/2016
Publication #:	US20160204038	Pub Dt:	07/14/2016
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES

Patent #:	9666589	Issue Dt:	05/30/2017	Application #:	15075352	Filing Dt:	03/21/2016
Title:	FINFET BASED FLASH MEMORY CELL

Patent #:	9768084	Issue Dt:	09/19/2017	Application #:	15075378	Filing Dt:	03/21/2016
Publication #:	US20170271220	Pub Dt:	09/21/2017
Title:	INLINE MONITORING OF TRANSISTOR-TO-TRANSISTOR CRITICAL DIMENSION

Patent #:	9431306	Issue Dt:	08/30/2016	Application #:	15075437	Filing Dt:	03/21/2016
Publication #:	US20160225677	Pub Dt:	08/04/2016
Title:	METHODS OF FORMING FIN ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES USING AN OXIDATION-BLOCKING LAYER OF MATERIAL AND BY PERFORMING A FIN-TRIMMING PROCESS

Patent #:	9722053	Issue Dt:	08/01/2017	Application #:	15075557	Filing Dt:	03/21/2016
Title:	METHODS, APPARATUS AND SYSTEM FOR LOCAL ISOLATION FORMATION FOR FINFET DEVICES

Patent #:	9793113	Issue Dt:	10/17/2017	Application #:	15075668	Filing Dt:	03/21/2016
Publication #:	US20170271146	Pub Dt:	09/21/2017
Title:	SEMICONDUCTOR STRUCTURE HAVING INSULATOR PILLARS AND SEMICONDUCTOR MATERIAL ON SUBSTRATE

Patent #:	9716138	Issue Dt:	07/25/2017	Application #:	15075890	Filing Dt:	03/21/2016
Title:	DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS

Patent #:	9570552	Issue Dt:	02/14/2017	Application #:	15076842	Filing Dt:	03/22/2016
Title:	FORMING SYMMETRICAL STRESS LINERS FOR STRAINED CMOS VERTICAL NANOWIRE FIELD-EFFECT TRANSISTORS

Patent #:	9564521	Issue Dt:	02/07/2017	Application #:	15076850	Filing Dt:	03/22/2016
Publication #:	US20160204219	Pub Dt:	07/14/2016
Title:	SEMICONDUCTOR DEVICE COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS

Patent #:	9437269	Issue Dt:	09/06/2016	Application #:	15076992	Filing Dt:	03/22/2016
Publication #:	US20160203851	Pub Dt:	07/14/2016
Title:	ANTIFERROMAGNETIC STORAGE DEVICE

Patent #:	9818623	Issue Dt:	11/14/2017	Application #:	15077480	Filing Dt:	03/22/2016
Publication #:	US20170278720	Pub Dt:	09/28/2017
Title:	METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES AND ASSOCIATED CONTINUITY BLOCKS IN AN INTEGRATED CIRCUIT

Patent #:	9747401	Issue Dt:	08/29/2017	Application #:	15078032	Filing Dt:	03/23/2016
Publication #:	US20160314234	Pub Dt:	10/27/2016
Title:	METHODS FOR MODIFYING AN INTEGRATED CIRCUIT LAYOUT DESIGN

100

Patent #:	9966431	Issue Dt:	05/08/2018	Application #:	15078112	Filing Dt:	03/23/2016
Publication #:	US20170278927	Pub Dt:	09/28/2017
Title:	Nanowire-Based Vertical Memory Cell Array having a Back Plate and Nanowire Seeds Contacting a Bit Line

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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