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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 67 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
Issue Dt:
07/03/2018
Application #:
15170134
Filing Dt:
06/01/2016
Publication #:
Pub Dt:
03/30/2017
Title:
FIELD EFFECT TRANSISTOR DEVICE SPACERS
2
Patent #:
Issue Dt:
10/17/2017
Application #:
15170224
Filing Dt:
06/01/2016
Title:
DEEP TRENCH CAPACITOR WITH METAL PLATE
3
Patent #:
Issue Dt:
02/13/2018
Application #:
15171314
Filing Dt:
06/02/2016
Publication #:
Pub Dt:
12/07/2017
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
4
Patent #:
Issue Dt:
03/27/2018
Application #:
15171320
Filing Dt:
06/02/2016
Publication #:
Pub Dt:
12/07/2017
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
5
Patent #:
Issue Dt:
05/02/2017
Application #:
15171795
Filing Dt:
06/02/2016
Title:
METHODS OF FORMING REPLACEMENT GATE STRUCTURES AND BOTTOM AND TOP SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE
6
Patent #:
Issue Dt:
04/04/2017
Application #:
15172201
Filing Dt:
06/03/2016
Publication #:
Pub Dt:
03/02/2017
Title:
FIN LINER INTEGRATION UNDER AGGRESSIVE PITCH
7
Patent #:
Issue Dt:
12/27/2016
Application #:
15172366
Filing Dt:
06/03/2016
Publication #:
Pub Dt:
09/29/2016
Title:
METHOD AND STRUCTURE TO SUPPRESS FINFET HEATING
8
Patent #:
Issue Dt:
10/02/2018
Application #:
15172551
Filing Dt:
06/03/2016
Publication #:
Pub Dt:
12/07/2017
Title:
INTERCONNECT STRUCTURE WITH CAPACITOR ELEMENT AND RELATED METHODS
9
Patent #:
Issue Dt:
12/05/2017
Application #:
15173756
Filing Dt:
06/06/2016
Publication #:
Pub Dt:
12/07/2017
Title:
SEMICONDUCTOR LAYOUT GENERATION
10
Patent #:
Issue Dt:
10/03/2017
Application #:
15173766
Filing Dt:
06/06/2016
Title:
THRESHOLD VOLTAGE AND WELL IMPLANTATION METHOD FOR SEMICONDUCTOR DEVICES
11
Patent #:
Issue Dt:
01/02/2018
Application #:
15174147
Filing Dt:
07/22/2016
Publication #:
Pub Dt:
01/25/2018
Title:
MULTIPLE STEP THIN FILM DEPOSITION METHOD FOR HIGH CONFORMALITY
12
Patent #:
Issue Dt:
06/26/2018
Application #:
15174273
Filing Dt:
06/06/2016
Publication #:
Pub Dt:
12/07/2017
Title:
SEMICONDUCTOR DEVICES
13
Patent #:
Issue Dt:
12/04/2018
Application #:
15175101
Filing Dt:
06/07/2016
Publication #:
Pub Dt:
12/07/2017
Title:
SEMICONDUCTOR WAFER INSPECTION USING CARE AREA GROUP-SPECIFIC THRESHOLD SETTINGS FOR DETECTING DEFECTS
14
Patent #:
Issue Dt:
10/17/2017
Application #:
15175187
Filing Dt:
06/07/2016
Title:
METHODS FOR FORMING MASK LAYERS USING A FLOWABLE CARBON-CONTAINING SILICON DIOXIDE MATERIAL
15
Patent #:
Issue Dt:
02/13/2018
Application #:
15175290
Filing Dt:
06/07/2016
Publication #:
Pub Dt:
12/07/2017
Title:
PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED DEVICE
16
Patent #:
Issue Dt:
08/22/2017
Application #:
15175308
Filing Dt:
06/07/2016
Title:
METHOD FOR PRODUCING SELF-ALIGNED LINE END VIAS AND RELATED DEVICE
17
Patent #:
Issue Dt:
11/07/2017
Application #:
15175495
Filing Dt:
06/07/2016
Title:
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES WITH MULTIPLE POWER RAILS AND REDUNDANCY
18
Patent #:
Issue Dt:
05/02/2017
Application #:
15175540
Filing Dt:
06/07/2016
Publication #:
Pub Dt:
12/01/2016
Title:
METHOD FOR FORMING SOURCE/DRAIN CONTACTS DURING CMOS INTEGRATION USING CONFINED EPITAXIAL GROWTH TECHNIQUES AND THE RESULTING SEMICONDUCTOR DEVICES
19
Patent #:
Issue Dt:
10/24/2017
Application #:
15175573
Filing Dt:
06/07/2016
Title:
COBALT INTERCONNECTS COVERED BY A METAL CAP
20
Patent #:
Issue Dt:
07/25/2017
Application #:
15175578
Filing Dt:
06/07/2016
Title:
LATENCY COMPENSATION NETWORK USING TIMING SLACK SENSORS
21
Patent #:
Issue Dt:
09/18/2018
Application #:
15175767
Filing Dt:
06/07/2016
Publication #:
Pub Dt:
12/07/2017
Title:
SECURE HYPER TRANSFER OF LARGE FILES
22
Patent #:
Issue Dt:
08/15/2017
Application #:
15175776
Filing Dt:
06/07/2016
Publication #:
Pub Dt:
02/16/2017
Title:
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
23
Patent #:
Issue Dt:
04/18/2017
Application #:
15175835
Filing Dt:
06/07/2016
Publication #:
Pub Dt:
02/16/2017
Title:
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
24
Patent #:
Issue Dt:
06/26/2018
Application #:
15176296
Filing Dt:
06/08/2016
Publication #:
Pub Dt:
03/23/2017
Title:
METHOD INCLUDING AN ADJUSTMENT OF A PLURALITY OF WAFER HANDLING ELEMENTS, SYSTEM INCLUDING A PLURALITY OF WAFER HANDLING ELEMENTS AND PHOTOLITHOGRAPHY TRACK
25
Patent #:
Issue Dt:
12/12/2017
Application #:
15176595
Filing Dt:
06/08/2016
Publication #:
Pub Dt:
12/14/2017
Title:
TILED-STRESS-ALLEVIATING PAD STRUCTURE
26
Patent #:
Issue Dt:
08/01/2017
Application #:
15178134
Filing Dt:
06/09/2016
Title:
FORMATION OF SEMICONDUCTOR STRUCTURES EMPLOYING SELECTIVE REMOVAL OF FINS
27
Patent #:
Issue Dt:
01/01/2019
Application #:
15178871
Filing Dt:
06/10/2016
Publication #:
Pub Dt:
12/14/2017
Title:
SELF-ALIGNED FINFET FORMATION
28
Patent #:
Issue Dt:
04/25/2017
Application #:
15179393
Filing Dt:
06/10/2016
Publication #:
Pub Dt:
03/23/2017
Title:
POC PROCESS FLOW FOR CONFORMAL RECESS FILL
29
Patent #:
Issue Dt:
10/17/2017
Application #:
15179620
Filing Dt:
06/10/2016
Publication #:
Pub Dt:
09/29/2016
Title:
BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
30
Patent #:
Issue Dt:
08/22/2017
Application #:
15179992
Filing Dt:
06/11/2016
Publication #:
Pub Dt:
06/08/2017
Title:
STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
31
Patent #:
Issue Dt:
12/12/2017
Application #:
15180422
Filing Dt:
06/13/2016
Publication #:
Pub Dt:
12/14/2017
Title:
FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES
32
Patent #:
Issue Dt:
04/25/2017
Application #:
15181992
Filing Dt:
06/14/2016
Publication #:
Pub Dt:
03/09/2017
Title:
FORMING RELIABLE CONTACTS ON TIGHT SEMICONDUCTOR PITCH
33
Patent #:
Issue Dt:
09/12/2017
Application #:
15182068
Filing Dt:
06/14/2016
Title:
SEMICONDUCTOR STRUCTURE WITH BACK-GATE SWITCHING
34
Patent #:
Issue Dt:
06/26/2018
Application #:
15182794
Filing Dt:
06/15/2016
Publication #:
Pub Dt:
12/21/2017
Title:
DEVICES AND METHODS OF FORMING ASYMMETRIC LINE/SPACE WITH BARRIERLESS METALLIZATION
35
Patent #:
Issue Dt:
01/23/2018
Application #:
15183390
Filing Dt:
06/15/2016
Publication #:
Pub Dt:
01/26/2017
Title:
HIGH-K AND P-TYPE WORK FUNCTION METAL FIRST FABRICATION PROCESS HAVING IMPROVED ANNEALING PROCESS FLOWS
36
Patent #:
Issue Dt:
10/09/2018
Application #:
15184164
Filing Dt:
06/16/2016
Publication #:
Pub Dt:
12/21/2017
Title:
FEED-FORWARD FOR SILICON INSPECTIONS (DFM2CFM : DESIGN TO SILICON) & FEED-BACK FOR WEAKPOINT PREDICTOR DECKS (CFM2DFM : SILICON TO DESIGN) GUIDED BY MARKER CLASSIFICATION, SAMPLING, AND HIGHER DIMENSIONAL ANALYSIS
37
Patent #:
Issue Dt:
06/27/2017
Application #:
15185185
Filing Dt:
06/17/2016
Title:
PEDESTAL ALIGNMENT TOOL FOR AN ORIENTER PEDESTAL OF AN ION IMPLANT DEVICE
38
Patent #:
Issue Dt:
04/25/2017
Application #:
15185267
Filing Dt:
06/17/2016
Title:
JUNCTION FORMATION WITH REDUCED Ceff FOR 22NM FDSOI DEVICES
39
Patent #:
Issue Dt:
03/20/2018
Application #:
15185593
Filing Dt:
06/17/2016
Publication #:
Pub Dt:
12/21/2017
Title:
GATE PATTERNING FOR AC AND DC PERFORMANCE BOOST
40
Patent #:
Issue Dt:
02/27/2018
Application #:
15185801
Filing Dt:
06/17/2016
Publication #:
Pub Dt:
10/06/2016
Title:
SEMICONDUCTOR STRUCTURE HAVING SOURCE/DRAIN GOUGING IMMUNITY
41
Patent #:
Issue Dt:
03/27/2018
Application #:
15187048
Filing Dt:
06/20/2016
Publication #:
Pub Dt:
12/21/2017
Title:
ELECTRICAL AND OPTICAL VIA CONNECTIONS ON A SAME CHIP
42
Patent #:
Issue Dt:
05/08/2018
Application #:
15187126
Filing Dt:
06/20/2016
Publication #:
Pub Dt:
12/21/2017
Title:
MASK SUBSTRATE STRUCTURE
43
Patent #:
Issue Dt:
12/19/2017
Application #:
15187860
Filing Dt:
06/21/2016
Publication #:
Pub Dt:
12/21/2017
Title:
FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS
44
Patent #:
Issue Dt:
05/08/2018
Application #:
15188419
Filing Dt:
06/21/2016
Publication #:
Pub Dt:
10/13/2016
Title:
III-V LASERS WITH INTEGRATED SILICON PHOTONIC CIRCUITS
45
Patent #:
Issue Dt:
12/26/2017
Application #:
15189432
Filing Dt:
06/22/2016
Publication #:
Pub Dt:
12/28/2017
Title:
ANTI-FUSES WITH REDUCED PROGRAMMING VOLTAGES
46
Patent #:
Issue Dt:
05/08/2018
Application #:
15190323
Filing Dt:
06/23/2016
Publication #:
Pub Dt:
12/28/2017
Title:
METHODS FOR CROSSED-FINS FINFET DEVICE FOR SENSING AND MEASURING MAGNETIC FIELDS
47
Patent #:
Issue Dt:
05/02/2017
Application #:
15190365
Filing Dt:
06/23/2016
Publication #:
Pub Dt:
11/17/2016
Title:
CARBON NANOTUBE DEVICE
48
Patent #:
Issue Dt:
11/21/2017
Application #:
15193300
Filing Dt:
06/27/2016
Title:
METHODS THAT USE AT LEAST A DUAL DAMASCENE PROCESS AND, OPTIONALLY, A SINGLE DAMASCENE PROCESS TO FORM INTERCONNECTS WITH HYBRID METALLIZATION AND THE RESULTING STRUCTURES
49
Patent #:
Issue Dt:
03/06/2018
Application #:
15193502
Filing Dt:
06/27/2016
Publication #:
Pub Dt:
12/28/2017
Title:
SELF-CONTAINED METROLOGY WAFER CARRIER SYSTEMS
50
Patent #:
Issue Dt:
03/28/2017
Application #:
15193770
Filing Dt:
06/27/2016
Publication #:
Pub Dt:
10/20/2016
Title:
INTEGRATED CIRCUIT PRODUCT WITH BULK AND SOI SEMICONDUCTOR DEVICES
51
Patent #:
Issue Dt:
07/18/2017
Application #:
15193867
Filing Dt:
06/27/2016
Title:
VERTICAL CHANNEL TRANSISTOR-BASED SEMICONDUCTOR MEMORY STRUCTURE
52
Patent #:
Issue Dt:
04/30/2019
Application #:
15194682
Filing Dt:
06/28/2016
Publication #:
Pub Dt:
12/28/2017
Title:
METHOD OF FORMING A GATE CONTACT STRUCTURE AND SOURCE/DRAIN CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE
53
Patent #:
Issue Dt:
05/05/2020
Application #:
15196335
Filing Dt:
06/29/2016
Publication #:
Pub Dt:
01/04/2018
Title:
SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY
54
Patent #:
Issue Dt:
12/18/2018
Application #:
15196371
Filing Dt:
06/29/2016
Publication #:
Pub Dt:
01/04/2018
Title:
SEMICONDUCTOR CONTACT
55
Patent #:
Issue Dt:
07/17/2018
Application #:
15196915
Filing Dt:
06/29/2016
Publication #:
Pub Dt:
01/04/2018
Title:
DIAGNOSING FAILURE LOCATIONS OF AN INTEGRATED CIRCUIT WITH LOGIC BUILT-IN SELF-TEST
56
Patent #:
Issue Dt:
11/21/2017
Application #:
15196920
Filing Dt:
06/29/2016
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR WITH STRESS COMPONENT
57
Patent #:
Issue Dt:
01/30/2018
Application #:
15197892
Filing Dt:
06/30/2016
Publication #:
Pub Dt:
01/04/2018
Title:
FORMING DEFECT-FREE RELAXED SIGE FINS
58
Patent #:
Issue Dt:
01/23/2018
Application #:
15197944
Filing Dt:
06/30/2016
Publication #:
Pub Dt:
01/04/2018
Title:
METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC PRODUCTS COMPRISING FINFET DEVICES
59
Patent #:
Issue Dt:
07/31/2018
Application #:
15198038
Filing Dt:
06/30/2016
Publication #:
Pub Dt:
11/02/2017
Title:
SEMICONDUCTOR DEVICE AND METHOD
60
Patent #:
Issue Dt:
02/06/2018
Application #:
15198044
Filing Dt:
06/30/2016
Publication #:
Pub Dt:
01/04/2018
Title:
INTERCONNECTS FOR VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS
61
Patent #:
Issue Dt:
03/27/2018
Application #:
15198309
Filing Dt:
06/30/2016
Publication #:
Pub Dt:
01/04/2018
Title:
VERTICAL TRANSISTORS AND METHODS OF FORMING SAME
62
Patent #:
Issue Dt:
11/24/2020
Application #:
15200475
Filing Dt:
07/01/2016
Publication #:
Pub Dt:
01/04/2018
Title:
METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING
63
Patent #:
Issue Dt:
03/19/2019
Application #:
15200716
Filing Dt:
07/01/2016
Publication #:
Pub Dt:
05/04/2017
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
64
Patent #:
Issue Dt:
05/08/2018
Application #:
15201771
Filing Dt:
07/05/2016
Publication #:
Pub Dt:
01/11/2018
Title:
ADVANCED PROCESS CONTROL METHODS FOR PROCESS-AWARE DIMENSION TARGETING
65
Patent #:
Issue Dt:
04/10/2018
Application #:
15202764
Filing Dt:
07/06/2016
Publication #:
Pub Dt:
01/11/2018
Title:
METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE REGION OF A SEMICONDUCTOR
66
Patent #:
Issue Dt:
11/21/2017
Application #:
15202817
Filing Dt:
07/06/2016
Title:
METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE A SEMICONDUCTOR ACTIVE REGION HAVING HIGH-K DIELECTRIC GATE CAPS
67
Patent #:
Issue Dt:
05/08/2018
Application #:
15202983
Filing Dt:
07/06/2016
Publication #:
Pub Dt:
03/23/2017
Title:
STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)
68
Patent #:
Issue Dt:
11/14/2017
Application #:
15202994
Filing Dt:
07/06/2016
Publication #:
Pub Dt:
03/23/2017
Title:
STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)
69
Patent #:
Issue Dt:
09/19/2017
Application #:
15203084
Filing Dt:
07/06/2016
Title:
INTERCONNECT STRUCTURES WITH VARIABLE DOPANT LEVELS
70
Patent #:
Issue Dt:
11/28/2017
Application #:
15203326
Filing Dt:
07/06/2016
Title:
EDGE COMPRESSION LAYERS
71
Patent #:
Issue Dt:
10/10/2017
Application #:
15204259
Filing Dt:
07/07/2016
Title:
VERTICAL-TRANSPORT FINFET DEVICE WITH VARIABLE FIN PITCH
72
Patent #:
Issue Dt:
04/24/2018
Application #:
15204473
Filing Dt:
07/07/2016
Publication #:
Pub Dt:
01/11/2018
Title:
STATIC RANDOM ACCESS MEMORY (SRAM) ASSIST CIRCUIT
73
Patent #:
Issue Dt:
01/02/2018
Application #:
15205496
Filing Dt:
07/08/2016
Publication #:
Pub Dt:
01/11/2018
Title:
THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
74
Patent #:
Issue Dt:
09/12/2017
Application #:
15205528
Filing Dt:
07/08/2016
Title:
DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC
75
Patent #:
Issue Dt:
09/05/2017
Application #:
15205535
Filing Dt:
07/08/2016
Title:
HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION
76
Patent #:
Issue Dt:
11/13/2018
Application #:
15206361
Filing Dt:
07/11/2016
Publication #:
Pub Dt:
01/11/2018
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING GATE CONTACT AND METHOD OF FORMING SAME
77
Patent #:
Issue Dt:
05/08/2018
Application #:
15207524
Filing Dt:
07/12/2016
Publication #:
Pub Dt:
01/18/2018
Title:
CENTERING FIXTURE FOR ELECTROSTATIC CHUCK SYSTEM
78
Patent #:
Issue Dt:
12/26/2017
Application #:
15207652
Filing Dt:
07/12/2016
Publication #:
Pub Dt:
11/03/2016
Title:
CUT FIRST ALTERNATIVE FOR 2D SELF-ALIGNED VIA
79
Patent #:
Issue Dt:
05/09/2017
Application #:
15208121
Filing Dt:
07/12/2016
Publication #:
Pub Dt:
12/15/2016
Title:
SPACER CHAMFERING GATE STACK SCHEME
80
Patent #:
Issue Dt:
03/06/2018
Application #:
15208495
Filing Dt:
07/12/2016
Publication #:
Pub Dt:
01/18/2018
Title:
METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES
81
Patent #:
Issue Dt:
01/16/2018
Application #:
15210403
Filing Dt:
07/14/2016
Publication #:
Pub Dt:
01/18/2018
Title:
THROUGH SILICON VIA SHARING IN A 3D INTEGRATED CIRCUIT
82
Patent #:
Issue Dt:
10/03/2017
Application #:
15212755
Filing Dt:
07/18/2016
Title:
METHOD AND STRUCTURE OF FORMING SELF-ALIGNED RMG GATE FOR VFET
83
Patent #:
Issue Dt:
10/23/2018
Application #:
15213665
Filing Dt:
07/19/2016
Publication #:
Pub Dt:
01/25/2018
Title:
METHODS OF DETECTING FAULTS IN REAL-TIME FOR SEMICONDUCTOR WAFERS
84
Patent #:
Issue Dt:
12/10/2019
Application #:
15214585
Filing Dt:
07/20/2016
Publication #:
Pub Dt:
01/25/2018
Title:
LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES
85
Patent #:
Issue Dt:
06/13/2017
Application #:
15214854
Filing Dt:
07/20/2016
Title:
FIN-TYPE FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS
86
Patent #:
Issue Dt:
05/16/2017
Application #:
15215043
Filing Dt:
07/20/2016
Title:
METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS
87
Patent #:
Issue Dt:
10/24/2017
Application #:
15215674
Filing Dt:
07/21/2016
Publication #:
Pub Dt:
11/24/2016
Title:
PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS
88
Patent #:
Issue Dt:
08/21/2018
Application #:
15217643
Filing Dt:
07/22/2016
Publication #:
Pub Dt:
01/25/2018
Title:
SEMICONDUCTOR WAFERS WITH REDUCED BOW AND WARPAGE
89
Patent #:
Issue Dt:
01/22/2019
Application #:
15218241
Filing Dt:
07/25/2016
Publication #:
Pub Dt:
01/25/2018
Title:
SYSTEMS AND METHODS FOR SENSING PROCESS PARAMETERS DURING SEMICONDUCTOR DEVICE FABRICATION
90
Patent #:
Issue Dt:
07/11/2017
Application #:
15218318
Filing Dt:
07/25/2016
Title:
FIN-BASED RF DIODES
91
Patent #:
Issue Dt:
08/28/2018
Application #:
15219370
Filing Dt:
07/26/2016
Publication #:
Pub Dt:
02/01/2018
Title:
PREVENTING BRIDGE FORMATION BETWEEN REPLACEMENT GATE AND SOURCE/DRAIN REGION THROUGH STI STRUCTURE
92
Patent #:
Issue Dt:
08/01/2017
Application #:
15219378
Filing Dt:
07/26/2016
Title:
MIDDLE OF THE LINE (MOL) METAL CONTACTS
93
Patent #:
Issue Dt:
07/03/2018
Application #:
15219403
Filing Dt:
07/26/2016
Publication #:
Pub Dt:
02/01/2018
Title:
METHODS OF FORMING IC PRODUCTS COMPRISING A NANO-SHEET DEVICE AND A TRANSISTOR DEVICE HAVING FIRST AND SECOND REPLACEMENT GATE STRUCTURES
94
Patent #:
Issue Dt:
12/19/2017
Application #:
15219917
Filing Dt:
07/26/2016
Title:
METHODS OF FORMING FIN CUT REGIONS BY OXIDIZING FIN PORTIONS
95
Patent #:
Issue Dt:
08/22/2017
Application #:
15219967
Filing Dt:
07/26/2016
Title:
HIGHER 'K' GATE DIELECTRIC CAP FOR REPLACEMENT METAL GATE (RMG) FINFET DEVICES
96
Patent #:
Issue Dt:
06/12/2018
Application #:
15220764
Filing Dt:
07/27/2016
Publication #:
Pub Dt:
02/01/2018
Title:
INTERCONNECT STRUCTURE HAVING POWER RAIL STRUCTURE AND RELATED METHOD
97
Patent #:
Issue Dt:
09/18/2018
Application #:
15221647
Filing Dt:
07/28/2016
Publication #:
Pub Dt:
02/01/2018
Title:
IC STRUCTURE WITH INTERFACE LINER AND METHODS OF FORMING SAME
98
Patent #:
Issue Dt:
02/20/2018
Application #:
15222096
Filing Dt:
07/28/2016
Publication #:
Pub Dt:
02/01/2018
Title:
STRUCTURE AND METHOD TO MEASURE FOCUS-DEPENDENT PATTERN SHIFT IN INTEGRATED CIRCUIT IMAGING
99
Patent #:
Issue Dt:
03/17/2020
Application #:
15222261
Filing Dt:
07/28/2016
Publication #:
Pub Dt:
04/13/2017
Title:
FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS
100
Patent #:
Issue Dt:
03/17/2020
Application #:
15223882
Filing Dt:
07/29/2016
Publication #:
Pub Dt:
11/17/2016
Title:
SYSTEM AND METHOD FOR MONITORING WAFER HANDLING AND A WAFER HANDLING MACHINE
Assignor
1
Exec Dt:
10/22/2020
Assignee
1
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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