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Patent Assignment Details
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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 69 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
9812365
Issue Dt:
11/07/2017
Application #:
15286117
Filing Dt:
10/05/2016
Title:
METHODS OF CUTTING GATE STRUCTURES ON TRANSISTOR DEVICES
2
Patent #:
10096595
Issue Dt:
10/09/2018
Application #:
15286196
Filing Dt:
10/05/2016
Publication #:
US20170125403
Pub Dt:
05/04/2017
Title:
ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES
3
Patent #:
9793395
Issue Dt:
10/17/2017
Application #:
15287134
Filing Dt:
10/06/2016
Title:
VERTICAL VACUUM CHANNEL TRANSISTOR
4
Patent #:
10062612
Issue Dt:
08/28/2018
Application #:
15288503
Filing Dt:
10/07/2016
Publication #:
US20180102291
Pub Dt:
04/12/2018
Title:
METHOD AND SYSTEM FOR CONSTRUCTING FINFET DEVICES HAVING A SUPER STEEP RETROGRADE WELL
5
Patent #:
9812368
Issue Dt:
11/07/2017
Application #:
15289158
Filing Dt:
10/08/2016
Publication #:
US20170162451
Pub Dt:
06/08/2017
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
6
Patent #:
9825044
Issue Dt:
11/21/2017
Application #:
15289161
Filing Dt:
10/08/2016
Publication #:
US20170162584
Pub Dt:
06/08/2017
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
7
Patent #:
10147714
Issue Dt:
12/04/2018
Application #:
15289401
Filing Dt:
10/10/2016
Publication #:
US20180102354
Pub Dt:
04/12/2018
Title:
METHOD, APPARATUS, AND SYSTEM FOR TWO-DIMENSIONAL POWER RAIL TO ENABLE SCALING OF A STANDARD CELL
8
Patent #:
9711447
Issue Dt:
07/18/2017
Application #:
15290277
Filing Dt:
10/11/2016
Title:
SELF-ALIGNED LITHOGRAPHIC PATTERNING WITH VARIABLE SPACINGS
9
Patent #:
9911619
Issue Dt:
03/06/2018
Application #:
15291446
Filing Dt:
10/12/2016
Title:
FIN CUT WITH ALTERNATING TWO COLOR FIN HARDMASK
10
Patent #:
10211090
Issue Dt:
02/19/2019
Application #:
15291561
Filing Dt:
10/12/2016
Publication #:
US20180102422
Pub Dt:
04/12/2018
Title:
TRANSISTOR WITH AN AIRGAP FOR REDUCED BASE-EMITTER CAPACITANCE AND METHOD OF FORMING THE TRANSISTOR
11
Patent #:
9911657
Issue Dt:
03/06/2018
Application #:
15291750
Filing Dt:
10/12/2016
Publication #:
US20170154821
Pub Dt:
06/01/2017
Title:
SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR
12
Patent #:
9960207
Issue Dt:
05/01/2018
Application #:
15292445
Filing Dt:
10/13/2016
Publication #:
US20180108706
Pub Dt:
04/19/2018
Title:
SPIN-SELECTIVE ELECTRON RELAY
13
Patent #:
10083958
Issue Dt:
09/25/2018
Application #:
15292488
Filing Dt:
10/13/2016
Publication #:
US20180108651
Pub Dt:
04/19/2018
Title:
DEEP TRENCH METAL-INSULATOR-METAL CAPACITORS
14
Patent #:
9947590
Issue Dt:
04/17/2018
Application #:
15294228
Filing Dt:
10/14/2016
Publication #:
US20180108571
Pub Dt:
04/19/2018
Title:
METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING METAL LINE JUMPING OVER MOL FEATURES IN A STANDARD CELL
15
Patent #:
9893718
Issue Dt:
02/13/2018
Application #:
15295299
Filing Dt:
10/17/2016
Title:
TRANSMISSION DRIVER IMPEDANCE CALIBRATION CIRCUIT
16
Patent #:
9947789
Issue Dt:
04/17/2018
Application #:
15295338
Filing Dt:
10/17/2016
Publication #:
US20180108776
Pub Dt:
04/19/2018
Title:
VERTICAL TRANSISTORS STRESSED FROM VARIOUS DIRECTIONS
17
Patent #:
10002965
Issue Dt:
06/19/2018
Application #:
15298648
Filing Dt:
10/20/2016
Publication #:
US20170125578
Pub Dt:
05/04/2017
Title:
FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING
18
Patent #:
10718806
Issue Dt:
07/21/2020
Application #:
15299824
Filing Dt:
10/21/2016
Publication #:
US20180113166
Pub Dt:
04/26/2018
Title:
HIGH SPEED AND HIGH PRECISION CHARACTERIZATION OF VTSAT AND VTLIN OF FET ARRAYS
19
Patent #:
10957588
Issue Dt:
03/23/2021
Application #:
15333874
Filing Dt:
10/25/2016
Publication #:
US20170062331
Pub Dt:
03/02/2017
Title:
CHAMFERLESS VIA STRUCTURES
20
Patent #:
10468310
Issue Dt:
11/05/2019
Application #:
15334964
Filing Dt:
10/26/2016
Publication #:
US20180114730
Pub Dt:
04/26/2018
Title:
SPACER INTEGRATION SCHEME FOR NFET AND PFET DEVICES
21
Patent #:
RE47630
Issue Dt:
10/01/2019
Application #:
15335313
Filing Dt:
10/26/2016
Title:
SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM
22
Patent #:
10056408
Issue Dt:
08/21/2018
Application #:
15335549
Filing Dt:
10/27/2016
Publication #:
US20170047350
Pub Dt:
02/16/2017
Title:
STRUCTURE AND METHOD TO FORM A FINFET DEVICE
23
Patent #:
9679805
Issue Dt:
06/13/2017
Application #:
15336589
Filing Dt:
10/27/2016
Publication #:
US20170047247
Pub Dt:
02/16/2017
Title:
SELF-ALIGNED BACK END OF LINE CUT
24
Patent #:
9905707
Issue Dt:
02/27/2018
Application #:
15337026
Filing Dt:
10/28/2016
Title:
MOS CAPACITIVE STRUCTURE OF REDUCED CAPACITANCE VARIABILITY
25
Patent #:
10177241
Issue Dt:
01/08/2019
Application #:
15337254
Filing Dt:
10/28/2016
Publication #:
US20180122919
Pub Dt:
05/03/2018
Title:
METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE THE ACTIVE REGION AND AN AIR GAP ADJACENT THE GATE OF THE TRANSISTOR
26
Patent #:
9972721
Issue Dt:
05/15/2018
Application #:
15337368
Filing Dt:
10/28/2016
Publication #:
US20180122956
Pub Dt:
05/03/2018
Title:
THICK FDSOI SOURCE-DRAIN IMPROVEMENT
27
Patent #:
9842845
Issue Dt:
12/12/2017
Application #:
15337441
Filing Dt:
10/28/2016
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE
28
Patent #:
9831124
Issue Dt:
11/28/2017
Application #:
15338070
Filing Dt:
10/28/2016
Title:
INTERCONNECT STRUCTURES
29
Patent #:
10181468
Issue Dt:
01/15/2019
Application #:
15338512
Filing Dt:
10/31/2016
Publication #:
US20180122795
Pub Dt:
05/03/2018
Title:
MEMORY CELL WITH ASYMMETRICAL TRANSISTOR, ASYMMETRICAL TRANSISTOR AND METHOD OF FORMING
30
Patent #:
10439031
Issue Dt:
10/08/2019
Application #:
15338925
Filing Dt:
10/31/2016
Publication #:
US20180122913
Pub Dt:
05/03/2018
Title:
INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND ELECTRICAL FUSES
31
Patent #:
10446399
Issue Dt:
10/15/2019
Application #:
15339497
Filing Dt:
10/31/2016
Publication #:
US20180122644
Pub Dt:
05/03/2018
Title:
HARD MASK LAYER TO REDUCE LOSS OF ISOLATION MATERIAL DURING DUMMY GATE REMOVAL
32
Patent #:
NONE
Issue Dt:
Application #:
15340491
Filing Dt:
11/01/2016
Publication #:
US20170053982
Pub Dt:
02/23/2017
Title:
SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS
33
Patent #:
9806078
Issue Dt:
10/31/2017
Application #:
15341240
Filing Dt:
11/02/2016
Title:
FINFET SPACER FORMATION ON GATE SIDEWALLS, BETWEEN THE CHANNEL AND SOURCE/DRAIN REGIONS
34
Patent #:
9853117
Issue Dt:
12/26/2017
Application #:
15342396
Filing Dt:
11/03/2016
Publication #:
US20170077099
Pub Dt:
03/16/2017
Title:
SPACER CHAMFERING GATE STACK SCHEME
35
Patent #:
9793157
Issue Dt:
10/17/2017
Application #:
15342440
Filing Dt:
11/03/2016
Publication #:
US20170125284
Pub Dt:
05/04/2017
Title:
ETCH STOP FOR AIRGAP PROTECTION
36
Patent #:
9876010
Issue Dt:
01/23/2018
Application #:
15342464
Filing Dt:
11/03/2016
Title:
RESISTOR DISPOSED DIRECTLY UPON A SAC CAP OF A GATE STRUCTURE OF A SEMICONDUCTOR STRUCTURE
37
Patent #:
9773781
Issue Dt:
09/26/2017
Application #:
15342498
Filing Dt:
11/03/2016
Title:
RESISTOR AND CAPACITOR DISPOSED DIRECTLY UPON A SAC CAP OF A GATE STRUCTURE OF A SEMICONDUCTOR STRUCTURE
38
Patent #:
9842741
Issue Dt:
12/12/2017
Application #:
15342794
Filing Dt:
11/03/2016
Publication #:
US20170076954
Pub Dt:
03/16/2017
Title:
REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS
39
Patent #:
9929057
Issue Dt:
03/27/2018
Application #:
15342801
Filing Dt:
11/03/2016
Publication #:
US20170076987
Pub Dt:
03/16/2017
Title:
HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
40
Patent #:
10164104
Issue Dt:
12/25/2018
Application #:
15343590
Filing Dt:
11/04/2016
Publication #:
US20180130899
Pub Dt:
05/10/2018
Title:
METHOD TO FORM AIR-GAP SPACERS AND AIR-GAP SPACER-CONTAINING STRUCTURES
41
Patent #:
10115807
Issue Dt:
10/30/2018
Application #:
15343821
Filing Dt:
11/04/2016
Publication #:
US20170141214
Pub Dt:
05/18/2017
Title:
METHOD, APPARATUS AND SYSTEM FOR IMPROVED PERFORMANCE USING TALL FINS IN FINFET DEVICES
42
Patent #:
9847347
Issue Dt:
12/19/2017
Application #:
15344856
Filing Dt:
11/07/2016
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AT A SEMICONDUCTOR-ON-INSULATOR REGION AND A SECOND TRANSISTOR AT A BULK REGION AND METHOD FOR THE FORMATION THEREOF
43
Patent #:
9978836
Issue Dt:
05/22/2018
Application #:
15344862
Filing Dt:
11/07/2016
Publication #:
US20180130878
Pub Dt:
05/10/2018
Title:
NANOSTRUCTURE FIELD-EFFECT TRANSISTORS WITH ENHANCED MOBILITY SOURCE/DRAIN REGIONS
44
Patent #:
10002932
Issue Dt:
06/19/2018
Application #:
15345137
Filing Dt:
11/07/2016
Publication #:
US20180130889
Pub Dt:
05/10/2018
Title:
SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS
45
Patent #:
10256204
Issue Dt:
04/09/2019
Application #:
15345608
Filing Dt:
11/08/2016
Publication #:
US20180130733
Pub Dt:
05/10/2018
Title:
SEPARATION OF INTEGRATED CIRCUIT STRUCTURE FROM ADJACENT CHIP
46
Patent #:
9984932
Issue Dt:
05/29/2018
Application #:
15345612
Filing Dt:
11/08/2016
Publication #:
US20180130711
Pub Dt:
05/10/2018
Title:
SEMICONDUCTOR FIN LOOP FOR USE WITH DIFFUSION BREAK
47
Patent #:
9966456
Issue Dt:
05/08/2018
Application #:
15345644
Filing Dt:
11/08/2016
Publication #:
US20180130895
Pub Dt:
05/10/2018
Title:
METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE
48
Patent #:
10262892
Issue Dt:
04/16/2019
Application #:
15345882
Filing Dt:
11/08/2016
Publication #:
US20180130699
Pub Dt:
05/10/2018
Title:
SKIP VIA STRUCTURES
49
Patent #:
10043708
Issue Dt:
08/07/2018
Application #:
15347119
Filing Dt:
11/09/2016
Publication #:
US20180130703
Pub Dt:
05/10/2018
Title:
STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS
50
Patent #:
9875936
Issue Dt:
01/23/2018
Application #:
15348109
Filing Dt:
11/10/2016
Title:
SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH
51
Patent #:
9842762
Issue Dt:
12/12/2017
Application #:
15349306
Filing Dt:
11/11/2016
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER HAVING AN SOI CONFIGURATION
52
Patent #:
9818876
Issue Dt:
11/14/2017
Application #:
15349358
Filing Dt:
11/11/2016
Title:
METHOD FOR FABRICATING A FINFET METALLIZATION ARCHITECTURE USING A SELF-ALIGNED CONTACT ETCH
53
Patent #:
9847416
Issue Dt:
12/19/2017
Application #:
15351597
Filing Dt:
11/15/2016
Title:
PERFORMANCE-ENHANCED VERTICAL DEVICE AND METHOD OF FORMING THEREOF
54
Patent #:
9972494
Issue Dt:
05/15/2018
Application #:
15351747
Filing Dt:
11/15/2016
Publication #:
US20180138046
Pub Dt:
05/17/2018
Title:
METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE
55
Patent #:
10446653
Issue Dt:
10/15/2019
Application #:
15351893
Filing Dt:
11/15/2016
Publication #:
US20180138279
Pub Dt:
05/17/2018
Title:
TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA
56
Patent #:
9865473
Issue Dt:
01/09/2018
Application #:
15352139
Filing Dt:
11/15/2016
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING AND ISLANDS
57
Patent #:
9893086
Issue Dt:
02/13/2018
Application #:
15352654
Filing Dt:
11/16/2016
Title:
CONTACT PUNCH THROUGH MITIGATION IN SOI SUBSTRATE
58
Patent #:
9917162
Issue Dt:
03/13/2018
Application #:
15353352
Filing Dt:
11/16/2016
Publication #:
US20170288030
Pub Dt:
10/05/2017
Title:
FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
59
Patent #:
10115738
Issue Dt:
10/30/2018
Application #:
15354205
Filing Dt:
11/17/2016
Publication #:
US20180138203
Pub Dt:
05/17/2018
Title:
SELF-ALIGNED BACK-PLANE AND WELL CONTACTS FOR FULLY DEPLETED SILICON ON INSULATOR DEVICE
60
Patent #:
9941162
Issue Dt:
04/10/2018
Application #:
15354212
Filing Dt:
11/17/2016
Title:
SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS
61
Patent #:
10079248
Issue Dt:
09/18/2018
Application #:
15355231
Filing Dt:
11/18/2016
Publication #:
US20180145088
Pub Dt:
05/24/2018
Title:
FIELD-EFFECT TRANSISTORS WITH A BURIED BODY CONTACT
62
Patent #:
10553353
Issue Dt:
02/04/2020
Application #:
15355584
Filing Dt:
11/18/2016
Publication #:
US20180144857
Pub Dt:
05/24/2018
Title:
Parallel Stacked Inductor for High-Q and High Current Handling and Method of Making the Same
63
Patent #:
10090202
Issue Dt:
10/02/2018
Application #:
15357287
Filing Dt:
11/21/2016
Publication #:
US20170125299
Pub Dt:
05/04/2017
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
64
Patent #:
10056292
Issue Dt:
08/21/2018
Application #:
15359037
Filing Dt:
11/22/2016
Publication #:
US20180144979
Pub Dt:
05/24/2018
Title:
SELF-ALIGNED LITHOGRAPHIC PATTERNING
65
Patent #:
10056291
Issue Dt:
08/21/2018
Application #:
15360255
Filing Dt:
11/23/2016
Publication #:
US20180144976
Pub Dt:
05/24/2018
Title:
POST SPACER SELF-ALIGNED CUTS
66
Patent #:
10153361
Issue Dt:
12/11/2018
Application #:
15360295
Filing Dt:
11/23/2016
Publication #:
US20180145160
Pub Dt:
05/24/2018
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE INTEGRATION SCHEMES ON A SAME WAFER
67
Patent #:
9825032
Issue Dt:
11/21/2017
Application #:
15360537
Filing Dt:
11/23/2016
Title:
METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING
68
Patent #:
10008582
Issue Dt:
06/26/2018
Application #:
15361790
Filing Dt:
11/28/2016
Publication #:
US20180151689
Pub Dt:
05/31/2018
Title:
SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
69
Patent #:
10121706
Issue Dt:
11/06/2018
Application #:
15361809
Filing Dt:
11/28/2016
Publication #:
US20180151449
Pub Dt:
05/31/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING TWO-DIMENSIONAL AND THREE-DIMENSIONAL BONDING MATERIALS
70
Patent #:
9935012
Issue Dt:
04/03/2018
Application #:
15361824
Filing Dt:
11/28/2016
Title:
METHODS FOR FORMING DIFFERENT SHAPES IN DIFFERENT REGIONS OF THE SAME LAYER
71
Patent #:
9882024
Issue Dt:
01/30/2018
Application #:
15361994
Filing Dt:
11/28/2016
Publication #:
US20170077266
Pub Dt:
03/16/2017
Title:
EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
72
Patent #:
9852986
Issue Dt:
12/26/2017
Application #:
15362035
Filing Dt:
11/28/2016
Title:
METHOD OF PATTERNING PILLARS TO FORM VARIABLE CONTINUITY CUTS IN INTERCONNECTION LINES OF AN INTEGRATED CIRCUIT
73
Patent #:
9899324
Issue Dt:
02/20/2018
Application #:
15362499
Filing Dt:
11/28/2016
Title:
STRUCTURE AND METHOD OF CONDUCTIVE BUS BAR FOR RESISTIVE SEED SUBSTRATE PLATING
74
Patent #:
9947769
Issue Dt:
04/17/2018
Application #:
15363461
Filing Dt:
11/29/2016
Title:
MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS
75
Patent #:
9922929
Issue Dt:
03/20/2018
Application #:
15363513
Filing Dt:
11/29/2016
Title:
SELF ALIGNED INTERCONNECT STRUCTURES
76
Patent #:
10002940
Issue Dt:
06/19/2018
Application #:
15363563
Filing Dt:
11/29/2016
Publication #:
US20170077259
Pub Dt:
03/16/2017
Title:
SPACER CHAMFERING GATE STACK SCHEME
77
Patent #:
9929020
Issue Dt:
03/27/2018
Application #:
15363596
Filing Dt:
11/29/2016
Publication #:
US20170092507
Pub Dt:
03/30/2017
Title:
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
78
Patent #:
10475660
Issue Dt:
11/12/2019
Application #:
15363607
Filing Dt:
11/29/2016
Publication #:
US20170092721
Pub Dt:
03/30/2017
Title:
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
79
Patent #:
10079242
Issue Dt:
09/18/2018
Application #:
15366425
Filing Dt:
12/01/2016
Publication #:
US20180158835
Pub Dt:
06/07/2018
Title:
LOGIC AND FLASH FIELD-EFFECT TRANSISTORS
80
Patent #:
9805988
Issue Dt:
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Application #:
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Filing Dt:
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Title:
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Pub Dt:
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Title:
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Filing Dt:
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Pub Dt:
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Title:
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Issue Dt:
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Filing Dt:
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Title:
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Issue Dt:
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Pub Dt:
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Title:
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Filing Dt:
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Title:
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Filing Dt:
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Title:
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Title:
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Title:
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Title:
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Filing Dt:
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Title:
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Title:
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Title:
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Title:
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15379645
Filing Dt:
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Title:
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Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
10/22/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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