USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 71 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Patent #:	9991131	Issue Dt:	06/05/2018	Application #:	15443335	Filing Dt:	02/27/2017
Title:	DUAL MANDRELS TO ENABLE VARIABLE FIN PITCH

Patent #:	10062692	Issue Dt:	08/28/2018	Application #:	15443381	Filing Dt:	02/27/2017
Publication #:	US20180247936	Pub Dt:	08/30/2018
Title:	FIELD EFFECT TRANSISTORS WITH REDUCED PARASITIC RESISTANCES AND METHOD

Patent #:	9899259	Issue Dt:	02/20/2018	Application #:	15443523	Filing Dt:	02/27/2017
Publication #:	US20170170070	Pub Dt:	06/15/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	10229999	Issue Dt:	03/12/2019	Application #:	15445392	Filing Dt:	02/28/2017
Publication #:	US20180248046	Pub Dt:	08/30/2018
Title:	METHODS OF FORMING UPPER SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE

Patent #:	9935168	Issue Dt:	04/03/2018	Application #:	15445481	Filing Dt:	02/28/2017
Publication #:	US20170170266	Pub Dt:	06/15/2017
Title:	GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN

Patent #:	10109722	Issue Dt:	10/23/2018	Application #:	15447210	Filing Dt:	03/02/2017
Publication #:	US20180254331	Pub Dt:	09/06/2018
Title:	ETCH-RESISTANT SPACER FORMATION ON GATE STRUCTURE

Patent #:	9831317	Issue Dt:	11/28/2017	Application #:	15447639	Filing Dt:	03/02/2017
Title:	BURIED CONTACT STRUCTURES FOR A VERTICAL FIELD-EFFECT TRANSISTOR

Patent #:	9899257	Issue Dt:	02/20/2018	Application #:	15448873	Filing Dt:	03/03/2017
Title:	ETCH STOP LINER FOR CONTACT PUNCH THROUGH MITIGATION IN SOI SUBSTRATE

Patent #:	10249726	Issue Dt:	04/02/2019	Application #:	15451565	Filing Dt:	03/07/2017
Publication #:	US20170179246	Pub Dt:	06/22/2017
Title:	METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	10074571	Issue Dt:	09/11/2018	Application #:	15451869	Filing Dt:	03/07/2017
Publication #:	US20180261512	Pub Dt:	09/13/2018
Title:	DEVICE WITH DECREASED PITCH CONTACT TO ACTIVE REGIONS

Patent #:	10109636	Issue Dt:	10/23/2018	Application #:	15453124	Filing Dt:	03/08/2017
Publication #:	US20180261604	Pub Dt:	09/13/2018
Title:	ACTIVE CONTACT AND GATE CONTACT INTERCONNECT FOR MITIGATING ADJACENT GATE ELECTRODE SHORTAGES

Patent #:	10157832	Issue Dt:	12/18/2018	Application #:	15453133	Filing Dt:	03/08/2017
Publication #:	US20180261536	Pub Dt:	09/13/2018
Title:	INTERGRATED CIRCUIT STRUCTURE INCLUDING VIA INTERCONNECT STRUCTURE ABUTTING LATERAL ENDS OF METAL LINES AND METHODS OF FORMING SAME

Patent #:	9865681	Issue Dt:	01/09/2018	Application #:	15453170	Filing Dt:	03/08/2017
Title:	NANOWIRE TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

Patent #:	9923082	Issue Dt:	03/20/2018	Application #:	15453939	Filing Dt:	03/09/2017
Publication #:	US20170179257	Pub Dt:	06/22/2017
Title:	JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE

Patent #:	10546785	Issue Dt:	01/28/2020	Application #:	15454445	Filing Dt:	03/09/2017
Publication #:	US20180261507	Pub Dt:	09/13/2018
Title:	METHOD TO RECESS COBALT FOR GATE METAL APPLICATION

Patent #:	10020386	Issue Dt:	07/10/2018	Application #:	15454511	Filing Dt:	03/09/2017
Title:	HIGH-VOLTAGE AND ANALOG BIPOLAR DEVICES

Patent #:	10177041	Issue Dt:	01/08/2019	Application #:	15455203	Filing Dt:	03/10/2017
Publication #:	US20180261514	Pub Dt:	09/13/2018
Title:	FIN-TYPE FIELD EFFECT TRANSISTORS (FINFETS) WITH REPLACEMENT METAL GATES AND METHODS

Patent #:	10242982	Issue Dt:	03/26/2019	Application #:	15455313	Filing Dt:	03/10/2017
Publication #:	US20180261595	Pub Dt:	09/13/2018
Title:	METHOD FOR FORMING A PROTECTION DEVICE HAVING AN INNER CONTACT SPACER AND THE RESULTING DEVICES

Patent #:	9793294	Issue Dt:	10/17/2017	Application #:	15455588	Filing Dt:	03/10/2017
Title:	JUNCTION FORMATION WITH REDUCED CEFF FOR 22NM FDSOI DEVICES

Patent #:	9905694	Issue Dt:	02/27/2018	Application #:	15457017	Filing Dt:	03/13/2017
Publication #:	US20180026137	Pub Dt:	01/25/2018
Title:	FIN-TYPE FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS

Patent #:	10163633	Issue Dt:	12/25/2018	Application #:	15457200	Filing Dt:	03/13/2017
Publication #:	US20180261457	Pub Dt:	09/13/2018
Title:	NON-MANDREL CUT FORMATION

Patent #:	10103224	Issue Dt:	10/16/2018	Application #:	15457384	Filing Dt:	03/13/2017
Publication #:	US20170288015	Pub Dt:	10/05/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A TRENCH CAPPING LAYER

Patent #:	9891039	Issue Dt:	02/13/2018	Application #:	15458124	Filing Dt:	03/14/2017
Title:	METHOD AND DEVICE FOR MEASURING PLATING RING ASSEMBLY DIMENSIONS

Patent #:	10002827	Issue Dt:	06/19/2018	Application #:	15458140	Filing Dt:	03/14/2017
Publication #:	US20170186687	Pub Dt:	06/29/2017
Title:	METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE

Patent #:	9997695	Issue Dt:	06/12/2018	Application #:	15458316	Filing Dt:	03/14/2017
Publication #:	US20170222126	Pub Dt:	08/03/2017
Title:	METHODS TO UTILIZE PIEZOELECTRIC MATERIALS AS GATE DIELECTRIC IN HIGH FREQUENCY RBTs IN AN IC DEVICE

Patent #:	10236363	Issue Dt:	03/19/2019	Application #:	15458457	Filing Dt:	03/14/2017
Publication #:	US20180269312	Pub Dt:	09/20/2018
Title:	VERTICAL FIELD-EFFECT TRANSISTORS WITH CONTROLLED DIMENSIONS

Patent #:	10340352	Issue Dt:	07/02/2019	Application #:	15458482	Filing Dt:	03/14/2017
Publication #:	US20180269295	Pub Dt:	09/20/2018
Title:	FIELD-EFFECT TRANSISTORS WITH A T-SHAPED GATE ELECTRODE

Patent #:	10770440	Issue Dt:	09/08/2020	Application #:	15459336	Filing Dt:	03/15/2017
Publication #:	US20180269191	Pub Dt:	09/20/2018
Title:	MICRO-LED DISPLAY ASSEMBLY

Patent #:	9871096	Issue Dt:	01/16/2018	Application #:	15459450	Filing Dt:	03/15/2017
Publication #:	US20170250243	Pub Dt:	08/31/2017
Title:	SERIAL CAPACITOR DEVICE WITH MIDDLE ELECTRODE CONTACT

Patent #:	10079597	Issue Dt:	09/18/2018	Application #:	15459867	Filing Dt:	03/15/2017
Publication #:	US20180269868	Pub Dt:	09/20/2018
Title:	CIRCUIT TUNING SCHEME FOR FDSOI

Patent #:	10068835	Issue Dt:	09/04/2018	Application #:	15461538	Filing Dt:	03/17/2017
Publication #:	US20170186669	Pub Dt:	06/29/2017
Title:	PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION

Patent #:	10283608	Issue Dt:	05/07/2019	Application #:	15461634	Filing Dt:	03/17/2017
Publication #:	US20180269297	Pub Dt:	09/20/2018
Title:	LOW RESISTANCE CONTACTS TO SOURCE OR DRAIN REGION OF TRANSISTOR

Patent #:	9985135	Issue Dt:	05/29/2018	Application #:	15462644	Filing Dt:	03/17/2017
Publication #:	US20170194499	Pub Dt:	07/06/2017
Title:	REPLACEMENT LOW-K SPACER

Patent #:	10033383	Issue Dt:	07/24/2018	Application #:	15463316	Filing Dt:	03/20/2017
Title:	PROGRAMMABLE LOGIC ELEMENTS AND METHODS OF OPERATING THE SAME

Patent #:	9966128	Issue Dt:	05/08/2018	Application #:	15463394	Filing Dt:	03/20/2017
Title:	STORAGE STRUCTURE WITH NON-VOLATILE STORAGE CAPABILITY AND A METHOD OF OPERATING THE SAME

Patent #:	10147783	Issue Dt:	12/04/2018	Application #:	15463465	Filing Dt:	03/20/2017
Publication #:	US20180269275	Pub Dt:	09/20/2018
Title:	ON-CHIP CAPACITORS WITH FLOATING ISLANDS

Patent #:	10002793	Issue Dt:	06/19/2018	Application #:	15464591	Filing Dt:	03/21/2017
Title:	SUB-FIN DOPING METHOD

Patent #:	10083874	Issue Dt:	09/25/2018	Application #:	15467536	Filing Dt:	03/23/2017
Publication #:	US20180277440	Pub Dt:	09/27/2018
Title:	GATE CUT METHOD

Patent #:	10217839	Issue Dt:	02/26/2019	Application #:	15468170	Filing Dt:	03/24/2017
Publication #:	US20180277652	Pub Dt:	09/27/2018
Title:	FIELD EFFECT TRANSISTOR (FET) WITH A GATE HAVING A RECESSED WORK FUNCTION METAL LAYER AND METHOD OF FORMING THE FET

Patent #:	10211100	Issue Dt:	02/19/2019	Application #:	15469701	Filing Dt:	03/27/2017
Publication #:	US20180277430	Pub Dt:	09/27/2018
Title:	METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A GATE CONTACT ABOVE THE ACTIVE REGION OF THE TRANSISTOR

Patent #:	10008456	Issue Dt:	06/26/2018	Application #:	15469983	Filing Dt:	03/27/2017
Title:	LAMINATED SPACERS FOR FIELD-EFFECT TRANSISTORS

Patent #:	10084053	Issue Dt:	09/25/2018	Application #:	15470205	Filing Dt:	03/27/2017
Publication #:	US20180277645	Pub Dt:	09/27/2018
Title:	GATE CUTS AFTER METAL GATE FORMATION

Patent #:	9935179	Issue Dt:	04/03/2018	Application #:	15472556	Filing Dt:	03/29/2017
Publication #:	US20170200812	Pub Dt:	07/13/2017
Title:	METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES

Patent #:	10068978	Issue Dt:	09/04/2018	Application #:	15472924	Filing Dt:	03/29/2017
Publication #:	US20170200797	Pub Dt:	07/13/2017
Title:	METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LAYER WITH LATERAL OVER-GROWTH SUPPRESSION

Patent #:	10134880	Issue Dt:	11/20/2018	Application #:	15473043	Filing Dt:	03/29/2017
Publication #:	US20180286968	Pub Dt:	10/04/2018
Title:	SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS WITH A BASE GROWN IN A DIELECTRIC CAVITY

Patent #:	10290582	Issue Dt:	05/14/2019	Application #:	15473371	Filing Dt:	03/29/2017
Publication #:	US20170207165	Pub Dt:	07/20/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL DESIGN

Patent #:	10649026	Issue Dt:	05/12/2020	Application #:	15474104	Filing Dt:	03/30/2017
Publication #:	US20180284184	Pub Dt:	10/04/2018
Title:	APPARATUS FOR AND METHOD OF NET TRACE PRIOR LEVEL SUBTRACTION

Patent #:	10510663	Issue Dt:	12/17/2019	Application #:	15474354	Filing Dt:	03/30/2017
Publication #:	US20180286801	Pub Dt:	10/04/2018
Title:	TRANSISTOR STRUCTURES HAVING ELECTRICALLY FLOATING METAL LAYER BETWEEN ACTIVE METAL LINES

Patent #:	10114282	Issue Dt:	10/30/2018	Application #:	15474408	Filing Dt:	03/30/2017
Publication #:	US20170205703	Pub Dt:	07/20/2017
Title:	SAMPLING FOR OPC MODEL BUILDING

Patent #:	10090169	Issue Dt:	10/02/2018	Application #:	15475272	Filing Dt:	03/31/2017
Publication #:	US20180286965	Pub Dt:	10/04/2018
Title:	METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING OPENING FILLED WITH INSULATOR IN METAL GATE

Patent #:	10134876	Issue Dt:	11/20/2018	Application #:	15475873	Filing Dt:	03/31/2017
Publication #:	US20180286982	Pub Dt:	10/04/2018
Title:	FINFETs WITH STRAINED CHANNELS AND REDUCED ON STATE RESISTANCE

Patent #:	10090385	Issue Dt:	10/02/2018	Application #:	15475946	Filing Dt:	03/31/2017
Publication #:	US20180286951	Pub Dt:	10/04/2018
Title:	METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE WITH A CHANNEL STRUCTURE COMPRISED OF ALTERNATIVE SEMICONDUCTOR MATERIALS

Patent #:	10361132	Issue Dt:	07/23/2019	Application #:	15476158	Filing Dt:	03/31/2017
Publication #:	US20170207134	Pub Dt:	07/20/2017
Title:	STRUCTURES WITH THINNED DIELECTRIC MATERIAL

Patent #:	10204994	Issue Dt:	02/12/2019	Application #:	15477565	Filing Dt:	04/03/2017
Publication #:	US20180286956	Pub Dt:	10/04/2018
Title:	METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

Patent #:	10163697	Issue Dt:	12/25/2018	Application #:	15478385	Filing Dt:	04/04/2017
Publication #:	US20170207121	Pub Dt:	07/20/2017
Title:	METHOD FOR FORMING BEOL METAL LEVELS WITH MULTIPLE DIELECTRIC LAYERS FOR IMPROVED DIELECTRIC TO METAL ADHESION

Patent #:	10622266	Issue Dt:	04/14/2020	Application #:	15478441	Filing Dt:	04/04/2017
Publication #:	US20180286681	Pub Dt:	10/04/2018
Title:	METHODS OF IDENTIFYING SPACE WITHIN INTEGRATED CIRCUIT STRUCTURE AS MANDREL SPACE OR NON-MANDREL SPACE

Patent #:	9847391	Issue Dt:	12/19/2017	Application #:	15479801	Filing Dt:	04/05/2017
Title:	STACKED NANOSHEET FIELD-EFFECT TRANSISTOR WITH DIODE ISOLATION

Patent #:	10054974	Issue Dt:	08/21/2018	Application #:	15480931	Filing Dt:	04/06/2017
Title:	CURRENT MIRROR DEVICES USING CASCODE WITH BACK-GATE BIAS

Patent #:	10147715	Issue Dt:	12/04/2018	Application #:	15481202	Filing Dt:	04/06/2017
Publication #:	US20180026028	Pub Dt:	01/25/2018
Title:	METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS

Patent #:	10475692	Issue Dt:	11/12/2019	Application #:	15481826	Filing Dt:	04/07/2017
Publication #:	US20180294267	Pub Dt:	10/11/2018
Title:	SELF ALIGNED BURIED POWER RAIL

Patent #:	9935180	Issue Dt:	04/03/2018	Application #:	15482040	Filing Dt:	04/07/2017
Publication #:	US20170243956	Pub Dt:	08/24/2017
Title:	FIN CUT FOR TAPER DEVICE

Patent #:	10041183	Issue Dt:	08/07/2018	Application #:	15482938	Filing Dt:	04/10/2017
Publication #:	US20170211199	Pub Dt:	07/27/2017
Title:	ELECTRODEPOSITION SYSTEMS AND METHODS THAT MINIMIZE ANODE AND/OR PLATING SOLUTION DEGRADATION

Patent #:	9972621	Issue Dt:	05/15/2018	Application #:	15483344	Filing Dt:	04/10/2017
Title:	FIN STRUCTURE IN SUBLITHO DIMENSION FOR HIGH PERFORMANCE CMOS APPLICATION

Patent #:	9984893	Issue Dt:	05/29/2018	Application #:	15483346	Filing Dt:	04/10/2017
Publication #:	US20170213741	Pub Dt:	07/27/2017
Title:	FIN CUT FOR TAPER DEVICE

Patent #:	10290738	Issue Dt:	05/14/2019	Application #:	15483476	Filing Dt:	04/10/2017
Publication #:	US20180294348	Pub Dt:	10/11/2018
Title:	METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL ON A RECESSED FIN IN THE SOURCE/DRAIN REGIONS OF A FINFET DEVICE

Patent #:	10236253	Issue Dt:	03/19/2019	Application #:	15484309	Filing Dt:	04/11/2017
Publication #:	US20170221808	Pub Dt:	08/03/2017
Title:	SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY

Patent #:	10297664	Issue Dt:	05/21/2019	Application #:	15486351	Filing Dt:	04/13/2017
Publication #:	US20180301531	Pub Dt:	10/18/2018
Title:	NANOSHEET TRANSISTOR WITH UNIFORM EFFECTIVE GATE LENGTH

Patent #:	9818836	Issue Dt:	11/14/2017	Application #:	15486387	Filing Dt:	04/13/2017
Title:	GATE CUT METHOD FOR REPLACEMENT METAL GATE INTEGRATION

Patent #:	10374106	Issue Dt:	08/06/2019	Application #:	15486849	Filing Dt:	04/13/2017
Publication #:	US20180301569	Pub Dt:	10/18/2018
Title:	INTEGRATED GRAPHENE DETECTORS WITH WAVEGUIDES

Patent #:	10014296	Issue Dt:	07/03/2018	Application #:	15487636	Filing Dt:	04/14/2017
Title:	FIN-TYPE FIELD EFFECT TRANSISTORS WITH SINGLE-DIFFUSION BREAKS AND METHOD

Patent #:	10374092	Issue Dt:	08/06/2019	Application #:	15488615	Filing Dt:	04/17/2017
Publication #:	US20180302038	Pub Dt:	10/18/2018
Title:	POWER AMPLIFIER RAMPING AND POWER CONTROL WITH FORWARD AND REVERSE BACK-GATE BIAS

Patent #:	9831175	Issue Dt:	11/28/2017	Application #:	15489404	Filing Dt:	04/17/2017
Publication #:	US20170221823	Pub Dt:	08/03/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES

Patent #:	10008576	Issue Dt:	06/26/2018	Application #:	15490180	Filing Dt:	04/18/2017
Publication #:	US20170222015	Pub Dt:	08/03/2017
Title:	EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES

Patent #:	9966338	Issue Dt:	05/08/2018	Application #:	15490181	Filing Dt:	04/18/2017
Title:	PRE-SPACER SELF-ALIGNED CUT FORMATION

Patent #:	9960271	Issue Dt:	05/01/2018	Application #:	15490255	Filing Dt:	04/18/2017
Title:	METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING INTEGRATED CIRCUIT STRUCTURE

Patent #:	10056373	Issue Dt:	08/21/2018	Application #:	15490702	Filing Dt:	04/18/2017
Publication #:	US20170221886	Pub Dt:	08/03/2017
Title:	TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS

Patent #:	9922972	Issue Dt:	03/20/2018	Application #:	15491222	Filing Dt:	04/19/2017
Title:	EMBEDDED SILICON CARBIDE BLOCK PATTERNING

Patent #:	10014370	Issue Dt:	07/03/2018	Application #:	15491420	Filing Dt:	04/19/2017
Title:	AIR GAP ADJACENT A BOTTOM SOURCE/DRAIN REGION OF VERTICAL TRANSISTOR DEVICE

Patent #:	10056303	Issue Dt:	08/21/2018	Application #:	15494119	Filing Dt:	04/21/2017
Title:	INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL

Patent #:	9905424	Issue Dt:	02/27/2018	Application #:	15494803	Filing Dt:	04/24/2017
Title:	SELF-ALIGNED NON-MANDREL CUT FORMATION FOR TONE INVERSION

Patent #:	10003302	Issue Dt:	06/19/2018	Application #:	15496049	Filing Dt:	04/25/2017
Publication #:	US20170230004	Pub Dt:	08/10/2017
Title:	MODIFIED TUNNELING FIELD EFFECT TRANSISTORS AND FABRICATION METHODS

Patent #:	10177037	Issue Dt:	01/08/2019	Application #:	15496429	Filing Dt:	04/25/2017
Publication #:	US20180308759	Pub Dt:	10/25/2018
Title:	METHODS OF FORMING A CT PILLAR BETWEEN GATE STRUCTURES IN A SEMICONDUCTOR

Patent #:	10062560	Issue Dt:	08/28/2018	Application #:	15497647	Filing Dt:	04/26/2017
Title:	METHOD OF CLEANING SEMICONDUCTOR DEVICE

Patent #:	9953927	Issue Dt:	04/24/2018	Application #:	15497828	Filing Dt:	04/26/2017
Title:	LINER REPLACEMENTS FOR INTERCONNECT OPENINGS

Patent #:	10297589	Issue Dt:	05/21/2019	Application #:	15497924	Filing Dt:	04/26/2017
Publication #:	US20170229443	Pub Dt:	08/10/2017
Title:	ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERTICAL GATE FIN-TYPE FIELD EFFECT DIODE

Patent #:	10153232	Issue Dt:	12/11/2018	Application #:	15498083	Filing Dt:	04/26/2017
Publication #:	US20180315707	Pub Dt:	11/01/2018
Title:	CRACK STOP WITH OVERLAPPING VIAS

Patent #:	10032891	Issue Dt:	07/24/2018	Application #:	15498652	Filing Dt:	04/27/2017
Publication #:	US20170271484	Pub Dt:	09/21/2017
Title:	FINFET BASED FLASH MEMORY CELL

Patent #:	10178718	Issue Dt:	01/08/2019	Application #:	15531458	Filing Dt:	05/29/2017
Publication #:	US20170273153	Pub Dt:	09/21/2017
Title:	A SYSTEM AND METHOD FOR ACTIVE POWER FACTOR CORRECTION AND CURRENT REGULATION IN LED CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	15531459	Filing Dt:	05/29/2017
Publication #:	US20170273150	Pub Dt:	09/21/2017
Title:	DYNAMIC BLEED SYSTEM AND METHOD FOR DYNAMIC LOADING OF A DIMMER USING EVENT DRIVEN ARCHITECTURE

Patent #:	10349482	Issue Dt:	07/09/2019	Application #:	15531460	Filing Dt:	05/29/2017
Publication #:	US20180295692	Pub Dt:	10/11/2018
Title:	SYSTEM AND METHOD TO REGULATE PRIMARY SIDE CURRENT USING AN EVENT DRIVEN ARCHITECTURE IN LED CIRCUIT

Patent #:	10490641	Issue Dt:	11/26/2019	Application #:	15581053	Filing Dt:	04/28/2017
Publication #:	US20180315821	Pub Dt:	11/01/2018
Title:	METHODS OF FORMING A GATE CONTACT STRUCTURE FOR A TRANSISTOR

Patent #:	10483363	Issue Dt:	11/19/2019	Application #:	15581105	Filing Dt:	04/28/2017
Publication #:	US20180315822	Pub Dt:	11/01/2018
Title:	METHODS OF FORMING A GATE CONTACT STRUCTURE ABOVE AN ACTIVE REGION OF A TRANSISTOR

Patent #:	9887135	Issue Dt:	02/06/2018	Application #:	15581510	Filing Dt:	04/28/2017
Title:	METHODS FOR PROVIDING VARIABLE FEATURE WIDTHS IN A SELF-ALIGNED SPACER-MASK PATTERNING PROCESS

Patent #:	11764060	Issue Dt:	09/19/2023	Application #:	15584121	Filing Dt:	05/02/2017
Publication #:	US20180323066	Pub Dt:	11/08/2018
Title:	FIELD-EFFECT TRANSISTORS WITH A BODY PEDESTAL

Patent #:	10176859	Issue Dt:	01/08/2019	Application #:	15585709	Filing Dt:	05/03/2017
Publication #:	US20180322912	Pub Dt:	11/08/2018
Title:	NON-VOLATILE TRANSISTOR ELEMENT INCLUDING A BURIED FERROELECTRIC MATERIAL BASED STORAGE MECHANISM

Patent #:	9887094	Issue Dt:	02/06/2018	Application #:	15585800	Filing Dt:	05/03/2017
Title:	METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL ON THE SOURCE/DRAIN REGIONS OF A FINFET DEVICE

Patent #:	10121868	Issue Dt:	11/06/2018	Application #:	15585865	Filing Dt:	05/03/2017
Publication #:	US20180323269	Pub Dt:	11/08/2018
Title:	METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL ON A THINNED FIN IN THE SOURCE/DRAIN REGIONS OF A FINFET DEVICE

Patent #:	9817940	Issue Dt:	11/14/2017	Application #:	15585972	Filing Dt:	05/03/2017
Publication #:	US20170235866	Pub Dt:	08/17/2017
Title:	METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOUT OF AN INTEGRATED CIRCUIT

Patent #:	9911738	Issue Dt:	03/06/2018	Application #:	15586621	Filing Dt:	05/04/2017
Title:	VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH A DAMASCENE GATE STRAP

100

Patent #:	10249496	Issue Dt:	04/02/2019	Application #:	15587597	Filing Dt:	05/05/2017
Publication #:	US20180323067	Pub Dt:	11/08/2018
Title:	NARROWED FEATURE FORMATION DURING A DOUBLE PATTERNING PROCESS

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

Search Results as of: 05/11/2024 08:34 PM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6