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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 72 of 85
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Patent #:	10120963	Issue Dt:	11/06/2018	Application #:	15587602	Filing Dt:	05/05/2017
Publication #:	US20180322228	Pub Dt:	11/08/2018
Title:	FIGURATIVE MODELS CALIBRATED TO CORRECT ERRORS IN PROCESS MODELS

Patent #:	10121713	Issue Dt:	11/06/2018	Application #:	15589126	Filing Dt:	05/08/2017
Publication #:	US20180323117	Pub Dt:	11/08/2018
Title:	IN-KERF TEST STRUCTURE AND TESTING METHOD FOR A MEMORY ARRAY

Patent #:	10008496	Issue Dt:	06/26/2018	Application #:	15589139	Filing Dt:	05/08/2017
Title:	METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING CONTINUOUS FIN DIFFUSION BREAK

Patent #:	9935104	Issue Dt:	04/03/2018	Application #:	15589292	Filing Dt:	05/08/2017
Title:	FIN-TYPE FIELD EFFECT TRANSISTORS WITH SINGLE-DIFFUSION BREAKS AND METHOD

Patent #:	10014297	Issue Dt:	07/03/2018	Application #:	15589312	Filing Dt:	05/08/2017
Title:	METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE USING EXTREME ULTRAVIOLET PHOTOLITHOGRAPHY TECHNIQUE AND RELATED INTEGRATED CIRCUIT STRUCTURE

Patent #:	10026693	Issue Dt:	07/17/2018	Application #:	15589829	Filing Dt:	05/08/2017
Publication #:	US20170243823	Pub Dt:	08/24/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR MOL INTERCONNECTS WITHOUT TITANIUM LINER

Patent #:	10192786	Issue Dt:	01/29/2019	Application #:	15590195	Filing Dt:	05/09/2017
Publication #:	US20180330994	Pub Dt:	11/15/2018
Title:	PROCESS FOR VARIABLE FIN PITCH AND CRITICAL DIMENSION

Patent #:	10269983	Issue Dt:	04/23/2019	Application #:	15590409	Filing Dt:	05/09/2017
Publication #:	US20180331232	Pub Dt:	11/15/2018
Title:	STACKED NANOSHEET FIELD-EFFECT TRANSISTOR WITH AIR GAP SPACERS

Patent #:	10347729	Issue Dt:	07/09/2019	Application #:	15590459	Filing Dt:	05/09/2017
Publication #:	US20170365676	Pub Dt:	12/21/2017
Title:	DEVICE FOR IMPROVING PERFORMANCE THROUGH GATE CUT LAST PROCESS

Patent #:	10043713	Issue Dt:	08/07/2018	Application #:	15591814	Filing Dt:	05/10/2017
Title:	METHOD TO REDUCE FINFET SHORT CHANNEL GATE HEIGHT

Patent #:	10204904	Issue Dt:	02/12/2019	Application #:	15592172	Filing Dt:	05/10/2017
Publication #:	US20180331097	Pub Dt:	11/15/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR VERTICAL FINFET DEVICE WITH REDUCED PARASITIC CAPACITANCE

Patent #:	10217864	Issue Dt:	02/26/2019	Application #:	15592444	Filing Dt:	05/11/2017
Publication #:	US20180331212	Pub Dt:	11/15/2018
Title:	DOUBLE GATE VERTICAL FINFET SEMICONDUCTOR STRUCTURE

Patent #:	9899525	Issue Dt:	02/20/2018	Application #:	15592597	Filing Dt:	05/11/2017
Publication #:	US20170250285	Pub Dt:	08/31/2017
Title:	INCREASED CONTACT AREA FOR FINFETS

Patent #:	10014214	Issue Dt:	07/03/2018	Application #:	15593496	Filing Dt:	05/12/2017
Publication #:	US20170250111	Pub Dt:	08/31/2017
Title:	ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH

Patent #:	10236379	Issue Dt:	03/19/2019	Application #:	15593651	Filing Dt:	05/12/2017
Publication #:	US20180331213	Pub Dt:	11/15/2018
Title:	VERTICAL FET WITH SELF-ALIGNED SOURCE/DRAIN REGIONS AND GATE LENGTH BASED ON CHANNEL EPITAXIAL GROWTH PROCESS

Patent #:	9929247	Issue Dt:	03/27/2018	Application #:	15594757	Filing Dt:	05/15/2017
Publication #:	US20170250262	Pub Dt:	08/31/2017
Title:	ETCH STOP FOR AIRGAP PROTECTION

Patent #:	10643894	Issue Dt:	05/05/2020	Application #:	15597650	Filing Dt:	05/17/2017
Publication #:	US20180006141	Pub Dt:	01/04/2018
Title:	SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY

Patent #:	10242867	Issue Dt:	03/26/2019	Application #:	15598393	Filing Dt:	05/18/2017
Publication #:	US20180337037	Pub Dt:	11/22/2018
Title:	GATE PICKUP METHOD USING METAL SELECTIVITY

Patent #:	9905473	Issue Dt:	02/27/2018	Application #:	15598447	Filing Dt:	05/18/2017
Title:	SELF-ALIGNED CONTACT ETCH FOR FABRICATING A FINFET

Patent #:	10685847	Issue Dt:	06/16/2020	Application #:	15598905	Filing Dt:	05/18/2017
Publication #:	US20170263465	Pub Dt:	09/14/2017
Title:	VERTICAL NANOWIRES FORMED ON UPPER FIN SURFACE

Patent #:	10388691	Issue Dt:	08/20/2019	Application #:	15599427	Filing Dt:	05/18/2017
Publication #:	US20170338275	Pub Dt:	11/23/2017
Title:	LIGHT EMITTING DIODES (LEDS) WITH STACKED MULTI-COLOR PIXELS FOR DISPLAYS

Patent #:	9941329	Issue Dt:	04/10/2018	Application #:	15599438	Filing Dt:	05/18/2017
Publication #:	US20170338276	Pub Dt:	11/23/2017
Title:	LIGHT EMITTING DIODES (LEDs) WITH INTEGRATED CMOS CIRCUITS

Patent #:	9941330	Issue Dt:	04/10/2018	Application #:	15599458	Filing Dt:	05/18/2017
Publication #:	US20170338277	Pub Dt:	11/23/2017
Title:	LEDS WITH THREE COLOR RGB PIXELS FOR DISPLAYS

Patent #:	10037981	Issue Dt:	07/31/2018	Application #:	15599465	Filing Dt:	05/18/2017
Publication #:	US20170358562	Pub Dt:	12/14/2017
Title:	INTEGRATED DISPLAY SYSTEM WITH MULTI-COLOR LIGHT EMITTING DIODES (LEDS)

Patent #:	9935112	Issue Dt:	04/03/2018	Application #:	15599581	Filing Dt:	05/19/2017
Title:	SRAM CELL HAVING DUAL PASS GATE TRANSISTORS AND METHOD OF MAKING THE SAME

Patent #:	10236768	Issue Dt:	03/19/2019	Application #:	15599596	Filing Dt:	05/19/2017
Publication #:	US20180337596	Pub Dt:	11/22/2018
Title:	SWITCHED-CAPACITOR CHARGE PUMP WITH REDUCED DIODE THRESHOLD VOLTAGE AND ON STATE RESISTANCE

Patent #:	9960233	Issue Dt:	05/01/2018	Application #:	15600837	Filing Dt:	05/22/2017
Publication #:	US20170263707	Pub Dt:	09/14/2017
Title:	EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR

Patent #:	10084093	Issue Dt:	09/25/2018	Application #:	15600872	Filing Dt:	05/22/2017
Title:	LOW RESISTANCE CONDUCTIVE CONTACTS

Patent #:	9947589	Issue Dt:	04/17/2018	Application #:	15600874	Filing Dt:	05/22/2017
Title:	METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE AN ACTIVE REGION AND THE RESULTING DEVICE

Patent #:	10410933	Issue Dt:	09/10/2019	Application #:	15602225	Filing Dt:	05/23/2017
Publication #:	US20180342427	Pub Dt:	11/29/2018
Title:	REPLACEMENT METAL GATE PATTERNING FOR NANOSHEET DEVICES

Patent #:	10157833	Issue Dt:	12/18/2018	Application #:	15602801	Filing Dt:	05/23/2017
Publication #:	US20180342454	Pub Dt:	11/29/2018
Title:	VIA AND SKIP VIA STRUCTURES

Patent #:	10163914	Issue Dt:	12/25/2018	Application #:	15603827	Filing Dt:	05/24/2017
Publication #:	US20180261605	Pub Dt:	09/13/2018
Title:	METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS

Patent #:	9972606	Issue Dt:	05/15/2018	Application #:	15604803	Filing Dt:	05/25/2017
Publication #:	US20170271309	Pub Dt:	09/21/2017
Title:	THREE-DIMENSIONAL HYBRID PACKAGING WITH THROUGH-SILICON-VIAS AND TAPE-AUTOMATED-BONDING

Patent #:	10199270	Issue Dt:	02/05/2019	Application #:	15605327	Filing Dt:	05/25/2017
Publication #:	US20180342421	Pub Dt:	11/29/2018
Title:	MULTI-DIRECTIONAL SELF-ALIGNED MULTIPLE PATTERNING

Patent #:	10109521	Issue Dt:	10/23/2018	Application #:	15606895	Filing Dt:	05/26/2017
Title:	METHOD TO PREVENT COBALT RECESS

Patent #:	10096488	Issue Dt:	10/09/2018	Application #:	15608283	Filing Dt:	05/30/2017
Publication #:	US20170263733	Pub Dt:	09/14/2017
Title:	FINFET SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SAME

Patent #:	10249534	Issue Dt:	04/02/2019	Application #:	15608506	Filing Dt:	05/30/2017
Publication #:	US20180350679	Pub Dt:	12/06/2018
Title:	METHOD OF FORMING A CONTACT ELEMENT OF A SEMICONDUCTOR DEVICE AND CONTACT ELEMENT STRUCTURE

Patent #:	10090204	Issue Dt:	10/02/2018	Application #:	15609201	Filing Dt:	05/31/2017
Title:	VERTICAL FINFET STRUCTURE AND METHODS OF FORMING SAME

Patent #:	9893154	Issue Dt:	02/13/2018	Application #:	15609295	Filing Dt:	05/31/2017
Publication #:	US20170294515	Pub Dt:	10/12/2017
Title:	RECESS LINER FOR SILICON GERMANIUM FIN FORMATION

Patent #:	10109526	Issue Dt:	10/23/2018	Application #:	15609408	Filing Dt:	05/31/2017
Title:	ETCH PROFILE CONTROL DURING SKIP VIA FORMATION

Patent #:	10037919	Issue Dt:	07/31/2018	Application #:	15609603	Filing Dt:	05/31/2017
Title:	INTEGRATED SINGLE-GATED VERTICAL FIELD EFFECT TRANSISTOR (VFET) AND INDEPENDENT DOUBLE-GATED VFET

Patent #:	10163679	Issue Dt:	12/25/2018	Application #:	15609742	Filing Dt:	05/31/2017
Publication #:	US20180350659	Pub Dt:	12/06/2018
Title:	SHALLOW TRENCH ISOLATION FORMATION WITHOUT PLANARIZATION

Patent #:	9922973	Issue Dt:	03/20/2018	Application #:	15611184	Filing Dt:	06/01/2017
Title:	SWITCHES WITH DEEP TRENCH DEPLETION AND ISOLATION STRUCTURES

Patent #:	10008385	Issue Dt:	06/26/2018	Application #:	15612335	Filing Dt:	06/02/2017
Title:	ENLARGED SACRIFICIAL GATE CAPS FOR FORMING SELF-ALIGNED CONTACTS

Patent #:	10083878	Issue Dt:	09/25/2018	Application #:	15613474	Filing Dt:	06/05/2017
Title:	FIN FABRICATION PROCESS WITH DUAL SHALLOW TRENCH ISOLATION AND TUNABLE INNER AND OUTER FIN PROFILE

Patent #:	10083873	Issue Dt:	09/25/2018	Application #:	15613981	Filing Dt:	06/05/2017
Title:	SEMICONDUCTOR STRUCTURE WITH UNIFORM GATE HEIGHTS

Patent #:	10249590	Issue Dt:	04/02/2019	Application #:	15614850	Filing Dt:	06/06/2017
Publication #:	US20180350684	Pub Dt:	12/06/2018
Title:	STACKED DIES USING ONE OR MORE INTERPOSERS

Patent #:	9859217	Issue Dt:	01/02/2018	Application #:	15614925	Filing Dt:	06/06/2017
Title:	MIDDLE OF THE LINE (MOL) METAL CONTACTS

Patent #:	10090209	Issue Dt:	10/02/2018	Application #:	15615072	Filing Dt:	06/06/2017
Publication #:	US20170271213	Pub Dt:	09/21/2017
Title:	METHODS OF PREDICTING UNITY GAIN FREQUENCY WITH DIRECT CURRENT AND/OR LOW FREQUENCY PARAMETERS

Patent #:	10068660	Issue Dt:	09/04/2018	Application #:	15615660	Filing Dt:	06/06/2017
Publication #:	US20170271032	Pub Dt:	09/21/2017
Title:	METHODS, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF WRITE-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY

Patent #:	10276689	Issue Dt:	04/30/2019	Application #:	15615925	Filing Dt:	06/07/2017
Publication #:	US20180358452	Pub Dt:	12/13/2018
Title:	METHOD OF FORMING A VERTICAL FIELD EFFECT TRANSISTOR (VFET) AND A VFET STRUCTURE

Patent #:	10211825	Issue Dt:	02/19/2019	Application #:	15616527	Filing Dt:	06/07/2017
Publication #:	US20180358962	Pub Dt:	12/13/2018
Title:	CIRCUITS HAVING A SWITCH WITH BACK-GATE BIAS

Patent #:	9960248	Issue Dt:	05/01/2018	Application #:	15616653	Filing Dt:	06/07/2017
Publication #:	US20180026113	Pub Dt:	01/25/2018
Title:	FIN-BASED RF DIODES

Patent #:	10153211	Issue Dt:	12/11/2018	Application #:	15616681	Filing Dt:	06/07/2017
Publication #:	US20180358267	Pub Dt:	12/13/2018
Title:	METHODS, APPARATUS, AND SYSTEM FOR FABRICATING FINFET DEVICES WITH INCREASED BREAKDOWN VOLTAGE

Patent #:	10103067	Issue Dt:	10/16/2018	Application #:	15617388	Filing Dt:	06/08/2017
Title:	SEMICONDUCTOR DEVICE COMPRISING TRENCH ISOLATION

Patent #:	9956845	Issue Dt:	05/01/2018	Application #:	15618197	Filing Dt:	06/09/2017
Publication #:	US20170274730	Pub Dt:	09/28/2017
Title:	SYSTEM AND METHOD TO ADJUST VEHICLE TEMPERATURE BASED ON DRIVER LOCATION

Patent #:	10256134	Issue Dt:	04/09/2019	Application #:	15618491	Filing Dt:	06/09/2017
Publication #:	US20180358259	Pub Dt:	12/13/2018
Title:	HEAT DISSIPATIVE ELEMENT FOR POLYSILICON RESISTOR BANK

Patent #:	9941163	Issue Dt:	04/10/2018	Application #:	15618880	Filing Dt:	06/09/2017
Publication #:	US20170278753	Pub Dt:	09/28/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	9905673	Issue Dt:	02/27/2018	Application #:	15620082	Filing Dt:	06/12/2017
Publication #:	US20170278949	Pub Dt:	09/28/2017
Title:	STRESS MEMORIZATION AND DEFECT SUPPRESSION TECHNIQUES FOR NMOS TRANSISTOR DEVICES

Patent #:	10121846	Issue Dt:	11/06/2018	Application #:	15620923	Filing Dt:	06/13/2017
Title:	RESISTOR STRUCTURE WITH HIGH RESISTANCE BASED ON VERY THIN SEMICONDUCTOR LAYER

Patent #:	10319732	Issue Dt:	06/11/2019	Application #:	15622497	Filing Dt:	06/14/2017
Publication #:	US20180366484	Pub Dt:	12/20/2018
Title:	TRANSISTOR ELEMENT INCLUDING A BURIED INSULATING LAYER HAVING ENHANCED FUNCTIONALITY

Patent #:	10074732	Issue Dt:	09/11/2018	Application #:	15622902	Filing Dt:	06/14/2017
Title:	METHODS OF FORMING SHORT CHANNEL AND LONG CHANNEL FINFET DEVICES SO AS TO ADJUST THRESHOLD VOLTAGES

Patent #:	9911736	Issue Dt:	03/06/2018	Application #:	15622949	Filing Dt:	06/14/2017
Title:	METHOD OF FORMING FIELD EFFECT TRANSISTORS WITH REPLACEMENT METAL GATES AND CONTACTS AND RESULTING STRUCTURE

Patent #:	10056334	Issue Dt:	08/21/2018	Application #:	15623691	Filing Dt:	06/15/2017
Publication #:	US20170287837	Pub Dt:	10/05/2017
Title:	DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD

Patent #:	10002792	Issue Dt:	06/19/2018	Application #:	15624156	Filing Dt:	06/15/2017
Publication #:	US20170287785	Pub Dt:	10/05/2017
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	9929236	Issue Dt:	03/27/2018	Application #:	15624762	Filing Dt:	06/16/2017
Title:	ACTIVE AREA SHAPES REDUCING DEVICE SIZE

Patent #:	9960113	Issue Dt:	05/01/2018	Application #:	15625035	Filing Dt:	06/16/2017
Publication #:	US20170294378	Pub Dt:	10/12/2017
Title:	METHOD TO FABRICATE A HIGH PERFORMANCE CAPACITOR IN A BACK END OF LINE (BEOL)

Patent #:	10083861	Issue Dt:	09/25/2018	Application #:	15625360	Filing Dt:	06/16/2017
Publication #:	US20170287776	Pub Dt:	10/05/2017
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	10054630	Issue Dt:	08/21/2018	Application #:	15625609	Filing Dt:	06/16/2017
Publication #:	US20170292986	Pub Dt:	10/12/2017
Title:	METHODS, APPARATUS AND SYSTEM FOR SCREENING PROCESS SPLITS FOR TECHNOLOGY DEVELOPMENT

Patent #:	10157794	Issue Dt:	12/18/2018	Application #:	15626321	Filing Dt:	06/19/2017
Publication #:	US20180366372	Pub Dt:	12/20/2018
Title:	INTEGRATED CIRCUIT STRUCTURE WITH STEPPED EPITAXIAL REGION

Patent #:	10256089	Issue Dt:	04/09/2019	Application #:	15626732	Filing Dt:	06/19/2017
Publication #:	US20180366324	Pub Dt:	12/20/2018
Title:	REPLACEMENT CONTACT CUTS WITH AN ENCAPSULATED LOW-K DIELECTRIC

Patent #:	10249616	Issue Dt:	04/02/2019	Application #:	15627835	Filing Dt:	06/20/2017
Publication #:	US20180366461	Pub Dt:	12/20/2018
Title:	METHODS OF FORMING A RESISTOR STRUCTURE BETWEEN ADJACENT TRANSISTOR GATES ON AN INTEGRATED CIRCUIT PRODUCT AND THE RESULTING DEVICES

Patent #:	10109490	Issue Dt:	10/23/2018	Application #:	15627879	Filing Dt:	06/20/2017
Title:	COBALT INTERCONNECTS FORMED BY SELECTIVE BOTTOM-UP FILL

Patent #:	10128333	Issue Dt:	11/13/2018	Application #:	15627973	Filing Dt:	06/20/2017
Publication #:	US20170288016	Pub Dt:	10/05/2017
Title:	FINFET WITH ISOLATED SOURCE AND DRAIN

Patent #:	10453750	Issue Dt:	10/22/2019	Application #:	15629884	Filing Dt:	06/22/2017
Publication #:	US20180374753	Pub Dt:	12/27/2018
Title:	STACKED ELONGATED NANOSHAPES OF DIFFERENT SEMICONDUCTOR MATERIALS AND STRUCTURES THAT INCORPORATE THE NANOSHAPES

Patent #:	10304735	Issue Dt:	05/28/2019	Application #:	15630002	Filing Dt:	06/22/2017
Publication #:	US20180374749	Pub Dt:	12/27/2018
Title:	MECHANICALLY STABLE COBALT CONTACTS

Patent #:	10176857	Issue Dt:	01/08/2019	Application #:	15630466	Filing Dt:	06/22/2017
Publication #:	US20180374523	Pub Dt:	12/27/2018
Title:	READ AND WRITE SCHEME FOR HIGH DENSITY SRAM

Patent #:	10014209	Issue Dt:	07/03/2018	Application #:	15630546	Filing Dt:	06/22/2017
Publication #:	US20170294338	Pub Dt:	10/12/2017
Title:	METHODS, APPARATUS AND SYSTEM FOR LOCAL ISOLATION FORMATION FOR FINFET DEVICES

Patent #:	10262903	Issue Dt:	04/16/2019	Application #:	15630547	Filing Dt:	06/22/2017
Publication #:	US20180374759	Pub Dt:	12/27/2018
Title:	BOUNDARY SPACER STRUCTURE AND INTEGRATION

Patent #:	10084068	Issue Dt:	09/25/2018	Application #:	15631385	Filing Dt:	06/23/2017
Publication #:	US20170358666	Pub Dt:	12/14/2017
Title:	SELF-ALIGNED FINFET FORMATION

Patent #:	10177151	Issue Dt:	01/08/2019	Application #:	15632702	Filing Dt:	06/26/2017
Publication #:	US20180374851	Pub Dt:	12/27/2018
Title:	SINGLE-DIFFUSION BREAK STRUCTURE FOR FIN-TYPE FIELD EFFECT TRANSISTORS

Patent #:	10002859	Issue Dt:	06/19/2018	Application #:	15632909	Filing Dt:	06/26/2017
Title:	FIN-FET RESONANT BODY TRANSISTOR

Patent #:	10134901	Issue Dt:	11/20/2018	Application #:	15632922	Filing Dt:	06/26/2017
Title:	METHODS OF FORMING A BULK FIELD EFFECT TRANSISTOR (FET) WITH SUB-SOURCE/DRAIN ISOLATION LAYERS AND THE RESULTING STRUCTURES

Patent #:	9899363	Issue Dt:	02/20/2018	Application #:	15632927	Filing Dt:	06/26/2017
Title:	FIN-FET RESONANT BODY TRANSISTOR

Patent #:	9966272	Issue Dt:	05/08/2018	Application #:	15632931	Filing Dt:	06/26/2017
Title:	METHODS FOR NITRIDE PLANARIZATION USING DIELECTRIC

Patent #:	10170353	Issue Dt:	01/01/2019	Application #:	15634091	Filing Dt:	06/27/2017
Publication #:	US20170294336	Pub Dt:	10/12/2017
Title:	DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS

Patent #:	10269707	Issue Dt:	04/23/2019	Application #:	15634135	Filing Dt:	06/27/2017
Publication #:	US20170294385	Pub Dt:	10/12/2017
Title:	SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)

Patent #:	10163915	Issue Dt:	12/25/2018	Application #:	15634227	Filing Dt:	06/27/2017
Publication #:	US20180374857	Pub Dt:	12/27/2018
Title:	VERTICAL SRAM STRUCTURE

Patent #:	10483943	Issue Dt:	11/19/2019	Application #:	15634397	Filing Dt:	06/27/2017
Publication #:	US20180375494	Pub Dt:	12/27/2018
Title:	ARTIFICIALLY ORIENTED PIEZOELECTRIC FILM FOR INTEGRATED FILTERS

Patent #:	9799652	Issue Dt:	10/24/2017	Application #:	15635288	Filing Dt:	06/28/2017
Title:	SEMICONDUCTOR STRUCTURE WITH A DOPANT IMPLANT REGION HAVING A LINEARLY GRADED CONDUCTIVITY LEVEL AND METHOD OF FORMING THE STRUCTURE

Patent #:	10355043	Issue Dt:	07/16/2019	Application #:	15635608	Filing Dt:	06/28/2017
Publication #:	US20190006413	Pub Dt:	01/03/2019
Title:	INTEGRATED VERTICAL TRANSISTORS AND LIGHT EMITTING DIODES

Patent #:	10126354	Issue Dt:	11/13/2018	Application #:	15635711	Filing Dt:	06/28/2017
Title:	ASSESSMENT OF HCI IN LOGIC CIRCUITS BASED ON AC STRESS IN DISCRETE FETS

Patent #:	10109533	Issue Dt:	10/23/2018	Application #:	15636725	Filing Dt:	06/29/2017
Title:	NANOSHEET DEVICES WITH CMOS EPITAXY AND METHOD OF FORMING

Patent #:	10121702	Issue Dt:	11/06/2018	Application #:	15638087	Filing Dt:	06/29/2017
Title:	METHODS, APPARATUS AND SYSTEM FOR FORMING SOURCE/DRAIN CONTACTS USING EARLY TRENCH SILICIDE CUT

Patent #:	10276560	Issue Dt:	04/30/2019	Application #:	15638850	Filing Dt:	06/30/2017
Publication #:	US20190006350	Pub Dt:	01/03/2019
Title:	PASSIVE DEVICE STRUCTURE AND METHODS OF MAKING THEREOF

Patent #:	10038065	Issue Dt:	07/31/2018	Application #:	15639095	Filing Dt:	06/30/2017
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Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

Patent #:	10236206	Issue Dt:	03/19/2019	Application #:	15640748	Filing Dt:	07/03/2017
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Title:	INTERCONNECTS WITH HYBRID METALLIZATION

Patent #:	10211094	Issue Dt:	02/19/2019	Application #:	15641861	Filing Dt:	07/05/2017
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Title:	HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

Patent #:	10468300	Issue Dt:	11/05/2019	Application #:	15641927	Filing Dt:	07/05/2017
Publication #:	US20190013241	Pub Dt:	01/10/2019
Title:	CONTACTING SOURCE AND DRAIN OF A TRANSISTOR DEVICE

100

Patent #:	10177178	Issue Dt:	01/08/2019	Application #:	15642017	Filing Dt:	07/05/2017
Publication #:	US20190013337	Pub Dt:	01/10/2019
Title:	ASSEMBLY OF CMOS DRIVER WAFER AND LED WAFER FOR MICRODISPLAY

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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