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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 76 of 85
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Patent #:	10388654	Issue Dt:	08/20/2019	Application #:	15868058	Filing Dt:	01/11/2018
Publication #:	US20190214387	Pub Dt:	07/11/2019
Title:	METHODS OF FORMING A GATE-TO-SOURCE/DRAIN CONTACT STRUCTURE

Patent #:	10777465	Issue Dt:	09/15/2020	Application #:	15868199	Filing Dt:	01/11/2018
Publication #:	US20190214307	Pub Dt:	07/11/2019
Title:	INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND PLANAR TRANSISTORS

Patent #:	10832965	Issue Dt:	11/10/2020	Application #:	15868229	Filing Dt:	01/11/2018
Publication #:	US20190214308	Pub Dt:	07/11/2019
Title:	FIN REVEAL FORMING STI REGIONS HAVING CONVEX SHAPE BETWEEN FINS

Patent #:	10552569	Issue Dt:	02/04/2020	Application #:	15868364	Filing Dt:	01/11/2018
Publication #:	US20190080038	Pub Dt:	03/14/2019
Title:	METHOD FOR CALCULATING NON-CORRECTABLE EUV BLANK FLATNESS FOR BLANK DISPOSITIONING

Patent #:	10522403	Issue Dt:	12/31/2019	Application #:	15868479	Filing Dt:	01/11/2018
Publication #:	US20190214298	Pub Dt:	07/11/2019
Title:	MIDDLE OF THE LINE SELF-ALIGNED DIRECT PATTERN CONTACTS

Patent #:	10705435	Issue Dt:	07/07/2020	Application #:	15869150	Filing Dt:	01/12/2018
Publication #:	US20190219930	Pub Dt:	07/18/2019
Title:	SELF-REFERENCING AND SELF-CALIBRATING INTERFERENCE PATTERN OVERLAY MEASUREMENT

Patent #:	10211317	Issue Dt:	02/19/2019	Application #:	15869349	Filing Dt:	01/12/2018
Publication #:	US20190051735	Pub Dt:	02/14/2019
Title:	VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH AN ETCHED-THROUGH SOURCE/DRAIN CAVITY

Patent #:	10600914	Issue Dt:	03/24/2020	Application #:	15869541	Filing Dt:	01/12/2018
Publication #:	US20190221661	Pub Dt:	07/18/2019
Title:	ISOLATION PILLAR FIRST GATE STRUCTURES AND METHODS OF FORMING SAME

Patent #:	10508900	Issue Dt:	12/17/2019	Application #:	15870108	Filing Dt:	01/12/2018
Publication #:	US20180135967	Pub Dt:	05/17/2018
Title:	THREE-DIMENSIONAL SCATTEROMETRY FOR MEASURING DIELECTRIC THICKNESS

Patent #:	10290626	Issue Dt:	05/14/2019	Application #:	15870238	Filing Dt:	01/12/2018
Title:	HIGH VOLTAGE ELECTROSTATIC DISCHARGE (ESD) BIPOLAR INTEGRATED IN A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) TECHNOLOGY AND METHOD FOR PRODUCING THE SAME

Patent #:	10340180	Issue Dt:	07/02/2019	Application #:	15872314	Filing Dt:	01/16/2018
Publication #:	US20190221474	Pub Dt:	07/18/2019
Title:	MERGE MANDREL FEATURES

Patent #:	10707108	Issue Dt:	07/07/2020	Application #:	15872335	Filing Dt:	01/16/2018
Publication #:	US20180138064	Pub Dt:	05/17/2018
Title:	WAFER CARRIER PURGE APPARATUSES, AUTOMATED MECHANICAL HANDLING SYSTEMS INCLUDING THE SAME, AND METHODS OF HANDLING A WAFER CARRIER DURING INTEGRATED CIRCUIT FABRICATION

Patent #:	10446483	Issue Dt:	10/15/2019	Application #:	15872589	Filing Dt:	01/16/2018
Publication #:	US20190221515	Pub Dt:	07/18/2019
Title:	METAL-INSULATOR-METAL CAPACITORS WITH ENLARGED CONTACT AREAS

Patent #:	10121788	Issue Dt:	11/06/2018	Application #:	15873006	Filing Dt:	01/17/2018
Publication #:	US20180323191	Pub Dt:	11/08/2018
Title:	FIN-TYPE FIELD EFFECT TRANSISTORS WITH SINGLE-DIFFUSION BREAKS AND METHOD

Patent #:	10217846	Issue Dt:	02/26/2019	Application #:	15873156	Filing Dt:	01/17/2018
Title:	VERTICAL FIELD EFFECT TRANSISTOR FORMATION WITH CRITICAL DIMENSION CONTROL

Patent #:	10552567	Issue Dt:	02/04/2020	Application #:	15873225	Filing Dt:	01/17/2018
Publication #:	US20190220567	Pub Dt:	07/18/2019
Title:	AUTOMATED REDESIGN OF INTEGRATED CIRCUITS USING RELAXED SPACING RULES

Patent #:	10580875	Issue Dt:	03/03/2020	Application #:	15873565	Filing Dt:	01/17/2018
Publication #:	US20190221650	Pub Dt:	07/18/2019
Title:	MIDDLE OF LINE STRUCTURES

Patent #:	10158021	Issue Dt:	12/18/2018	Application #:	15873935	Filing Dt:	01/18/2018
Publication #:	US20180226503	Pub Dt:	08/09/2018
Title:	VERTICAL PILLAR-TYPE FIELD EFFECT TRANSISTOR AND METHOD

Patent #:	10741495	Issue Dt:	08/11/2020	Application #:	15873946	Filing Dt:	01/18/2018
Publication #:	US20190221523	Pub Dt:	07/18/2019
Title:	STRUCTURE AND METHOD TO REDUCE SHORTS AND CONTACT RESISTANCE IN SEMICONDUCTOR DEVICES

Patent #:	10564554	Issue Dt:	02/18/2020	Application #:	15874039	Filing Dt:	01/18/2018
Publication #:	US20190219933	Pub Dt:	07/18/2019
Title:	SYSTEM AND METHOD FOR ANALYZING PRINTED MASKS FOR LITHOGRAPHY BASED ON REPRESENTATIVE CONTOURS

Patent #:	10409006	Issue Dt:	09/10/2019	Application #:	15874210	Filing Dt:	01/18/2018
Publication #:	US20180164508	Pub Dt:	06/14/2018
Title:	PHOTONICS CHIP

Patent #:	10269932	Issue Dt:	04/23/2019	Application #:	15874341	Filing Dt:	01/18/2018
Title:	ASYMMETRIC FORMATION OF EPI SEMICONDUCTOR MATERIAL IN SOURCE/DRAIN REGIONS OF FINFET DEVICES

Patent #:	10431665	Issue Dt:	10/01/2019	Application #:	15875055	Filing Dt:	01/19/2018
Publication #:	US20180151690	Pub Dt:	05/31/2018
Title:	MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS

Patent #:	10468481	Issue Dt:	11/05/2019	Application #:	15875132	Filing Dt:	01/19/2018
Publication #:	US20190229183	Pub Dt:	07/25/2019
Title:	SELF-ALIGNED SINGLE DIFFUSION BREAK ISOLATION WITH REDUCTION OF STRAIN LOSS

Patent #:	10199264	Issue Dt:	02/05/2019	Application #:	15875212	Filing Dt:	01/19/2018
Publication #:	US20180151504	Pub Dt:	05/31/2018
Title:	SELF ALIGNED INTERCONNECT STRUCTURES

Patent #:	10325913	Issue Dt:	06/18/2019	Application #:	15875609	Filing Dt:	01/19/2018
Publication #:	US20180145079	Pub Dt:	05/24/2018
Title:	METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES

Patent #:	10243053	Issue Dt:	03/26/2019	Application #:	15876316	Filing Dt:	01/22/2018
Title:	GATE CONTACT STRUCTURE POSITIONED ABOVE AN ACTIVE REGION OF A TRANSISTOR DEVICE

Patent #:	10559470	Issue Dt:	02/11/2020	Application #:	15876407	Filing Dt:	01/22/2018
Publication #:	US20190228976	Pub Dt:	07/25/2019
Title:	CAPPING STRUCTURE

Patent #:	10242895	Issue Dt:	03/26/2019	Application #:	15876472	Filing Dt:	01/22/2018
Publication #:	US20180143077	Pub Dt:	05/24/2018
Title:	SELF-CONTAINED METROLOGY WAFER CARRIER SYSTEMS

Patent #:	10720494	Issue Dt:	07/21/2020	Application #:	15876530	Filing Dt:	01/22/2018
Publication #:	US20190229184	Pub Dt:	07/25/2019
Title:	FIELD-EFFECT TRANSISTORS WITH AIRGAPS

Patent #:	10768521	Issue Dt:	09/08/2020	Application #:	15876540	Filing Dt:	01/22/2018
Publication #:	US20190227427	Pub Dt:	07/25/2019
Title:	EXTREME ULTRAVIOLET (EUV) MASK ABSORBER AND METHOD FOR FORMING THE SAME

Patent #:	10263099	Issue Dt:	04/16/2019	Application #:	15876606	Filing Dt:	01/22/2018
Publication #:	US20180158931	Pub Dt:	06/07/2018
Title:	SELF-ALIGNED FINFET FORMATION

Patent #:	10446643	Issue Dt:	10/15/2019	Application #:	15876727	Filing Dt:	01/22/2018
Publication #:	US20190229185	Pub Dt:	07/25/2019
Title:	SEALED CAVITY STRUCTURES WITH A PLANAR SURFACE

Patent #:	10566300	Issue Dt:	02/18/2020	Application #:	15876734	Filing Dt:	01/22/2018
Publication #:	US20190229079	Pub Dt:	07/25/2019
Title:	BOND PADS WITH SURROUNDING FILL LINES

Patent #:	10446443	Issue Dt:	10/15/2019	Application #:	15877549	Filing Dt:	01/23/2018
Publication #:	US20180158733	Pub Dt:	06/07/2018
Title:	INTEGRATED CIURCUIT PRODUCT HAVING A THROUGH-SUBSTRATE-VIA (TSV) AND A METALLIZATION LAYER THAT ARE FORMED AFTER FORMATION OF A SEMICONDUCTOR DEVICE

Patent #:	10746925	Issue Dt:	08/18/2020	Application #:	15878025	Filing Dt:	01/23/2018
Publication #:	US20190227229	Pub Dt:	07/25/2019
Title:	SILICON NITRIDE GRATING COUPLERS

Patent #:	10510613	Issue Dt:	12/17/2019	Application #:	15878081	Filing Dt:	01/23/2018
Publication #:	US20190229019	Pub Dt:	07/25/2019
Title:	CONTACT STRUCTURES

Patent #:	10361293	Issue Dt:	07/23/2019	Application #:	15878478	Filing Dt:	01/24/2018
Publication #:	US20190229207	Pub Dt:	07/25/2019
Title:	VERTICAL FIN-TYPE DEVICES AND METHODS

Patent #:	10074564	Issue Dt:	09/11/2018	Application #:	15878486	Filing Dt:	01/24/2018
Publication #:	US20180166335	Pub Dt:	06/14/2018
Title:	SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS

Patent #:	10211045	Issue Dt:	02/19/2019	Application #:	15878502	Filing Dt:	01/24/2018
Title:	MICROWAVE ANNEALING OF FLOWABLE OXIDES WITH TRAP LAYERS

Patent #:	10332747	Issue Dt:	06/25/2019	Application #:	15878519	Filing Dt:	01/24/2018
Title:	SELECTIVE TITANIUM NITRIDE DEPOSITION USING OXIDES OF LANTHANUM MASKS

Patent #:	10332977	Issue Dt:	06/25/2019	Application #:	15880059	Filing Dt:	01/25/2018
Publication #:	US20180151433	Pub Dt:	05/31/2018
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	10147496	Issue Dt:	12/04/2018	Application #:	15881356	Filing Dt:	01/26/2018
Publication #:	US20180151238	Pub Dt:	05/31/2018
Title:	NOVEL OTPROM FOR POST-PROCESS PROGRAMMING USING SELECTIVE BREAKDOWN

Patent #:	10332963	Issue Dt:	06/25/2019	Application #:	15882031	Filing Dt:	01/29/2018
Title:	UNIFORMITY TUNING OF VARIABLE-HEIGHT FEATURES FORMED IN TRENCHES

Patent #:	10388631	Issue Dt:	08/20/2019	Application #:	15882036	Filing Dt:	01/29/2018
Publication #:	US20190237430	Pub Dt:	08/01/2019
Title:	3D IC PACKAGE WITH RDL INTERPOSER AND RELATED METHOD

Patent #:	10727327	Issue Dt:	07/28/2020	Application #:	15882053	Filing Dt:	01/29/2018
Publication #:	US20190237568	Pub Dt:	08/01/2019
Title:	SILICON CONTROLLED RECTIFIERS INTEGRATED INTO A HETEROJUNCTION BIPOLAR TRANSISTOR PROCESS

Patent #:	10460986	Issue Dt:	10/29/2019	Application #:	15882291	Filing Dt:	01/29/2018
Publication #:	US20190237363	Pub Dt:	08/01/2019
Title:	CAP STRUCTURE

Patent #:	10224286	Issue Dt:	03/05/2019	Application #:	15883693	Filing Dt:	01/30/2018
Title:	INTERCONNECT STRUCTURE WITH ADHESIVE DIELECTRIC LAYER AND METHODS OF FORMING SAME

Patent #:	10529728	Issue Dt:	01/07/2020	Application #:	15883975	Filing Dt:	01/30/2018
Publication #:	US20180158833	Pub Dt:	06/07/2018
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF PAIRS OF NONVOLATILE MEMORY CELLS AND AN EDGE CELL

Patent #:	11069809	Issue Dt:	07/20/2021	Application #:	15884045	Filing Dt:	01/30/2018
Publication #:	US20180175197	Pub Dt:	06/21/2018
Title:	SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION

Patent #:	10469041	Issue Dt:	11/05/2019	Application #:	15886475	Filing Dt:	02/01/2018
Publication #:	US20190238105	Pub Dt:	08/01/2019
Title:	GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME

Patent #:	10403772	Issue Dt:	09/03/2019	Application #:	15886927	Filing Dt:	02/02/2018
Publication #:	US20180158967	Pub Dt:	06/07/2018
Title:	ELECTRICAL AND OPTICAL VIA CONNECTIONS ON A SAME CHIP

Patent #:	NONE	Issue Dt:		Application #:	15887357	Filing Dt:	02/02/2018
Publication #:	US20190242938	Pub Dt:	08/08/2019
Title:	METHODS OF BANDGAP ANALYSIS AND MODELING FOR HIGH K METAL GATE

Patent #:	10386406	Issue Dt:	08/20/2019	Application #:	15887417	Filing Dt:	02/02/2018
Publication #:	US20190242939	Pub Dt:	08/08/2019
Title:	BACK GATE TUNING CIRCUITS

Patent #:	10475921	Issue Dt:	11/12/2019	Application #:	15888195	Filing Dt:	02/05/2018
Publication #:	US20190245080	Pub Dt:	08/08/2019
Title:	LATERALLY DIFFUSED FIELD EFFECT TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME

Patent #:	10510675	Issue Dt:	12/17/2019	Application #:	15888366	Filing Dt:	02/05/2018
Publication #:	US20190244911	Pub Dt:	08/08/2019
Title:	SUBSTRATE STRUCTURE WITH SPATIAL ARRANGEMENT CONFIGURED FOR COUPLING OF SURFACE PLASMONS TO INCIDENT LIGHT

Patent #:	10192867	Issue Dt:	01/29/2019	Application #:	15888401	Filing Dt:	02/05/2018
Title:	COMPLEMENTARY FETs WITH WRAP AROUND CONTACTS AND METHOD OF FORMING SAME

Patent #:	10153209	Issue Dt:	12/11/2018	Application #:	15888408	Filing Dt:	02/05/2018
Title:	INSULATING GATE SEPARATION STRUCTURE AND METHODS OF MAKING SAME

Patent #:	10340359	Issue Dt:	07/02/2019	Application #:	15889321	Filing Dt:	02/06/2018
Publication #:	US20180175155	Pub Dt:	06/21/2018
Title:	GATE STRUCTURE WITH DUAL WIDTH ELECTRODE LAYER

Patent #:	10164099	Issue Dt:	12/25/2018	Application #:	15889367	Filing Dt:	02/06/2018
Publication #:	US20180175198	Pub Dt:	06/21/2018
Title:	DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION

Patent #:	10515679	Issue Dt:	12/24/2019	Application #:	15889369	Filing Dt:	02/06/2018
Publication #:	US20190244650	Pub Dt:	08/08/2019
Title:	MAGNETO-RESISTIVE MEMORY STRUCTURES WITH IMPROVED SENSING, AND ASSOCIATED SENSING METHODS

Patent #:	10403622	Issue Dt:	09/03/2019	Application #:	15889635	Filing Dt:	02/06/2018
Publication #:	US20190244954	Pub Dt:	08/08/2019
Title:	ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHODS

Patent #:	10217672	Issue Dt:	02/26/2019	Application #:	15889654	Filing Dt:	02/06/2018
Publication #:	US20180240715	Pub Dt:	08/23/2018
Title:	VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS

Patent #:	10204797	Issue Dt:	02/12/2019	Application #:	15890210	Filing Dt:	02/06/2018
Title:	METHODS, APPARATUS, AND SYSTEM FOR REDUCING STEP HEIGHT DIFFERENCE IN SEMICONDUCTOR DEVICES

Patent #:	10269654	Issue Dt:	04/23/2019	Application #:	15890246	Filing Dt:	02/06/2018
Title:	METHODS. APPARATUS AND SYSTEM FOR REPLACEMENT CONTACT FOR A FINFET DEVICE

Patent #:	10705121	Issue Dt:	07/07/2020	Application #:	15890270	Filing Dt:	02/06/2018
Publication #:	US20190242927	Pub Dt:	08/08/2019
Title:	PROBE CARD CONTINUITY TESTING AND CLEANING FIXTURE COMPRISING HIGHLY PURIFIED TUNGSTEN

Patent #:	10056369	Issue Dt:	08/21/2018	Application #:	15890452	Filing Dt:	02/07/2018
Publication #:	US20180240796	Pub Dt:	08/23/2018
Title:	SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME

Patent #:	10395939	Issue Dt:	08/27/2019	Application #:	15890859	Filing Dt:	02/07/2018
Publication #:	US20180174855	Pub Dt:	06/21/2018
Title:	METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME

Patent #:	10256304	Issue Dt:	04/09/2019	Application #:	15890880	Filing Dt:	02/07/2018
Publication #:	US20180175202	Pub Dt:	06/21/2018
Title:	HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS

Patent #:	10381069	Issue Dt:	08/13/2019	Application #:	15891619	Filing Dt:	02/08/2018
Publication #:	US20190244658	Pub Dt:	08/08/2019
Title:	WRITE ASSIST

Patent #:	10490501	Issue Dt:	11/26/2019	Application #:	15893193	Filing Dt:	02/09/2018
Publication #:	US20180166385	Pub Dt:	06/14/2018
Title:	METHOD TO FORM INTERCONNECT STRUCTURE WITH TUNGSTEN FILL

Patent #:	10256235	Issue Dt:	04/09/2019	Application #:	15893860	Filing Dt:	02/12/2018
Publication #:	US20180175025	Pub Dt:	06/21/2018
Title:	VERTICAL TRANSISTORS AND METHODS OF FORMING SAME

Patent #:	10497703	Issue Dt:	12/03/2019	Application #:	15894785	Filing Dt:	02/12/2018
Publication #:	US20180175037	Pub Dt:	06/21/2018
Title:	METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH SILICON AND SILICON GERMANIUM FINS

Patent #:	10177163	Issue Dt:	01/08/2019	Application #:	15895053	Filing Dt:	02/13/2018
Title:	SOI-BASED FLOATING GATE MEMORY CELL

Patent #:	10504798	Issue Dt:	12/10/2019	Application #:	15897204	Filing Dt:	02/15/2018
Publication #:	US20190252268	Pub Dt:	08/15/2019
Title:	GATE CUT IN REPLACEMENT METAL GATE PROCESS

Patent #:	10741497	Issue Dt:	08/11/2020	Application #:	15897416	Filing Dt:	02/15/2018
Publication #:	US20190252320	Pub Dt:	08/15/2019
Title:	CONTACT AND INTERCONNECT STRUCTURES

Patent #:	10707330	Issue Dt:	07/07/2020	Application #:	15897570	Filing Dt:	02/15/2018
Publication #:	US20190252522	Pub Dt:	08/15/2019
Title:	SEMICONDUCTOR DEVICE WITH INTERCONNECT TO SOURCE/DRAIN

Patent #:	10276700	Issue Dt:	04/30/2019	Application #:	15897820	Filing Dt:	02/15/2018
Publication #:	US20180175179	Pub Dt:	06/21/2018
Title:	SYMMETRICAL LATERAL BIPOLAR JUNCTION TRANSISTOR AND USE OF SAME IN CHARACTERIZING AND PROTECTING TRANSISTORS

Patent #:	10411069	Issue Dt:	09/10/2019	Application #:	15898547	Filing Dt:	02/17/2018
Publication #:	US20190259808	Pub Dt:	08/22/2019
Title:	INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES AND METHODS FOR FABRICATING THE SAME

Patent #:	10381406	Issue Dt:	08/13/2019	Application #:	15898555	Filing Dt:	02/17/2018
Publication #:	US20190259809	Pub Dt:	08/22/2019
Title:	INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES HAVING REDUCED SWITCHING ENERGY BARRIERS FOR DUAL BIT OPERATION AND METHODS FOR FABRICATING THE SAME

Patent #:	10468456	Issue Dt:	11/05/2019	Application #:	15898562	Filing Dt:	02/17/2018
Publication #:	US20190259810	Pub Dt:	08/22/2019
Title:	INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES HAVING REDUCED SWITCHING ENERGY BARRIERS FOR DIFFERENTIAL BIT OPERATION AND METHODS FOR FABRICATING THE SAME

Patent #:	10607893	Issue Dt:	03/31/2020	Application #:	15898569	Filing Dt:	02/17/2018
Publication #:	US20190259667	Pub Dt:	08/22/2019
Title:	MIDDLE OF LINE STRUCTURES

Patent #:	10566291	Issue Dt:	02/18/2020	Application #:	15898606	Filing Dt:	02/18/2018
Publication #:	US20190259708	Pub Dt:	08/22/2019
Title:	MARK STRUCTURE FOR ALIGNING LAYERS OF INTEGRATED CIRCUIT STRUCTURE AND METHODS OF FORMING SAME

Patent #:	10304833	Issue Dt:	05/28/2019	Application #:	15898812	Filing Dt:	02/19/2018
Title:	METHOD OF FORMING COMPLEMENTARY NANO-SHEET/WIRE TRANSISTOR DEVICES WITH SAME DEPTH CONTACTS

Patent #:	10283560	Issue Dt:	05/07/2019	Application #:	15899374	Filing Dt:	02/20/2018
Publication #:	US20180175107	Pub Dt:	06/21/2018
Title:	LIGHT EMITTING DIODES (LEDs) WITH INTEGRATED CMOS CIRCUITS

Patent #:	10916478	Issue Dt:	02/09/2021	Application #:	15899508	Filing Dt:	02/20/2018
Publication #:	US20190259670	Pub Dt:	08/22/2019
Title:	METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES

Patent #:	10236256	Issue Dt:	03/19/2019	Application #:	15899685	Filing Dt:	02/20/2018
Publication #:	US20180301413	Pub Dt:	10/18/2018
Title:	PRE-SPACER SELF-ALIGNED CUT FORMATION

Patent #:	10832966	Issue Dt:	11/10/2020	Application #:	15899986	Filing Dt:	02/20/2018
Publication #:	US20190259668	Pub Dt:	08/22/2019
Title:	METHODS AND STRUCTURES FOR A GATE CUT

Patent #:	10236218	Issue Dt:	03/19/2019	Application #:	15900264	Filing Dt:	02/20/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR FORMING WRAP-AROUND CONTACT WITH DUAL SILICIDE

Patent #:	10395980	Issue Dt:	08/27/2019	Application #:	15901411	Filing Dt:	02/21/2018
Publication #:	US20190259649	Pub Dt:	08/22/2019
Title:	DUAL AIRGAP STRUCTURE

Patent #:	10374064	Issue Dt:	08/06/2019	Application #:	15901447	Filing Dt:	02/21/2018
Publication #:	US20180182867	Pub Dt:	06/28/2018
Title:	FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING

Patent #:	10199429	Issue Dt:	02/05/2019	Application #:	15901850	Filing Dt:	02/21/2018
Publication #:	US20180197913	Pub Dt:	07/12/2018
Title:	LEDs WITH THREE COLOR RGB PIXELS FOR DISPLAYS

Patent #:	10483205	Issue Dt:	11/19/2019	Application #:	15901979	Filing Dt:	02/22/2018
Publication #:	US20180182711	Pub Dt:	06/28/2018
Title:	CONTACT USING MULTILAYER LINER

Patent #:	10090330	Issue Dt:	10/02/2018	Application #:	15901997	Filing Dt:	02/22/2018
Publication #:	US20180182778	Pub Dt:	06/28/2018
Title:	STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION

Patent #:	10734233	Issue Dt:	08/04/2020	Application #:	15902098	Filing Dt:	02/22/2018
Publication #:	US20190259619	Pub Dt:	08/22/2019
Title:	FINFET WITH HIGH-K SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER

Patent #:	10580779	Issue Dt:	03/03/2020	Application #:	15903203	Filing Dt:	02/23/2018
Publication #:	US20190267387	Pub Dt:	08/29/2019
Title:	VERTICAL TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL

Patent #:	10566328	Issue Dt:	02/18/2020	Application #:	15904555	Filing Dt:	02/26/2018
Publication #:	US20190267371	Pub Dt:	08/29/2019
Title:	INTEGRATED CIRCUIT PRODUCTS WITH GATE STRUCTURES POSITIONED ABOVE ELEVATED ISOLATION STRUCTURES

Patent #:	10504851	Issue Dt:	12/10/2019	Application #:	15904853	Filing Dt:	02/26/2018
Publication #:	US20190267329	Pub Dt:	08/29/2019
Title:	STRUCTURE AND METHOD TO IMPROVE OVERLAY PERFORMANCE IN SEMICONDUCTOR DEVICES

Patent #:	10446665	Issue Dt:	10/15/2019	Application #:	15904982	Filing Dt:	02/26/2018
Publication #:	US20180190787	Pub Dt:	07/05/2018
Title:	METHOD AND STRUCTURE FOR PROTECTING GATES DURING EPITAXIAL GROWTH

100

Patent #:	10156676	Issue Dt:	12/18/2018	Application #:	15905134	Filing Dt:	02/26/2018
Title:	WAVEGUIDES WITH MULTIPLE AIRGAPS ARRANGED IN AND OVER A SILICON-ON-INSULATOR SUBSTRATE

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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