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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 80 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
10818659
Issue Dt:
10/27/2020
Application #:
16161294
Filing Dt:
10/16/2018
Publication #:
US20200119000
Pub Dt:
04/16/2020
Title:
FINFET HAVING UPPER SPACERS ADJACENT GATE AND SOURCE/DRAIN CONTACTS
2
Patent #:
10714422
Issue Dt:
07/14/2020
Application #:
16161590
Filing Dt:
10/16/2018
Publication #:
US20200118927
Pub Dt:
04/16/2020
Title:
ANTI-FUSE WITH SELF ALIGNED VIA PATTERNING
3
Patent #:
10811409
Issue Dt:
10/20/2020
Application #:
16161620
Filing Dt:
10/16/2018
Publication #:
US20200119001
Pub Dt:
04/16/2020
Title:
METHOD OF MANUFACTURING FINFET WITH REDUCED PARASITIC CAPACITANCE AND FINFET STRUCTURE FORMED THEREBY
4
Patent #:
10665590
Issue Dt:
05/26/2020
Application #:
16162373
Filing Dt:
10/16/2018
Publication #:
US20200119002
Pub Dt:
04/16/2020
Title:
WRAP-AROUND CONTACT SURROUNDING EPITAXIAL REGIONS OF INTEGRATED CIRCUIT STRUCTURES AND METHOD OF FORMING SAME
5
Patent #:
10692987
Issue Dt:
06/23/2020
Application #:
16164867
Filing Dt:
10/19/2018
Publication #:
US20200127109
Pub Dt:
04/23/2020
Title:
IC STRUCTURE WITH AIR GAP ADJACENT TO GATE STRUCTURE AND METHODS OF FORMING SAME
6
Patent #:
10698159
Issue Dt:
06/30/2020
Application #:
16165600
Filing Dt:
10/19/2018
Publication #:
US20200124796
Pub Dt:
04/23/2020
Title:
MULTIPLE-LAYER ARRANGEMENTS INCLUDING ONE OR MORE DIELECTRIC LAYERS OVER A WAVEGUIDE
7
Patent #:
10332969
Issue Dt:
06/25/2019
Application #:
16167081
Filing Dt:
10/22/2018
Publication #:
US20190115437
Pub Dt:
04/18/2019
Title:
NEGATIVE CAPACITANCE MATCHING IN GATE ELECTRODE STRUCTURES
8
Patent #:
10727108
Issue Dt:
07/28/2020
Application #:
16168414
Filing Dt:
10/23/2018
Publication #:
US20200127013
Pub Dt:
04/23/2020
Title:
DUMMY GATE ISOLATION AND METHOD OF PRODUCTION THEREOF
9
Patent #:
10580701
Issue Dt:
03/03/2020
Application #:
16168441
Filing Dt:
10/23/2018
Title:
METHODS OF MAKING A SELF-ALIGNED GATE CONTACT STRUCTURE AND SOURCE/DRAIN METALLIZATION STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS
10
Patent #:
10644099
Issue Dt:
05/05/2020
Application #:
16168951
Filing Dt:
10/24/2018
Publication #:
US20200135845
Pub Dt:
04/30/2020
Title:
THREE-DIMENSIONAL (3D) METAL-INSULATOR-METAL CAPACITOR (MIMCAP) AND METHOD
11
Patent #:
10892338
Issue Dt:
01/12/2021
Application #:
16169269
Filing Dt:
10/24/2018
Publication #:
US20200135872
Pub Dt:
04/30/2020
Title:
SCALED GATE CONTACT AND SOURCE/DRAIN CAP
12
Patent #:
10797049
Issue Dt:
10/06/2020
Application #:
16170117
Filing Dt:
10/25/2018
Publication #:
US20200135723
Pub Dt:
04/30/2020
Title:
FINFET STRUCTURE WITH DIELECTRIC BAR CONTAINING GATE TO REDUCE EFFECTIVE CAPACITANCE, AND METHOD OF FORMING SAME
13
Patent #:
10444433
Issue Dt:
10/15/2019
Application #:
16170262
Filing Dt:
10/25/2018
Title:
WAVEGUIDES INCLUDING A PATTERNED DIELECTRIC LAYER
14
Patent #:
10714380
Issue Dt:
07/14/2020
Application #:
16171477
Filing Dt:
10/26/2018
Publication #:
US20200135545
Pub Dt:
04/30/2020
Title:
METHOD OF FORMING SMOOTH SIDEWALL STRUCTURES USING SPACER MATERIALS
15
Patent #:
10692852
Issue Dt:
06/23/2020
Application #:
16171760
Filing Dt:
10/26/2018
Publication #:
US20200135715
Pub Dt:
04/30/2020
Title:
SILICON-CONTROLLED RECTIFIERS WITH WELLS LATERALLY ISOLATED BY TRENCH ISOLATION REGIONS
16
Patent #:
10644149
Issue Dt:
05/05/2020
Application #:
16172109
Filing Dt:
10/26/2018
Publication #:
US20200135917
Pub Dt:
04/30/2020
Title:
LDMOS FIN-TYPE FIELD-EFFECT TRANSISTORS INCLUDING A DUMMY GATE
17
Patent #:
10411752
Issue Dt:
09/10/2019
Application #:
16174145
Filing Dt:
10/29/2018
Title:
METHODS, APPARATUS, AND SYSTEM FOR HIGH-BANDWIDTH ON-MOLD ANTENNAS
18
Patent #:
10566201
Issue Dt:
02/18/2020
Application #:
16174510
Filing Dt:
10/30/2018
Title:
GATE CUT METHOD AFTER SOURCE/DRAIN METALLIZATION
19
Patent #:
10636872
Issue Dt:
04/28/2020
Application #:
16176380
Filing Dt:
10/31/2018
Publication #:
US20200135856
Pub Dt:
04/30/2020
Title:
APPARATUS AND METHOD TO PREVENT INTEGRATED CIRCUIT FROM ENTERING LATCH-UP MODE
20
Patent #:
10832944
Issue Dt:
11/10/2020
Application #:
16177854
Filing Dt:
11/01/2018
Publication #:
US20200144106
Pub Dt:
05/07/2020
Title:
INTERCONNECT STRUCTURE HAVING REDUCED RESISTANCE VARIATION AND METHOD OF FORMING SAME
21
Patent #:
10833183
Issue Dt:
11/10/2020
Application #:
16177877
Filing Dt:
11/01/2018
Publication #:
US20200144404
Pub Dt:
05/07/2020
Title:
INTERLAYER BALLISTIC TRANSPORT SEMICONDUCTOR DEVICES
22
Patent #:
10756184
Issue Dt:
08/25/2020
Application #:
16180486
Filing Dt:
11/05/2018
Publication #:
US20200144365
Pub Dt:
05/07/2020
Title:
FACETED EPITAXIAL SOURCE/DRAIN REGIONS
23
Patent #:
10466514
Issue Dt:
11/05/2019
Application #:
16181879
Filing Dt:
11/06/2018
Title:
ELECTRO-OPTIC MODULATOR WITH VERTICALLY-ARRANGED OPTICAL PATHS
24
Patent #:
11333558
Issue Dt:
05/17/2022
Application #:
16181972
Filing Dt:
11/06/2018
Publication #:
US20200141810
Pub Dt:
05/07/2020
Title:
BOOLEAN TEMPERATURE SENSING USING PHASE TRANSITION MATERIAL
25
Patent #:
10658505
Issue Dt:
05/19/2020
Application #:
16182692
Filing Dt:
11/07/2018
Publication #:
US20200144414
Pub Dt:
05/07/2020
Title:
HIGH VOLTAGE DEVICE AND A METHOD FOR FORMING THE HIGH VOLTAGE DEVICE
26
Patent #:
11380581
Issue Dt:
07/05/2022
Application #:
16185015
Filing Dt:
11/09/2018
Publication #:
US20200152512
Pub Dt:
05/14/2020
Title:
INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICES HAVING A VIA STRUCTURE THROUGH AN UPPER CONDUCTIVE LINE
27
Patent #:
10727136
Issue Dt:
07/28/2020
Application #:
16185675
Filing Dt:
11/09/2018
Publication #:
US20200152518
Pub Dt:
05/14/2020
Title:
INTEGRATED GATE CONTACT AND CROSS-COUPLING CONTACT FORMATION
28
Patent #:
10790204
Issue Dt:
09/29/2020
Application #:
16185696
Filing Dt:
11/09/2018
Publication #:
US20200152530
Pub Dt:
05/14/2020
Title:
TEST STRUCTURE LEVERAGING THE LOWEST METALLIZATION LEVEL OF AN INTERCONNECT STRUCTURE
29
Patent #:
10679894
Issue Dt:
06/09/2020
Application #:
16185799
Filing Dt:
11/09/2018
Publication #:
US20200152504
Pub Dt:
05/14/2020
Title:
AIRGAP SPACERS FORMED IN CONJUNCTION WITH A LATE GATE CUT
30
Patent #:
10714567
Issue Dt:
07/14/2020
Application #:
16185881
Filing Dt:
11/09/2018
Publication #:
US20200152734
Pub Dt:
05/14/2020
Title:
NANOSHEET FIELD-EFFECT TRANSISTOR WITH SUBSTRATE ISOLATION
31
Patent #:
10424584
Issue Dt:
09/24/2019
Application #:
16186781
Filing Dt:
11/12/2018
Publication #:
US20190198503
Pub Dt:
06/27/2019
Title:
SEMICONDUCTOR MEMORY DEVICES HAVING AN UNDERCUT SOURCE/DRAIN REGION
32
Patent #:
10971583
Issue Dt:
04/06/2021
Application #:
16188408
Filing Dt:
11/13/2018
Publication #:
US20200152736
Pub Dt:
05/14/2020
Title:
GATE CUT ISOLATION INCLUDING AIR GAP, INTEGRATED CIRCUIT INCLUDING SAME AND RELATED METHOD
33
Patent #:
10635007
Issue Dt:
04/28/2020
Application #:
16188814
Filing Dt:
11/13/2018
Publication #:
US20200152498
Pub Dt:
05/14/2020
Title:
APPARATUS AND METHOD FOR ALIGNING INTEGRATED CIRCUIT LAYERS USING MULTIPLE GRATING MATERIALS
34
Patent #:
10429581
Issue Dt:
10/01/2019
Application #:
16189125
Filing Dt:
11/13/2018
Title:
POLARIZATION SPLITTERS BASED ON STACKED WAVEGUIDES
35
Patent #:
10475899
Issue Dt:
11/12/2019
Application #:
16190549
Filing Dt:
11/14/2018
Publication #:
US20190123160
Pub Dt:
04/25/2019
Title:
METHOD OF FORMING GATE-ALL-AROUND (GAA) FINFET AND GAA FINFET FORMED THEREBY
36
Patent #:
10505545
Issue Dt:
12/10/2019
Application #:
16190922
Filing Dt:
11/14/2018
Title:
SIMPLIFIED BIAS SCHEME FOR DIGITAL DESIGNS
37
Patent #:
11061315
Issue Dt:
07/13/2021
Application #:
16191589
Filing Dt:
11/15/2018
Publication #:
US20200159105
Pub Dt:
05/21/2020
Title:
HYBRID OPTICAL AND EUV LITHOGRAPHY
38
Patent #:
10643927
Issue Dt:
05/05/2020
Application #:
16192999
Filing Dt:
11/16/2018
Publication #:
US20200161218
Pub Dt:
05/21/2020
Title:
RING ISOLATED THROUGH-SUBSTRATE VIAS FOR HIGH RESISTIVITY SUBSTRATES
39
Patent #:
10755918
Issue Dt:
08/25/2020
Application #:
16193313
Filing Dt:
11/16/2018
Publication #:
US20200161122
Pub Dt:
05/21/2020
Title:
SPACER WITH LAMINATE LINER
40
Patent #:
10685840
Issue Dt:
06/16/2020
Application #:
16193960
Filing Dt:
11/16/2018
Publication #:
US20200161136
Pub Dt:
05/21/2020
Title:
GATE STRUCTURES
41
Patent #:
10707206
Issue Dt:
07/07/2020
Application #:
16194691
Filing Dt:
11/19/2018
Publication #:
US20200161296
Pub Dt:
05/21/2020
Title:
GATE CUT ISOLATION FORMED AS LAYER AGAINST SIDEWALL OF DUMMY GATE MANDREL
42
Patent #:
10557989
Issue Dt:
02/11/2020
Application #:
16194902
Filing Dt:
11/19/2018
Title:
SLOT ASSISTED GRATING BASED TRANSVERSE MAGNETIC (TM) TRANSMISSION MODE PASS POLARIZER
43
Patent #:
10811422
Issue Dt:
10/20/2020
Application #:
16196060
Filing Dt:
11/20/2018
Publication #:
US20200161315
Pub Dt:
05/21/2020
Title:
SEMICONDUCTOR RECESS TO EPITAXIAL REGIONS AND RELATED INTEGRATED CIRCUIT STRUCTURE
44
Patent #:
10775826
Issue Dt:
09/15/2020
Application #:
16196183
Filing Dt:
11/20/2018
Publication #:
US20200159270
Pub Dt:
05/21/2020
Title:
BACK-GATE BIASING VOLTAGE DIVIDER TOPOLOGY CIRCUIT STRUCTURE
45
Patent #:
10825741
Issue Dt:
11/03/2020
Application #:
16196413
Filing Dt:
11/20/2018
Publication #:
US20200161190
Pub Dt:
05/21/2020
Title:
METHODS OF FORMING SINGLE DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS
46
Patent #:
10784976
Issue Dt:
09/22/2020
Application #:
16196970
Filing Dt:
11/20/2018
Publication #:
US20200162179
Pub Dt:
05/21/2020
Title:
NANOSECOND ACCURACY OF TIMESTAMPING BY LEVERAGING ALIGNMENT MARKER AND METHOD FOR PRODUCING THE SAME
47
Patent #:
11315870
Issue Dt:
04/26/2022
Application #:
16197646
Filing Dt:
11/21/2018
Publication #:
US20200161236
Pub Dt:
05/21/2020
Title:
TOP ELECTRODE INTERCONNECT STRUCTURES
48
Patent #:
11061186
Issue Dt:
07/13/2021
Application #:
16199468
Filing Dt:
11/26/2018
Publication #:
US20200166702
Pub Dt:
05/28/2020
Title:
WAVEGUIDE STRUCTURES
49
Patent #:
10585245
Issue Dt:
03/10/2020
Application #:
16199727
Filing Dt:
11/26/2018
Title:
MULTIPLE-LAYER ARRANGEMENTS USING TUNABLE MATERIALS TO PROVIDE SWITCHABLE OPTICAL COMPONENTS
50
Patent #:
10895689
Issue Dt:
01/19/2021
Application #:
16199811
Filing Dt:
11/26/2018
Publication #:
US20200166709
Pub Dt:
05/28/2020
Title:
SWITCHABLE AND RECONFIGURABLE GRATING COUPLERS
51
Patent #:
10699957
Issue Dt:
06/30/2020
Application #:
16201449
Filing Dt:
11/27/2018
Publication #:
US20200168509
Pub Dt:
05/28/2020
Title:
LATE GATE CUT USING SELECTIVE DIELECTRIC DEPOSITION
52
Patent #:
10712499
Issue Dt:
07/14/2020
Application #:
16202037
Filing Dt:
11/27/2018
Publication #:
US20200166704
Pub Dt:
05/28/2020
Title:
SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME
53
Patent #:
10923397
Issue Dt:
02/16/2021
Application #:
16203619
Filing Dt:
11/29/2018
Publication #:
US20200176312
Pub Dt:
06/04/2020
Title:
THROUGH-SUBSTRATE VIA STRUCTURES IN SEMICONDUCTOR DEVICES
54
Patent #:
10566202
Issue Dt:
02/18/2020
Application #:
16203623
Filing Dt:
11/29/2018
Title:
GATE STRUCTURES OF FINFET SEMICONDUCTOR DEVICES
55
Patent #:
10727067
Issue Dt:
07/28/2020
Application #:
16203816
Filing Dt:
11/29/2018
Publication #:
US20200176258
Pub Dt:
06/04/2020
Title:
LATE GATE CUT USING SELECTIVE CONDUCTOR DEPOSITION
56
Patent #:
10811319
Issue Dt:
10/20/2020
Application #:
16204482
Filing Dt:
11/29/2018
Publication #:
US20200176324
Pub Dt:
06/04/2020
Title:
MIDDLE OF LINE STRUCTURES
57
Patent #:
10651173
Issue Dt:
05/12/2020
Application #:
16204506
Filing Dt:
11/29/2018
Publication #:
US20200176444
Pub Dt:
06/04/2020
Title:
SINGLE DIFFUSION CUT FOR GATE STRUCTURES
58
Patent #:
10586581
Issue Dt:
03/10/2020
Application #:
16205921
Filing Dt:
11/30/2018
Title:
DYNAMIC BIPOLAR WRITE-ASSIST FOR NON-VOLATILE MEMORY ELEMENTS
59
Patent #:
10629694
Issue Dt:
04/21/2020
Application #:
16206231
Filing Dt:
11/30/2018
Title:
GATE CONTACT AND CROSS-COUPLING CONTACT FORMATION
60
Patent #:
11410872
Issue Dt:
08/09/2022
Application #:
16206375
Filing Dt:
11/30/2018
Publication #:
US20200176304
Pub Dt:
06/04/2020
Title:
OXIDIZED CAVITY STRUCTURES WITHIN AND UNDER SEMICONDUCTOR DEVICES
61
Patent #:
10727251
Issue Dt:
07/28/2020
Application #:
16207730
Filing Dt:
12/03/2018
Publication #:
US20200176456
Pub Dt:
06/04/2020
Title:
ROUNDED SHAPED TRANSISTORS FOR MEMORY DEVICES
62
Patent #:
10651281
Issue Dt:
05/12/2020
Application #:
16207915
Filing Dt:
12/03/2018
Publication #:
US20200176589
Pub Dt:
06/04/2020
Title:
SUBSTRATES WITH SELF-ALIGNED BURIED DIELECTRIC AND POLYCRYSTALLINE LAYERS
63
Patent #:
11127623
Issue Dt:
09/21/2021
Application #:
16213189
Filing Dt:
12/07/2018
Publication #:
US20200185266
Pub Dt:
06/11/2020
Title:
SINGLE DIFFUSION CUT FOR GATE STRUCTURES
64
Patent #:
10685951
Issue Dt:
06/16/2020
Application #:
16214450
Filing Dt:
12/10/2018
Publication #:
US20200185374
Pub Dt:
06/11/2020
Title:
WORDLINE STRAPPING FOR NON-VOLATILE MEMORY ELEMENTS
65
Patent #:
10509244
Issue Dt:
12/17/2019
Application #:
16216027
Filing Dt:
12/11/2018
Title:
OPTICAL SWITCHES AND ROUTERS OPERATED BY PHASE-CHANGING MATERIALS CONTROLLED BY HEATERS
66
Patent #:
10712498
Issue Dt:
07/14/2020
Application #:
16216321
Filing Dt:
12/11/2018
Publication #:
US20190121022
Pub Dt:
04/25/2019
Title:
SHIELDING STRUCTURES BETWEEN OPTICAL WAVEGUIDES
67
Patent #:
10914897
Issue Dt:
02/09/2021
Application #:
16217838
Filing Dt:
12/12/2018
Publication #:
US20200192033
Pub Dt:
06/18/2020
Title:
OPTICAL ON-WAFER PROBING WITH V-GROOVE COUPLERS
68
Patent #:
10832940
Issue Dt:
11/10/2020
Application #:
16218868
Filing Dt:
12/13/2018
Publication #:
US20190295881
Pub Dt:
09/26/2019
Title:
BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER
69
Patent #:
10685874
Issue Dt:
06/16/2020
Application #:
16220565
Filing Dt:
12/14/2018
Publication #:
US20200194306
Pub Dt:
06/18/2020
Title:
SELF-ALIGNED CUTS IN AN INTERCONNECT STRUCTURE
70
Patent #:
10664638
Issue Dt:
05/26/2020
Application #:
16221631
Filing Dt:
12/17/2018
Publication #:
US20200192987
Pub Dt:
06/18/2020
Title:
MEASURING COMPLEX STRUCTURES IN SEMICONDUCTOR FABRICATION
71
Patent #:
10733354
Issue Dt:
08/04/2020
Application #:
16225199
Filing Dt:
12/19/2018
Publication #:
US20200201955
Pub Dt:
06/25/2020
Title:
DESIGN SYSTEM AND METHOD EMPLOYING THREE-DIMENSIONAL (3D) EMULATION OF IN-KERF OPTICAL MACROS
72
Patent #:
10770338
Issue Dt:
09/08/2020
Application #:
16225540
Filing Dt:
12/19/2018
Publication #:
US20200203208
Pub Dt:
06/25/2020
Title:
SYSTEM COMPRISING A SINGLE WAFER, REDUCED VOLUME PROCESS CHAMBER
73
Patent #:
11049932
Issue Dt:
06/29/2021
Application #:
16226640
Filing Dt:
12/20/2018
Publication #:
US20200203478
Pub Dt:
06/25/2020
Title:
SEMICONDUCTOR ISOLATION STRUCTURES COMPRISING SHALLOW TRENCH AND DEEP TRENCH ISOLATION
74
Patent #:
10923594
Issue Dt:
02/16/2021
Application #:
16227059
Filing Dt:
12/20/2018
Publication #:
US20200203530
Pub Dt:
06/25/2020
Title:
METHODS TO REDUCE OR PREVENT STRAIN RELAXATION ON PFET DEVICES AND CORRESPONDING NOVEL IC PRODUCTS
75
Patent #:
10727236
Issue Dt:
07/28/2020
Application #:
16229600
Filing Dt:
12/21/2018
Publication #:
US20200203355
Pub Dt:
06/25/2020
Title:
CIRCUITS CONSTRUCTED FROM STACKED FIELD-EFFECT TRANSISTORS
76
Patent #:
10991796
Issue Dt:
04/27/2021
Application #:
16231671
Filing Dt:
12/24/2018
Publication #:
US20200203480
Pub Dt:
06/25/2020
Title:
SOURCE/DRAIN CONTACT DEPTH CONTROL
77
Patent #:
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Title:
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Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
10/22/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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