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02/23/2016
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13890776
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05/09/2013
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11/13/2014
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TEMPORARY LIQUID THERMAL INTERFACE MATERIAL FOR SURFACE TENSION ADHESION AND THERMAL CONTROL
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02/10/2015
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13890849
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05/09/2013
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11/13/2014
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STACKED CARBON-BASED FETS
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09/02/2014
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13891241
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05/10/2013
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01/12/2016
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05/10/2013
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11/13/2014
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MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES
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06/03/2014
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13891636
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05/10/2013
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09/19/2013
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FULLY-DEPLETED SON
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05/17/2016
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13891700
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05/10/2013
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11/13/2014
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FACILITATION OF SOCIAL INTERACTIONS
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06/30/2015
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13891725
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05/10/2013
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11/13/2014
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05/12/2015
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13891873
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05/10/2013
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11/13/2014
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05/06/2014
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13892265
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05/11/2013
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09/26/2013
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Metal Alloy Cap Integration
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08/12/2014
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13892801
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05/13/2013
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11/28/2013
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08/22/2017
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05/14/2013
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11/20/2014
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AUTOMATED GUIDANCE FOR SELECTING COMPONENTS OF AN IT SOLUTION
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03/03/2015
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13893483
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05/14/2013
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11/20/2014
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SOFTWARE VULNERABILITY NOTIFICATION VIA ICON DECORATIONS
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03/10/2015
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13893524
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05/14/2013
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11/20/2014
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DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME
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05/05/2015
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05/14/2013
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09/26/2013
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Determining Simulation Fidelity in a Self-Optimized Simulation of a Complex System
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12/23/2014
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05/14/2013
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11/20/2014
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FINFET DEVICE AND METHOD OF FABRICATION
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11/04/2014
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13893955
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05/14/2013
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11/20/2014
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METHODS OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENT INSULATION THICKNESSES ON THE SAME SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICES
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12/01/2015
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13894291
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05/14/2013
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11/20/2014
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ACCIDENTAL SHARED VOLUME ERASURE PREVENTION
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01/20/2015
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05/15/2013
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11/20/2014
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CONTACT FORMATION FOR ULTRA-SCALED DEVICES
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06/17/2014
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05/15/2013
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09/26/2013
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BORDERLESS CONTACTS FOR SEMICONDUCTOR DEVICES
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07/28/2015
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13894856
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05/15/2013
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11/20/2014
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DIRECT CURRENT GROUND FAULT INTERRUPTER
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05/10/2016
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05/15/2013
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11/20/2014
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FORMATION OF LARGE SCALE SINGLE CRYSTALLINE GRAPHENE
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06/16/2015
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05/15/2013
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11/20/2014
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SOLID STATE STORAGE MEDIA CARTRIDGE
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06/16/2015
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13895605
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05/16/2013
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11/20/2014
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ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY
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07/21/2015
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05/16/2013
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11/20/2014
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DETECT DRIVER PERSONA IN A VEHICLE
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09/29/2015
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05/16/2013
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11/20/2014
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11/04/2014
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05/17/2013
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11/20/2014
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03/31/2015
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05/17/2013
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11/20/2014
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06/02/2015
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05/20/2013
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11/20/2014
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ELEMENTAL SEMICONDUCTOR MATERIAL CONTACT FOR HIGH INDIUM CONTENT INGAN LIGHT EMITTING DIODES
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02/24/2015
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05/20/2013
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11/20/2014
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10/18/2016
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05/20/2013
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11/20/2014
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METADATA MANAGEMENT
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02/16/2016
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05/20/2013
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11/20/2014
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03/01/2016
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05/21/2013
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11/27/2014
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01/05/2016
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05/21/2013
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11/27/2014
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ELEMENTAL SEMICONDUCTOR MATERIAL CONTACTFOR HIGH ELECTRON MOBILITY TRANSISTOR
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04/07/2015
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05/21/2013
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11/28/2013
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SPIN LOGIC BASED ON PERSISTENT SPIN HELICES
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10/25/2016
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05/21/2013
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11/27/2014
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04/07/2015
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05/21/2013
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11/28/2013
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10/20/2015
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05/22/2013
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11/27/2014
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VALIDATION OF CACHE LOCKING USING INSTRUCTION FETCH AND EXECUTION
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09/16/2014
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05/22/2013
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03/29/2016
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05/22/2013
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11/27/2014
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07/21/2015
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05/22/2013
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11/27/2014
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11/24/2015
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13900605
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05/23/2013
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11/27/2014
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03/08/2016
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13900808
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05/23/2013
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11/27/2014
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07/21/2015
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05/23/2013
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11/27/2014
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BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES
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09/06/2016
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13900857
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05/23/2013
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11/27/2014
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METHOD OF RECONSTRUCTING ELECTRICAL PROBES
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03/08/2016
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05/23/2013
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11/27/2014
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RECOVERY FROM FAILURE OF PRIMARY STORAGE VOLUMES BY USING MIRRORED DATA MAINTAINED WITH HOST TIMESTAMPS
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01/17/2017
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13901108
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05/23/2013
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11/27/2014
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DETECTING SUDDEN CHANGES IN ACCELERATION IN SEMICONDUCTOR DEVICE OR SEMICONDUCTOR PACKAGING CONTAINING SEMICONDUCTOR DEVICE
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10/21/2014
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05/23/2013
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04/19/2016
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05/23/2013
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11/27/2014
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MAPPING A SOURCE WORKLOAD PATTERN FOR A SOURCE STORAGE SYSTEM TO A TARGET WORKLOAD PATTERN FOR A TARGET STORAGE SYSTEM
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10/27/2015
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13901739
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05/24/2013
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11/27/2014
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METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR STRUCTURE, A DEGAS PROCESS AND A PRECLEAN PROCESS
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05/12/2015
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05/24/2013
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10/03/2013
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07/22/2014
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05/24/2013
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09/26/2013
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01/19/2016
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05/24/2013
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11/27/2014
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01/26/2016
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05/24/2013
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11/27/2014
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09/29/2015
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05/24/2013
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11/27/2014
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FORMING MODIFIED CELL ARCHITECTURE FOR FINFET TECHNOLOGY AND RESULTING DEVICE
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12/22/2015
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05/24/2013
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11/27/2014
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INTEGRATED CIRCUITS WITH IMPROVED SOURCE/DRAIN CONTACTS AND METHODS FOR FABRICATING SUCH INTEGRATED CIRCUITS
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02/28/2017
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05/24/2013
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11/27/2014
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ASYMMETRIC FINFET SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
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02/17/2015
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05/28/2013
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12/04/2014
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02/09/2016
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05/28/2013
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12/04/2014
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12/02/2014
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05/28/2013
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Publication #:
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Pub Dt:
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12/04/2014
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Title:
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WAFER BONDING MISALIGNMENT REDUCTION
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Patent #:
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Issue Dt:
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11/10/2015
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Application #:
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13903199
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Filing Dt:
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05/28/2013
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Publication #:
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Pub Dt:
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12/04/2014
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Title:
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DECISION FEEDBACK EQUALIZER ('DFE') WITH A PLURALITY OF INDEPENDENTLY-CONTROLLED ISOLATED POWER DOMAINS
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Patent #:
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Issue Dt:
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01/13/2015
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Application #:
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13903283
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Filing Dt:
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05/28/2013
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Publication #:
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Pub Dt:
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12/04/2014
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Title:
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METHODS OF SELF-FORMING BARRIER INTEGRATION WITH PORE STUFFED ULK MATERIAL
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Patent #:
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Issue Dt:
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06/14/2016
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Application #:
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13903332
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Filing Dt:
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05/28/2013
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Publication #:
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Pub Dt:
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12/04/2014
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Title:
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POLICY ENFORCEMENT USING NATURAL LANGUAGE PROCESSING
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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13903434
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Filing Dt:
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05/28/2013
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Publication #:
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Pub Dt:
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12/04/2014
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Title:
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ADDRESS WINDOWING FOR AT-SPEED BITMAPPING WITH MEMORY BUILT-IN SELF-TEST
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Patent #:
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Issue Dt:
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12/01/2015
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Application #:
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13903610
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Filing Dt:
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05/28/2013
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Publication #:
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Pub Dt:
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12/04/2014
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Title:
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Detecting sensitive data access by reporting presence of benign pseudo virus signatures
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13903802
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Filing Dt:
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05/28/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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METHODS FOR INTEGRATION OF PORE STUFFING MATERIAL
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Patent #:
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Issue Dt:
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02/02/2016
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Application #:
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13904033
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Filing Dt:
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05/29/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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LOCATION INFO-GRAPHICS VISUALIZATIONS
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Patent #:
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Issue Dt:
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01/13/2015
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Application #:
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13904060
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Filing Dt:
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05/29/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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Self-Aligned Gate Electrode Diffusion Barriers
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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13904304
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Filing Dt:
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05/29/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE BY FORMING MONOCRYSTALLINE SEMICONDUCTOR LAYERS ON A DIELECTRIC LAYER OVER ISOLATION REGIONS
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13904384
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Filing Dt:
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05/29/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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LATERAL BIPOLAR TRANSISTORS HAVING PARTIALLY-DEPLETED INTRINSIC BASE
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Patent #:
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Issue Dt:
|
07/21/2015
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Application #:
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13904626
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Filing Dt:
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05/29/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH SHALLOW TRENCH ISOLATION THAT INCLUDES A THERMAL OXIDE LAYER AND METHODS FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13904744
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Filing Dt:
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05/29/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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Silicidation Blocking Process Using Optically Sensitive HSQ Resist and Organic Planarizing Layer
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Patent #:
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Issue Dt:
|
09/27/2016
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Application #:
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13904942
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Filing Dt:
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05/29/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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METHOD AND SYSTEM FOR CREATING AND REFINING RULES FOR PERSONALIZED CONTENT DELIVERY BASED ON USERS PHYSICAL ACTIVITES
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Patent #:
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Issue Dt:
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06/17/2014
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Application #:
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13905204
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
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12/12/2013
| | | | |
Title:
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SPACER ISOLATION IN DEEP TRENCH
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Patent #:
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Issue Dt:
|
11/11/2014
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Application #:
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13905271
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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METHODS OF FORMING CONDUCTIVE STRUCTURES USING A SACRIFICIAL MATERIAL DURING A METAL HARD MASK REMOVAL PROCESS
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13905289
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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TRANSMISSION ELECTRON MICROSCOPE SAMPLE FABRICATION
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Patent #:
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Issue Dt:
|
10/07/2014
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Application #:
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13905351
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Filing Dt:
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05/30/2013
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Title:
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HYBRID HARD MASK FOR DAMASCENE AND DUAL DAMASCENE
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Patent #:
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Issue Dt:
|
06/23/2015
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Application #:
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13905442
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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13905556
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
|
10/03/2013
| | | | |
Title:
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MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY
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Patent #:
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Issue Dt:
|
10/27/2015
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Application #:
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13905661
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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LOW GATE-TO-DRAIN CAPACITANCE FULLY MERGED FINFET
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Patent #:
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Issue Dt:
|
08/19/2014
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Application #:
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13905741
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Filing Dt:
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05/30/2013
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Title:
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INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CLADDED NON-PLANAR TRANSISTOR STRUCTURES
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Patent #:
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Issue Dt:
|
02/02/2016
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Application #:
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13905840
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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HETEROJUNCTION LIGHT EMITTING DIODE
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Patent #:
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Issue Dt:
|
08/26/2014
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Application #:
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13905850
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Filing Dt:
|
05/30/2013
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Title:
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MULTIGATE DEVICE ISOLATION ON BULK SEMICONDUCTORS
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13905894
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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LOCAL INTERCONNECTS BY METAL-III-V ALLOY WIRING IN SEMI-INSULATING III-V SUBSTRATES
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Patent #:
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Issue Dt:
|
05/03/2016
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Application #:
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13906428
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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MULTI-HEIGHT FINFETS WITH COPLANAR TOPOGRAPHY BACKGROUND
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Patent #:
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Issue Dt:
|
07/21/2015
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Application #:
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13906482
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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INCREASING RESILIENCY OF A DISTRIBUTED COMPUTING SYSTEM THROUGH LIFEBOAT MONITORING
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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13906644
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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HALO REGION FORMATION BY EPITAXIAL GROWTH
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Patent #:
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Issue Dt:
|
06/09/2015
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Application #:
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13906746
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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Optimal Volume Placement Across Remote Replication Relationships
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Patent #:
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Issue Dt:
|
02/24/2015
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Application #:
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13906852
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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DEVICE ISOLATION IN FINFET CMOS
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Patent #:
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Issue Dt:
|
05/26/2015
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Application #:
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13906921
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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Fin eFuse Formed by Trench Silicide Process
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13906955
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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METHODS FOR OVERLAY IMPROVEMENT THROUGH FEED FORWARD CORRECTION
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13907237
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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METHOD FOR THE FORMATION OF A PROTECTIVE DUAL LINER FOR A SHALLOW TRENCH ISOLATION STRUCTURE
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Patent #:
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Issue Dt:
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07/07/2015
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Application #:
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13907362
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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SPACER STRESS RELAXATION
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Patent #:
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Issue Dt:
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03/24/2015
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13907690
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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PREVENTION OF FACETING IN EPITAXIAL SOURCE DRAIN TRANSISTORS
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13907736
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Filing Dt:
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05/31/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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ITERATIVE DATA STORAGE READ CHANNEL ARCHITECTURE
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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13908048
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Filing Dt:
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06/03/2013
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Publication #:
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Pub Dt:
|
10/17/2013
| | | | |
Title:
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SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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13908096
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Filing Dt:
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06/03/2013
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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WIDE PIN FOR IMPROVED CIRCUIT ROUTING
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Patent #:
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Issue Dt:
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06/30/2015
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Application #:
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13908118
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Filing Dt:
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06/03/2013
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Publication #:
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Pub Dt:
|
10/10/2013
| | | | |
Title:
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Reduced S/D Contact Resistance of III-V Mosfet Using Low Temperature Metal-Induced Crystallization of n+ Ge
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13908161
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Filing Dt:
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06/03/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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COORDINATED NETWORK SECURITY MANAGEMENT
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13908510
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Filing Dt:
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06/03/2013
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Publication #:
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Pub Dt:
|
12/04/2014
| | | | |
Title:
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DISTORTING DONOR WAFER TO CORRESPONDING DISTORTION OF HOST WAFER
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Patent #:
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Issue Dt:
|
03/24/2015
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Application #:
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13908624
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Filing Dt:
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06/03/2013
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Publication #:
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Pub Dt:
|
10/10/2013
| | | | |
Title:
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METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE
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