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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
03/19/2002
Application #:
09716215
Filing Dt:
11/21/2000
Title:
Bright field image reversal for contact hole patterning
2
Patent #:
Issue Dt:
05/28/2002
Application #:
09716749
Filing Dt:
11/20/2000
Title:
TRENCH-DEFINED SILICON GERMANIUM ESD DIODE NETWORK
3
Patent #:
Issue Dt:
09/28/2004
Application #:
09716915
Filing Dt:
11/20/2000
Title:
METHOD AND SYSTEM FOR DETECTING A HARD FAILURE IN A MEMORY ARRAY
4
Patent #:
Issue Dt:
08/31/2004
Application #:
09716916
Filing Dt:
11/20/2000
Title:
FAULT TOLERANT MEMORY SYSTEM UTILIZING MEMORY ARRAYS WITH HARD ERROR DETECTION
5
Patent #:
Issue Dt:
09/14/2004
Application #:
09718850
Filing Dt:
11/22/2000
Title:
LOGIC SOI STRUCTURE, PROCESS AND APPLICATION FOR VERTICAL BIPOLAR TRANSISTOR
6
Patent #:
Issue Dt:
09/17/2002
Application #:
09722222
Filing Dt:
11/27/2000
Title:
HOW TO IMPROVE THE ESD ON SOI DEVICES
7
Patent #:
Issue Dt:
04/09/2002
Application #:
09723812
Filing Dt:
11/28/2000
Title:
Graded compound seed layers for semiconductors
8
Patent #:
Issue Dt:
03/25/2003
Application #:
09724134
Filing Dt:
11/28/2000
Title:
SYSTEMS AND METHODS FOR GENERATING HARDWARE DESCRIPTION CODE
9
Patent #:
Issue Dt:
07/10/2001
Application #:
09725412
Filing Dt:
11/29/2000
Title:
Embedded vertical dram cells and dual workfunction logic gates
10
Patent #:
Issue Dt:
04/22/2003
Application #:
09726697
Filing Dt:
11/29/2000
Publication #:
Pub Dt:
05/30/2002
Title:
FLUX COMPOSITION AND SOLDERING METHOD FOR HIGH DENSITY ARRAYS
11
Patent #:
Issue Dt:
11/26/2002
Application #:
09727572
Filing Dt:
11/30/2000
Publication #:
Pub Dt:
05/30/2002
Title:
METHOD TO STABILIZE A CARBON ALIGNMENT LAYER FOR LIQUID CRYSTAL DISPLAYS
12
Patent #:
Issue Dt:
09/03/2002
Application #:
09728312
Filing Dt:
11/30/2000
Title:
METHOD OF REDUCING CARBON, SULPHUR, AND OXYGEN IMPURITIES IN A CALCIUM-DOPED COPPER SURFACE AND SEMICONDUCTOR DEVICE THEREBY FORMED
13
Patent #:
Issue Dt:
09/18/2001
Application #:
09728315
Filing Dt:
11/30/2000
Title:
Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby formed
14
Patent #:
Issue Dt:
09/03/2002
Application #:
09729295
Filing Dt:
12/04/2000
Title:
ELECTRON BEAM FLOOD EXPOSURE TECHNIQUE TO REDUCE THE CARBON CONTAMINATION
15
Patent #:
Issue Dt:
08/12/2003
Application #:
09729699
Filing Dt:
12/06/2000
Publication #:
Pub Dt:
06/06/2002
Title:
METHOD OF FORMING NICKEL SILICIDE USING A ONE-STEP RAPID THERMAL ANNEAL PROCESS AND BACKEND PROCESSING
16
Patent #:
Issue Dt:
08/06/2002
Application #:
09730673
Filing Dt:
12/06/2000
Publication #:
Pub Dt:
06/06/2002
Title:
DRAM CAM CELL WITH HIDDEN REFRESH
17
Patent #:
Issue Dt:
11/05/2002
Application #:
09731031
Filing Dt:
12/07/2000
Publication #:
Pub Dt:
08/01/2002
Title:
DAMASCENE NISI METAL GATE HIGH-K TRANSISTOR
18
Patent #:
Issue Dt:
06/10/2003
Application #:
09731147
Filing Dt:
12/05/2000
Publication #:
Pub Dt:
08/01/2002
Title:
METHOD AND APPARATUS FOR INITIALIZING AN INTEGRATED CIRCUIT USING COMPRESSED DATA FROM A REMOTE FUSEBOX
19
Patent #:
Issue Dt:
12/31/2002
Application #:
09731577
Filing Dt:
12/06/2000
Publication #:
Pub Dt:
06/06/2002
Title:
RESIST TRIM PROCESS TO DEFINE SMALL OPENINGS IN DIELECTRIC LAYERS
20
Patent #:
Issue Dt:
06/11/2002
Application #:
09731616
Filing Dt:
12/07/2000
Title:
ENHANCED INTERFACE THERMOELECTRIC COOLERS WITH ALL-METAL TIPS
21
Patent #:
Issue Dt:
08/05/2003
Application #:
09731620
Filing Dt:
12/07/2000
Publication #:
Pub Dt:
06/13/2002
Title:
SHALLOW TRENCH ISOLATION FOR THIN SILICON/SILICON-ON-INSULATOR SUBSTRATES BY UTILIZING POLYSILICON
22
Patent #:
Issue Dt:
05/07/2002
Application #:
09731997
Filing Dt:
12/07/2000
Title:
THERMOELECTRIC COOLERS WITH ENHANCED STRUCTURED INTERFACES
23
Patent #:
Issue Dt:
12/17/2002
Application #:
09733295
Filing Dt:
12/08/2000
Publication #:
Pub Dt:
08/15/2002
Title:
METHOD AND APPARATUS FOR TESTING A WRITE FUNCTION OF A DUAL-PORT STATIC MEMORY CELL
24
Patent #:
Issue Dt:
05/14/2002
Application #:
09733778
Filing Dt:
12/08/2000
Title:
METHOD OF SALICIDE FORMATION BY SILICIDING A GATE AREA PRIOR TO SLILICIDING A SOURCE AND DRAIN AREA
25
Patent #:
Issue Dt:
01/06/2004
Application #:
09733968
Filing Dt:
12/12/2000
Publication #:
Pub Dt:
02/21/2002
Title:
NANOPARTICLE STRUCTURES UTILIZING SYNTHETIC DNA LATTICES
26
Patent #:
Issue Dt:
04/09/2002
Application #:
09734186
Filing Dt:
12/12/2000
Title:
SILICIDE GATE TRANSISTORS
27
Patent #:
Issue Dt:
01/29/2002
Application #:
09734189
Filing Dt:
12/12/2000
Title:
Damascene NiSi metal gate high-K transistor
28
Patent #:
Issue Dt:
08/05/2003
Application #:
09734207
Filing Dt:
12/12/2000
Title:
METAL SILICIDE GATE TRANSISTORS
29
Patent #:
Issue Dt:
09/14/2004
Application #:
09734225
Filing Dt:
12/11/2000
Publication #:
Pub Dt:
06/13/2002
Title:
BACKSIDE INTEGRATED CIRCUIT DIE SURFACE FINISHING TECHNIQUE AND TOOL
30
Patent #:
Issue Dt:
09/30/2003
Application #:
09734830
Filing Dt:
12/12/2000
Publication #:
Pub Dt:
08/15/2002
Title:
ELECTROPLATING APPARATUS WITH VERTICAL ELECTRICAL CONTACT
31
Patent #:
Issue Dt:
04/02/2002
Application #:
09735197
Filing Dt:
12/06/2000
Title:
PROCESSOR CONFIGURED TO FETCH A BRANCH TARGET ADDRESS FROM ONE SEVERAL INSTRUCTION CACHES RESPONSIVE TO A SIZE OF A DISPLACEMENT OF A CORRESPONDING BRANCH INSTRUCTION
32
Patent #:
Issue Dt:
07/09/2002
Application #:
09735988
Filing Dt:
12/13/2000
Publication #:
Pub Dt:
08/08/2002
Title:
METHOD FOR FORMING A LINER IN A TRENCH
33
Patent #:
Issue Dt:
02/18/2003
Application #:
09737012
Filing Dt:
12/14/2000
Publication #:
Pub Dt:
08/15/2002
Title:
METHOD FOR SUPPLY VOLTAGE DROP ANALYSIS DURING PLACEMENT PHASE OF CHIP DESIGN
34
Patent #:
Issue Dt:
02/26/2002
Application #:
09737198
Filing Dt:
12/14/2000
Title:
Increased polish removal rate of dielectric layers using fixed abrasive pads
35
Patent #:
Issue Dt:
09/17/2002
Application #:
09739935
Filing Dt:
12/18/2000
Publication #:
Pub Dt:
06/20/2002
Title:
METHOD FOR FORMING A POROUS DIELECTRIC MATERIAL LAYER IN A SEMICONDUCTOR DEVICE AND DEVICE FORMED
36
Patent #:
Issue Dt:
01/07/2003
Application #:
09740089
Filing Dt:
12/18/2000
Publication #:
Pub Dt:
06/20/2002
Title:
INTERCONNECTS WITH TI-CONTAINING LINERS
37
Patent #:
Issue Dt:
08/06/2002
Application #:
09742976
Filing Dt:
12/20/2000
Publication #:
Pub Dt:
08/23/2001
Title:
MICROPROCESSOR HAVING AIR AS A DIELECTRIC AND ENCAPSULATED LINES
38
Patent #:
Issue Dt:
01/20/2004
Application #:
09745047
Filing Dt:
12/20/2000
Title:
CONTACT CAPPING LOCAL INTERCONNECT
39
Patent #:
Issue Dt:
11/18/2003
Application #:
09745273
Filing Dt:
12/20/2000
Publication #:
Pub Dt:
11/08/2001
Title:
DEVICE FOR CONTACTING AND/OR MODIFYING A SURFACE HAVING A CANTILEVER AND A METHOD FOR PRODUCTION OF SAID CANTILEVER
40
Patent #:
Issue Dt:
08/27/2002
Application #:
09745361
Filing Dt:
12/21/2000
Title:
METHOD OF FABRICATING A POLY-POLY CAPACITOR WITH A SIGE BICMOS INTEGRATION SCHEME
41
Patent #:
Issue Dt:
04/22/2003
Application #:
09745951
Filing Dt:
12/22/2000
Publication #:
Pub Dt:
06/27/2002
Title:
DUAL PURPOSE LOW POWER INPUT CIRCUIT FOR A MEMORY DEVICE INTERFACE
42
Patent #:
Issue Dt:
11/30/2004
Application #:
09748256
Filing Dt:
12/27/2000
Title:
SEMICONDUCTOR DEVICE ON A COMBINATION BULK SILICON AND SILICON-ON-INSULATOR (SOI) SUBSTRATE
43
Patent #:
Issue Dt:
09/21/2004
Application #:
09748965
Filing Dt:
12/27/2000
Publication #:
Pub Dt:
05/17/2001
Title:
INTEGRATED COBALT SILICIDE PROCESS FOR SEMICONDUCTOR DEVICES
44
Patent #:
Issue Dt:
02/26/2002
Application #:
09749112
Filing Dt:
12/26/2000
Publication #:
Pub Dt:
05/03/2001
Title:
Method for determining a polishing recipe based upon the measured pre-polish thickness of a process layer
45
Patent #:
Issue Dt:
05/13/2003
Application #:
09749162
Filing Dt:
12/27/2000
Publication #:
Pub Dt:
06/27/2002
Title:
DISTRIBUTED CONNECTOR SYSTEM FOR WEARABLE COMPUTERS
46
Patent #:
Issue Dt:
04/13/2004
Application #:
09749191
Filing Dt:
12/26/2000
Publication #:
Pub Dt:
01/22/2004
Title:
PREVENTION OF PRECIPITATION DEFECTS ON COPPER INTERCONNECTS DURING CPM BY USE OF SOLUTIONS CONTAINING ORGANIC COMPOUNDS WITH SILICA ADSORPTION AND COPPER CORROSION INHIBITING PROPERTIES
47
Patent #:
Issue Dt:
05/27/2003
Application #:
09749293
Filing Dt:
12/27/2000
Title:
METHOD AND APPARATUS FOR USING LATENCY TIME AS A RUN-TO RUN CONTROL PARAMETER
48
Patent #:
Issue Dt:
11/12/2013
Application #:
09750475
Filing Dt:
12/28/2000
Publication #:
Pub Dt:
04/04/2002
Title:
DATA SOURCE INTERFACE ENHANCED ERROR RECOVERY
49
Patent #:
Issue Dt:
12/04/2001
Application #:
09750593
Filing Dt:
12/28/2000
Publication #:
Pub Dt:
05/31/2001
Title:
Chemical-mechanical polishing slurry that reduces wafer defects
50
Patent #:
Issue Dt:
02/03/2004
Application #:
09750969
Filing Dt:
12/28/2000
Publication #:
Pub Dt:
08/22/2002
Title:
SYSTEM AND METHOD FOR INSERTING LEAKAGE REDUCTION CONTROL IN LOGIC CIRCUITS
51
Patent #:
Issue Dt:
05/21/2002
Application #:
09752571
Filing Dt:
12/28/2000
Publication #:
Pub Dt:
08/23/2001
Title:
PROCESS FOR FABRICATING SINGLE CRYSTAL RESONANT DEVICES THAT ARE COMPATIBLE WITH INTEGRATED CIRCUIT PROCESSING
52
Patent #:
Issue Dt:
10/18/2005
Application #:
09752719
Filing Dt:
01/03/2001
Publication #:
Pub Dt:
07/04/2002
Title:
METHOD AND APPARATUS FOR PERFORMING PRIORITY-BASED FLOW CONTROL
53
Patent #:
Issue Dt:
09/17/2002
Application #:
09753015
Filing Dt:
01/02/2001
Publication #:
Pub Dt:
09/20/2001
Title:
COMPOSITE LAMINATE CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME
54
Patent #:
Issue Dt:
12/03/2002
Application #:
09753284
Filing Dt:
01/02/2001
Publication #:
Pub Dt:
07/04/2002
Title:
SPIRAL INDUCTOR SEMICONDUCTING DEVICE WITH GROUNDING STRIPS AND CONDUCTING VIAS
55
Patent #:
Issue Dt:
07/01/2003
Application #:
09753705
Filing Dt:
01/03/2001
Title:
USE OF ENDPOINT SYSTEM TO MATCH INDIVIDUAL PROCESSING STATIONS WITHIN A TOOL
56
Patent #:
Issue Dt:
11/12/2002
Application #:
09753809
Filing Dt:
01/03/2001
Title:
LOW DEFECT ORGANIC BARC COATING IN A SEMICONDUCTOR STRUCTURE
57
Patent #:
Issue Dt:
07/23/2002
Application #:
09753845
Filing Dt:
01/03/2001
Title:
METHODOLOGY FOR ELECTRICALLY INDUCED SELECTIVE BREAKDOWN OF NANOTUBES
58
Patent #:
Issue Dt:
04/22/2003
Application #:
09754910
Filing Dt:
01/05/2001
Publication #:
Pub Dt:
07/11/2002
Title:
METHOD TO DETERMINE OPTICAL PROXIMITY CORRECTION AND ASSIST FEATURE RULES WHICH ACCOUNT FOR VARIATIONS IN MASK DIMENSIONS
59
Patent #:
Issue Dt:
09/16/2003
Application #:
09755012
Filing Dt:
01/05/2001
Title:
SOI DIE ANALYSIS OF CIRCUITRY LOGIC STATES VIA COUPLING THROUGH THE INSULATOR
60
Patent #:
Issue Dt:
12/14/2004
Application #:
09755164
Filing Dt:
01/08/2001
Publication #:
Pub Dt:
07/11/2002
Title:
ALUMINUM NITRIDE AND ALUMINUM OXIDE/ALUMINUM NITRIDE HETEROSTRUCTURE GATE DIELECTRIC STACK BASED FIELD EFFECT TRANSISTORS AND METHOD FOR FORMING SAME
61
Patent #:
Issue Dt:
10/29/2002
Application #:
09755216
Filing Dt:
01/04/2001
Title:
DEVICE FOR POWER SUPPLY DETECTION AND POWER ON RESET
62
Patent #:
Issue Dt:
10/15/2002
Application #:
09757107
Filing Dt:
01/08/2001
Publication #:
Pub Dt:
07/11/2002
Title:
LINEAR VOLTAGE CONTROLLED OSCILLATOR TRANSCONDUCTOR WITH GAIN COMPENSATION
63
Patent #:
Issue Dt:
10/08/2002
Application #:
09757118
Filing Dt:
01/09/2001
Title:
Method and apparatus for measuring effects of packaging stresses of common IC electrical performance parameters at wafer sort
64
Patent #:
Issue Dt:
06/10/2003
Application #:
09757159
Filing Dt:
01/09/2001
Publication #:
Pub Dt:
01/17/2002
Title:
METHOD FOR BONDING HEAT SINKS TO OVERMOLDS AND DEVICE FORMED THEREBY
65
Patent #:
Issue Dt:
04/13/2004
Application #:
09757185
Filing Dt:
01/09/2001
Publication #:
Pub Dt:
05/17/2001
Title:
METHOD FOR BONDING HEAT SINKS TO OVERMOLDS AND DEVICE FORMED THEREBY
66
Patent #:
Issue Dt:
07/16/2002
Application #:
09757267
Filing Dt:
01/09/2001
Publication #:
Pub Dt:
07/11/2002
Title:
PROGRAMMABLE LATCH DEVICE WITH INTEGRATED PROGRAMMABLE ELEMENT
67
Patent #:
Issue Dt:
12/02/2003
Application #:
09757317
Filing Dt:
01/09/2001
Publication #:
Pub Dt:
07/11/2002
Title:
GROUND-PLANE DEVICE WITH BACK OXIDE TOPOGRAPHY
68
Patent #:
Issue Dt:
02/01/2005
Application #:
09757965
Filing Dt:
01/10/2001
Publication #:
Pub Dt:
07/11/2002
Title:
FULLY-DEPLETED-COLLECTOR SILICON-ON-INSULATOR (SOI) BIPOLAR TRANSISTOR USEFUL ALONE OR IN SOI BICMOS
69
Patent #:
Issue Dt:
02/26/2002
Application #:
09758487
Filing Dt:
01/10/2001
Title:
Apparatus and method for monitoring the performance of a microprocessor
70
Patent #:
Issue Dt:
01/01/2002
Application #:
09758989
Filing Dt:
01/12/2001
Title:
Wafer cleaning apparatus
71
Patent #:
Issue Dt:
06/10/2003
Application #:
09759013
Filing Dt:
01/11/2001
Publication #:
Pub Dt:
07/11/2002
Title:
PROCESS WINDOW BASED OPTICAL PROXIMITY CORRECTION OF LITHOGRAPHIC IMAGES
72
Patent #:
Issue Dt:
08/20/2002
Application #:
09759258
Filing Dt:
01/16/2001
Publication #:
Pub Dt:
04/25/2002
Title:
THIN FILM METAL BARRIER FOR ELECTRICAL INTERCONNECTIONS
73
Patent #:
Issue Dt:
06/11/2002
Application #:
09760241
Filing Dt:
01/12/2001
Title:
CROSS-SHAPED RESIST DISPENSING SYSTEM AND METHOD
74
Patent #:
Issue Dt:
11/12/2002
Application #:
09760421
Filing Dt:
01/11/2001
Title:
DIELECTRIC TREATMENT IN INTEGRATED CIRCUIT INTERCONNECTS
75
Patent #:
Issue Dt:
05/02/2006
Application #:
09760560
Filing Dt:
01/16/2001
Publication #:
Pub Dt:
09/26/2002
Title:
METHOD AND INTERFACE FOR GLITCH-FREE CLOCK SWITCHING
76
Patent #:
Issue Dt:
11/12/2002
Application #:
09760955
Filing Dt:
01/16/2001
Title:
BOND PAD STRUCTURE AND METHOD FOR REDUCED DOWNWARD FORCE WIREBONDING
77
Patent #:
Issue Dt:
11/26/2002
Application #:
09761124
Filing Dt:
01/16/2001
Publication #:
Pub Dt:
07/18/2002
Title:
COMPLIANT LAYER FOR ENCAPSULATED CLOUMNS
78
Patent #:
Issue Dt:
02/18/2003
Application #:
09761464
Filing Dt:
01/16/2001
Publication #:
Pub Dt:
07/18/2002
Title:
METHOD FOR ADDING DECOUPLING CAPACITANCE DURING INTEGRATED CIRCUIT DESIGN
79
Patent #:
Issue Dt:
04/08/2003
Application #:
09764048
Filing Dt:
01/17/2001
Publication #:
Pub Dt:
10/03/2002
Title:
ADJUSTING FILLET GEOMETRY TO COUPLE A HEAT SPREADER TO A CHIP CARRIER
80
Patent #:
Issue Dt:
01/28/2003
Application #:
09764132
Filing Dt:
01/19/2001
Title:
HEAT SINK GROUNDED TO A GROUNDED PACKAGE LID
81
Patent #:
Issue Dt:
04/01/2003
Application #:
09764674
Filing Dt:
01/18/2001
Publication #:
Pub Dt:
07/18/2002
Title:
METHOD OF FORMING A SHALLOW TRENCH ISOLATION USING NON-CONFORMAL DIELECTRIC MATERIAL AND PLANARIZATRION
82
Patent #:
Issue Dt:
02/03/2004
Application #:
09764833
Filing Dt:
01/17/2001
Publication #:
Pub Dt:
07/18/2002
Title:
STRUCTURE AND METHOD OF FORMING BITLINE CONTACTS FOR A VERTICAL DRAM ARRAY USING A LINE BITLINE CONTACT MASK
83
Patent #:
Issue Dt:
04/16/2002
Application #:
09765035
Filing Dt:
01/17/2001
Title:
INTEGRATED FUSE LATCH AND SHIFT REGISTER FOR EFFICIENT PROGRAMMING AND FUSE READOUT
84
Patent #:
Issue Dt:
06/04/2002
Application #:
09765666
Filing Dt:
01/22/2001
Publication #:
Pub Dt:
08/23/2001
Title:
INTEGRATION OF LOW-K SIOF FOR DAMASCENE STRUCTURE
85
Patent #:
Issue Dt:
04/01/2003
Application #:
09766005
Filing Dt:
01/18/2001
Publication #:
Pub Dt:
07/18/2002
Title:
METHOD AND APPARATUS FOR LITHOGRAPHICALLY PRINTING TIGHTLY NESTED AND ISOLATED DEVICE FEATURES USING MULTIPLE MASK EXPOSURES
86
Patent #:
Issue Dt:
03/18/2003
Application #:
09766481
Filing Dt:
01/19/2001
Title:
CIRCUIT FOR DETECTING A COOLING DEVICE IN A COMPUTER SYSTEM
87
Patent #:
Issue Dt:
04/02/2002
Application #:
09766737
Filing Dt:
01/22/2001
Title:
Automated variation of stepper exposure dose based upon across wafer variations in device characteristics, and system for accomplishing same
88
Patent #:
Issue Dt:
08/13/2002
Application #:
09766799
Filing Dt:
01/22/2001
Publication #:
Pub Dt:
07/25/2002
Title:
REFRESH CONTROL CIRCUIT FOR LOW-POWER SRAM APPLICATIONS
89
Patent #:
Issue Dt:
03/19/2002
Application #:
09768112
Filing Dt:
01/23/2001
Publication #:
Pub Dt:
05/31/2001
Title:
Rolling ball connector
90
Patent #:
Issue Dt:
03/16/2004
Application #:
09768122
Filing Dt:
01/23/2001
Publication #:
Pub Dt:
07/25/2002
Title:
METHOD FOR GUARANTEEING A MINIMUM DATA STROBE VALID WINDOW AND A MINIMUM DATA VALID WINDOW FOR DDR MEMORY DEVICES
91
Patent #:
Issue Dt:
09/11/2001
Application #:
09768493
Filing Dt:
01/24/2001
Publication #:
Pub Dt:
07/19/2001
Title:
Silicon-germanium BiCMOS on SOI
92
Patent #:
Issue Dt:
11/18/2003
Application #:
09768833
Filing Dt:
01/24/2001
Publication #:
Pub Dt:
07/25/2002
Title:
APPARATUS AND METHOD FOR WAFER CLEANING
93
Patent #:
Issue Dt:
08/10/2004
Application #:
09769170
Filing Dt:
01/25/2001
Publication #:
Pub Dt:
07/25/2002
Title:
TRANSFERABLE DEVICE-CONTAINING LAYER FOR SILICON-ON-INSULATOR APPLICATIONS
94
Patent #:
Issue Dt:
01/06/2004
Application #:
09769640
Filing Dt:
01/25/2001
Publication #:
Pub Dt:
07/25/2002
Title:
STI PULL-DOWN TO CONTROL SIGE FACET GROWTH
95
Patent #:
Issue Dt:
10/15/2002
Application #:
09769667
Filing Dt:
01/25/2001
Publication #:
Pub Dt:
07/25/2002
Title:
ESD ROBUST SILICON GERMANIUM TRANSISTOR WITH EMITTER NP-BLOCK MASK EXTRINSIC BASE BALLASTING RESISTOR WITH DOPED FACET REGION
96
Patent #:
Issue Dt:
07/23/2002
Application #:
09770065
Filing Dt:
01/25/2001
Publication #:
Pub Dt:
02/28/2002
Title:
PROGRAMMABLE GAIN AMPLIFIER FOR USE IN DATA NETWORK
97
Patent #:
Issue Dt:
09/10/2002
Application #:
09770468
Filing Dt:
01/29/2001
Title:
ULTRA THIN ETCH STOP LAYER FOR DAMASCENE PROCESS
98
Patent #:
Issue Dt:
10/29/2002
Application #:
09770469
Filing Dt:
01/29/2001
Title:
DIELECTRIC LAYER WITH TREATED TOP SURFACE FORMING AN ETCH STOP LAYER AND METHOD OF MAKING THE SAME
99
Patent #:
Issue Dt:
09/23/2003
Application #:
09770730
Filing Dt:
01/26/2001
Title:
PELLICLE FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A PELLICLE
100
Patent #:
Issue Dt:
04/08/2003
Application #:
09770733
Filing Dt:
01/26/2001
Publication #:
Pub Dt:
09/12/2002
Title:
PELLICLE FOR USE IN SMALL WAVELENGTH LITHOGRAPHY AND A METHOD FOR MAKING SUCH A PELLICLE
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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