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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
03/28/2017
Application #:
14681428
Filing Dt:
04/08/2015
Publication #:
Pub Dt:
10/13/2016
Title:
INTEGRATED CIRCUITS WITH SPACER CHAMFERING AND METHODS OF SPACER CHAMFERING
2
Patent #:
Issue Dt:
07/05/2016
Application #:
14682910
Filing Dt:
04/09/2015
Publication #:
Pub Dt:
07/30/2015
Title:
ENHANCED CHARGE DEVICE MODEL CLAMP
3
Patent #:
Issue Dt:
06/28/2016
Application #:
14684533
Filing Dt:
04/13/2015
Publication #:
Pub Dt:
08/06/2015
Title:
DEEP TRENCH CAPACITOR
4
Patent #:
Issue Dt:
03/21/2017
Application #:
14684664
Filing Dt:
04/13/2015
Publication #:
Pub Dt:
10/13/2016
Title:
INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER
5
Patent #:
Issue Dt:
09/05/2017
Application #:
14684782
Filing Dt:
04/13/2015
Publication #:
Pub Dt:
06/09/2016
Title:
METHOD, COMPUTER READABLE STORAGE MEDIUM AND COMPUTER SYSTEM FOR CREATING A LAYOUT OF A PHOTOMASK
6
Patent #:
Issue Dt:
12/27/2016
Application #:
14684949
Filing Dt:
04/13/2015
Publication #:
Pub Dt:
10/13/2016
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING MULTI-PATTERNING PROCESSES
7
Patent #:
Issue Dt:
10/04/2016
Application #:
14685061
Filing Dt:
04/13/2015
Publication #:
Pub Dt:
10/13/2016
Title:
ELECTRONIC PACKAGE THAT INCLUDES A PLURALITY OF INTEGRATED CIRCUIT DEVICES BONDED IN A THREE-DIMENSIONAL STACK ARRANGEMENT
8
Patent #:
Issue Dt:
05/16/2017
Application #:
14685701
Filing Dt:
04/14/2015
Publication #:
Pub Dt:
06/09/2016
Title:
METHODS FOR OPTICAL PROXIMITY CORRECTION IN THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS USING EXTREME ULTRAVIOLET LITHOGRAPHY
9
Patent #:
Issue Dt:
04/05/2016
Application #:
14685745
Filing Dt:
04/14/2015
Title:
UNIFORMLY DOPED LEAKAGE CURRENT STOPPER TO COUNTER UNDER CHANNEL LEAKAGE CURRENTS IN BULK FINFET DEVICES
10
Patent #:
Issue Dt:
04/18/2017
Application #:
14685944
Filing Dt:
04/14/2015
Publication #:
Pub Dt:
10/20/2016
Title:
REPLACEMENT CHANNEL TFET
11
Patent #:
Issue Dt:
09/06/2016
Application #:
14686228
Filing Dt:
04/14/2015
Publication #:
Pub Dt:
08/06/2015
Title:
EPITAXIALLY FORMING A SET OF FINS IN A SEMICONDUCTOR DEVICE
12
Patent #:
Issue Dt:
07/05/2016
Application #:
14686260
Filing Dt:
04/14/2015
Publication #:
Pub Dt:
08/06/2015
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING SOURCE/DRAIN EPITAXIAL OVERGROWTH FOR FORMING SELF-ALIGNED CONTACTS WITHOUT SPACER LOSS AND A SEMICONDUCTOR DEVICE FORMED BY SAME
13
Patent #:
Issue Dt:
05/17/2016
Application #:
14686857
Filing Dt:
04/15/2015
Title:
METHODS OF FORMING SOURCE/DRAIN REGIONS FOR A PMOS TRANSISTOR DEVICE WITH A GERMANIUM-CONTAINING CHANNEL REGION
14
Patent #:
Issue Dt:
03/07/2017
Application #:
14686904
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
10/20/2016
Title:
WHOLE WAFER EDGE SEAL
15
Patent #:
Issue Dt:
09/06/2016
Application #:
14686972
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
08/06/2015
Title:
BARRIER TRENCH STRUCTURE AND METHODS OF MANUFACTURE
16
Patent #:
Issue Dt:
08/08/2017
Application #:
14687002
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
10/20/2016
Title:
ON CHIP ANTENNA WITH OPENING
17
Patent #:
Issue Dt:
03/29/2016
Application #:
14687049
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
08/06/2015
Title:
ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
18
Patent #:
Issue Dt:
11/17/2015
Application #:
14687050
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
08/06/2015
Title:
DATA STORAGE TAPE WITH RANDOM ACCESS DATA
19
Patent #:
Issue Dt:
06/28/2016
Application #:
14687203
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
07/14/2016
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF FINS AND AN ALIGNMENT/OVERLAY MARK
20
Patent #:
Issue Dt:
01/12/2016
Application #:
14687300
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
11/26/2015
Title:
METHODS OF FABRICATING SEMICONDUCTOR FIN STRUCTURES
21
Patent #:
Issue Dt:
07/26/2016
Application #:
14687477
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
08/06/2015
Title:
COLOR-INSENSITIVE RULES FOR ROUTING STRUCTURES
22
Patent #:
Issue Dt:
06/28/2016
Application #:
14687489
Filing Dt:
04/15/2015
Publication #:
Pub Dt:
10/15/2015
Title:
CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
23
Patent #:
Issue Dt:
02/16/2016
Application #:
14688027
Filing Dt:
04/16/2015
Publication #:
Pub Dt:
08/06/2015
Title:
OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
24
Patent #:
Issue Dt:
03/19/2019
Application #:
14689088
Filing Dt:
04/17/2015
Publication #:
Pub Dt:
10/20/2016
Title:
SYSTEMATIC DEFECTS INSPECTION METHOD WITH COMBINED EBEAM INSPECTION AND NET TRACING CLASSIFICATION
25
Patent #:
Issue Dt:
01/03/2017
Application #:
14689181
Filing Dt:
04/17/2015
Publication #:
Pub Dt:
10/20/2016
Title:
FET DEVICE WITH TUNED GATE WORK FUNCTION
26
Patent #:
Issue Dt:
08/07/2018
Application #:
14691124
Filing Dt:
04/20/2015
Publication #:
Pub Dt:
08/13/2015
Title:
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack for Dopant Source and Passivation
27
Patent #:
Issue Dt:
01/10/2017
Application #:
14691233
Filing Dt:
04/20/2015
Publication #:
Pub Dt:
10/20/2016
Title:
PUNCH-THROUGH-STOP AFTER PARTIAL FIN ETCH
28
Patent #:
Issue Dt:
05/30/2017
Application #:
14691270
Filing Dt:
04/20/2015
Publication #:
Pub Dt:
08/13/2015
Title:
FORMATION OF LARGE SCALE SINGLE CRYSTALLINE GRAPHENE
29
Patent #:
Issue Dt:
11/29/2016
Application #:
14691392
Filing Dt:
04/20/2015
Publication #:
Pub Dt:
08/13/2015
Title:
INFRARED-BASED METROLOGY FOR DETECTION OF STRESS AND DEFECTS AROUND THROUGH SILICON VIAS
30
Patent #:
Issue Dt:
04/04/2017
Application #:
14692359
Filing Dt:
04/21/2015
Publication #:
Pub Dt:
02/04/2016
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY CHEMOEPITAXY
31
Patent #:
Issue Dt:
09/05/2017
Application #:
14692881
Filing Dt:
04/22/2015
Publication #:
Pub Dt:
10/27/2016
Title:
HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
32
Patent #:
Issue Dt:
10/18/2016
Application #:
14693978
Filing Dt:
04/23/2015
Publication #:
Pub Dt:
06/09/2016
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SUCH A SEMICONDUCTOR DEVICE STRUCTURE
33
Patent #:
Issue Dt:
06/07/2016
Application #:
14694243
Filing Dt:
04/23/2015
Publication #:
Pub Dt:
08/13/2015
Title:
METHOD OF MANUFACTURING A FINFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FINFET DEVICE FORMED BY SAME
34
Patent #:
Issue Dt:
01/17/2017
Application #:
14694265
Filing Dt:
04/23/2015
Publication #:
Pub Dt:
09/24/2015
Title:
BURIED WAVEGUIDE PHOTODETECTOR
35
Patent #:
Issue Dt:
08/23/2016
Application #:
14694276
Filing Dt:
04/23/2015
Title:
METHODS OF FACILITATING FABRICATING TRANSISTORS
36
Patent #:
Issue Dt:
12/29/2015
Application #:
14694831
Filing Dt:
04/23/2015
Publication #:
Pub Dt:
08/13/2015
Title:
BOOSTING DECOMPRESSION IN THE PRESENCE OF REOCCURRING HUFFMAN TREES
37
Patent #:
Issue Dt:
01/24/2017
Application #:
14695091
Filing Dt:
04/24/2015
Publication #:
Pub Dt:
10/27/2016
Title:
SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERATURE USING TIMING CLOSURE-BASED ADAPTIVE FREQUENCY SCALING
38
Patent #:
Issue Dt:
09/12/2017
Application #:
14695112
Filing Dt:
04/24/2015
Publication #:
Pub Dt:
10/27/2016
Title:
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING
39
Patent #:
Issue Dt:
01/24/2017
Application #:
14695232
Filing Dt:
04/24/2015
Publication #:
Pub Dt:
10/27/2016
Title:
METHOD OF MANUFACTURING P-CHANNEL FET DEVICE WITH SIGE CHANNEL
40
Patent #:
Issue Dt:
07/24/2018
Application #:
14695411
Filing Dt:
04/24/2015
Publication #:
Pub Dt:
10/27/2016
Title:
FINFET DEVICES HAVING ASYMMETRICAL EPITAXIALLY-GROWN SOURCE AND DRAIN REGIONS AND METHODS OF FORMING THE SAME
41
Patent #:
Issue Dt:
03/15/2016
Application #:
14695965
Filing Dt:
04/24/2015
Publication #:
Pub Dt:
08/20/2015
Title:
INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES
42
Patent #:
Issue Dt:
07/12/2016
Application #:
14696034
Filing Dt:
04/24/2015
Publication #:
Pub Dt:
08/13/2015
Title:
DOUBLE MIRROR STRUCTURE FOR WAVELENGTH DIVISION MULTIPLEXING WITH POLYMER WAVEGUIDES
43
Patent #:
Issue Dt:
08/02/2016
Application #:
14696534
Filing Dt:
04/27/2015
Publication #:
Pub Dt:
08/13/2015
Title:
FINFET DEVICE
44
Patent #:
Issue Dt:
02/09/2016
Application #:
14696605
Filing Dt:
04/27/2015
Publication #:
Pub Dt:
08/20/2015
Title:
A MANUFACTURING PROCESS FOR FINFET DEVICE
45
Patent #:
Issue Dt:
08/02/2016
Application #:
14696684
Filing Dt:
04/27/2015
Title:
METHOD FOR CREATING SELF-ALIGNED COMPACT CONTACTS IN AN IC DEVICE MEETING FABRICATION SPACING CONSTRAINTS
46
Patent #:
Issue Dt:
07/12/2016
Application #:
14696693
Filing Dt:
04/27/2015
Publication #:
Pub Dt:
08/13/2015
Title:
MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
47
Patent #:
Issue Dt:
11/01/2016
Application #:
14696736
Filing Dt:
04/27/2015
Publication #:
Pub Dt:
09/17/2015
Title:
MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
48
Patent #:
Issue Dt:
10/18/2016
Application #:
14696843
Filing Dt:
04/27/2015
Publication #:
Pub Dt:
08/13/2015
Title:
WAVELENGTH DIVISION MULTIPLEXING WITH MULTI-CORE FIBER
49
Patent #:
Issue Dt:
10/25/2016
Application #:
14696954
Filing Dt:
04/27/2015
Publication #:
Pub Dt:
10/27/2016
Title:
SEMICONDUCTOR DEVICE STRUCTURES WITH SELF-ALIGNED FIN STRUCTURE(S) AND FABRICATION METHODS THEREOF
50
Patent #:
Issue Dt:
05/10/2016
Application #:
14697670
Filing Dt:
04/28/2015
Publication #:
Pub Dt:
08/27/2015
Title:
SEMICONDUCTOR DEVICE INCLUDING FINFET AND DIODE HAVING REDUCED DEFECTS IN DEPLETION REGION
51
Patent #:
Issue Dt:
07/12/2016
Application #:
14698066
Filing Dt:
04/28/2015
Title:
MEMORY BIT CELL FOR REDUCED LAYOUT AREA
52
Patent #:
Issue Dt:
08/23/2016
Application #:
14698103
Filing Dt:
04/28/2015
Publication #:
Pub Dt:
08/13/2015
Title:
REDUCED THRESHOLD VOLTAGE-WIDTH DEPENDENCY IN TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES
53
Patent #:
Issue Dt:
10/18/2016
Application #:
14698206
Filing Dt:
04/28/2015
Publication #:
Pub Dt:
08/13/2015
Title:
SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS
54
Patent #:
Issue Dt:
08/30/2016
Application #:
14698948
Filing Dt:
04/29/2015
Title:
ALTERNATE DUAL DAMASCENE METHOD FOR FORMING INTERCONNECTS
55
Patent #:
Issue Dt:
06/27/2017
Application #:
14699015
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
11/03/2016
Title:
PHOTODETECTOR AND METHODS OF MANUFACTURE
56
Patent #:
Issue Dt:
08/30/2016
Application #:
14699034
Filing Dt:
04/29/2015
Title:
SERIES-CONNECTED NANOWIRE STRUCTURES
57
Patent #:
Issue Dt:
05/24/2016
Application #:
14699083
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
06/16/2016
Title:
INTEGRATED CIRCUITS WITH CAPACITORS AND METHODS OF PRODUCING THE SAME
58
Patent #:
Issue Dt:
05/09/2017
Application #:
14699122
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
11/03/2016
Title:
BLOCK LEVEL PATTERNING PROCESS
59
Patent #:
Issue Dt:
11/28/2017
Application #:
14699134
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
11/03/2016
Title:
ELECTROSTATIC DISCHARGE (ESD) PROTECTION TRANSISTOR DEVICES AND INTEGRATED CIRCUITS WITH ELECTROSTATIC DISCHARGE PROTECTION TRANSISTOR DEVICES
60
Patent #:
Issue Dt:
08/23/2016
Application #:
14699154
Filing Dt:
04/29/2015
Title:
CUT FIRST ALTERNATIVE FOR 2D SELF-ALIGNED VIA
61
Patent #:
Issue Dt:
11/01/2016
Application #:
14699427
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
08/20/2015
Title:
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
62
Patent #:
Issue Dt:
01/12/2016
Application #:
14699543
Filing Dt:
04/29/2015
Title:
SEMICONDUCTOR DEVICE AND METHODS OF FORMING FINS AND GATES WITH ULTRAVIOLET CURING
63
Patent #:
Issue Dt:
07/12/2016
Application #:
14699557
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
10/08/2015
Title:
COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID
64
Patent #:
Issue Dt:
05/10/2016
Application #:
14699580
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
08/27/2015
Title:
TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR
65
Patent #:
Issue Dt:
09/13/2016
Application #:
14699705
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
06/30/2016
Title:
METHODS FOR RETARGETING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING RETARGETED LAYOUTS
66
Patent #:
Issue Dt:
10/11/2016
Application #:
14699746
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
08/27/2015
Title:
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
67
Patent #:
Issue Dt:
07/12/2016
Application #:
14699843
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
08/27/2015
Title:
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
68
Patent #:
Issue Dt:
05/10/2016
Application #:
14699920
Filing Dt:
04/29/2015
Publication #:
Pub Dt:
08/20/2015
Title:
PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT
69
Patent #:
Issue Dt:
05/31/2016
Application #:
14700147
Filing Dt:
04/30/2015
Publication #:
Pub Dt:
09/17/2015
Title:
INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES
70
Patent #:
Issue Dt:
10/17/2017
Application #:
14700402
Filing Dt:
04/30/2015
Publication #:
Pub Dt:
11/03/2016
Title:
ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD
71
Patent #:
NONE
Issue Dt:
Application #:
14700639
Filing Dt:
04/30/2015
Publication #:
Pub Dt:
11/03/2016
Title:
METHOD AND APPARATUS FOR DETECTION OF FAILURES IN UNDER-FILL LAYERS IN INTEGRATED CIRCUIT ASSEMBLIES
72
Patent #:
Issue Dt:
03/29/2016
Application #:
14700744
Filing Dt:
04/30/2015
Publication #:
Pub Dt:
08/27/2015
Title:
TUNABLE FILTER STRUCTURES AND DESIGN STRUCTURES
73
Patent #:
Issue Dt:
11/15/2016
Application #:
14700748
Filing Dt:
04/30/2015
Publication #:
Pub Dt:
11/03/2016
Title:
SEMICONDUCTOR STRUCTURE HAVING LOGIC REGION AND ANALOG REGION
74
Patent #:
Issue Dt:
02/07/2017
Application #:
14700850
Filing Dt:
04/30/2015
Publication #:
Pub Dt:
11/19/2015
Title:
AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
75
Patent #:
Issue Dt:
05/15/2018
Application #:
14701371
Filing Dt:
04/30/2015
Publication #:
Pub Dt:
01/14/2016
Title:
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
76
Patent #:
Issue Dt:
03/15/2016
Application #:
14701910
Filing Dt:
05/01/2015
Publication #:
Pub Dt:
10/15/2015
Title:
PROVIDING ACCESS CONTROL FOR PUBLIC AND PRIVATE DOCUMENT FIELDS
77
Patent #:
Issue Dt:
02/21/2017
Application #:
14702984
Filing Dt:
05/04/2015
Publication #:
Pub Dt:
11/10/2016
Title:
SILVER ALLOYING POST-CHIP JOIN
78
Patent #:
Issue Dt:
06/06/2017
Application #:
14703179
Filing Dt:
05/04/2015
Publication #:
Pub Dt:
11/10/2016
Title:
METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOUT OF AN INTEGRATED CIRCUIT
79
Patent #:
Issue Dt:
06/06/2017
Application #:
14704488
Filing Dt:
05/05/2015
Publication #:
Pub Dt:
11/10/2016
Title:
METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE
80
Patent #:
Issue Dt:
06/06/2017
Application #:
14705065
Filing Dt:
05/06/2015
Publication #:
Pub Dt:
11/10/2016
Title:
DETECTION OF FOREIGN MATERIAL ON A SUBSTRATE CHUCK
81
Patent #:
Issue Dt:
01/19/2016
Application #:
14705397
Filing Dt:
05/06/2015
Publication #:
Pub Dt:
08/20/2015
Title:
ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUTOR DEVICES
82
Patent #:
Issue Dt:
01/12/2016
Application #:
14705425
Filing Dt:
05/06/2015
Publication #:
Pub Dt:
08/20/2015
Title:
HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS
83
Patent #:
Issue Dt:
02/21/2017
Application #:
14707442
Filing Dt:
05/08/2015
Publication #:
Pub Dt:
11/10/2016
Title:
INDUCING DEVICE VARIATION FOR SECURITY APPLICATIONS
84
Patent #:
Issue Dt:
06/07/2016
Application #:
14707443
Filing Dt:
05/08/2015
Title:
2D SELF-ALIGNED VIA FIRST PROCESS FLOW
85
Patent #:
Issue Dt:
02/21/2017
Application #:
14707923
Filing Dt:
05/08/2015
Publication #:
Pub Dt:
08/27/2015
Title:
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
86
Patent #:
Issue Dt:
01/12/2016
Application #:
14708405
Filing Dt:
05/11/2015
Publication #:
Pub Dt:
09/03/2015
Title:
METHODS OF FORMING REPLACEMENT GATE STRUCTURES AND FINS ON FINFET DEVICES AND THE RESULTING DEVICES
87
Patent #:
Issue Dt:
10/18/2016
Application #:
14708753
Filing Dt:
05/11/2015
Publication #:
Pub Dt:
08/27/2015
Title:
PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
88
Patent #:
Issue Dt:
11/10/2015
Application #:
14708755
Filing Dt:
05/11/2015
Publication #:
Pub Dt:
08/27/2015
Title:
INTEGRATED CIRCUIT STRUCTURES HAVING OFF-AXIS IN-HOLE CAPACITOR
89
Patent #:
Issue Dt:
03/07/2017
Application #:
14709889
Filing Dt:
05/12/2015
Publication #:
Pub Dt:
11/17/2016
Title:
ALIGNMENT MONITORING STRUCTURE AND ALIGNMENT MONITORING METHOD FOR SEMICONDUCTOR DEVICES
90
Patent #:
Issue Dt:
02/14/2017
Application #:
14709924
Filing Dt:
05/12/2015
Publication #:
Pub Dt:
11/19/2015
Title:
ARTICLES INCLUDING BONDED METAL STRUCTURES AND METHODS OF PREPARING THE SAME
91
Patent #:
Issue Dt:
09/20/2016
Application #:
14710053
Filing Dt:
05/12/2015
Title:
METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
92
Patent #:
Issue Dt:
11/08/2016
Application #:
14710894
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
11/17/2016
Title:
VIA FORMATION USING SIDEWALL IMAGE TRANSFER PROCESS TO DEFINE LATERAL DIMENSION
93
Patent #:
Issue Dt:
12/15/2015
Application #:
14710935
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
08/27/2015
Title:
METHOD OF SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES
94
Patent #:
Issue Dt:
01/12/2016
Application #:
14711029
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
08/27/2015
Title:
SEMICONDUCTOR DEVICE WITH FIELD-INDUCING STRUCTURE
95
Patent #:
Issue Dt:
12/29/2015
Application #:
14711069
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
08/27/2015
Title:
SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES
96
Patent #:
Issue Dt:
01/10/2017
Application #:
14711109
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
09/10/2015
Title:
CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP
97
Patent #:
Issue Dt:
03/01/2016
Application #:
14711119
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
09/03/2015
Title:
THICK AND THIN DATA VOLUME MANAGEMENT
98
Patent #:
Issue Dt:
08/23/2016
Application #:
14711196
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
09/10/2015
Title:
SEMICONDUCTOR DEVICE WITH LOW-K SPACERS
99
Patent #:
Issue Dt:
12/22/2015
Application #:
14711377
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
09/03/2015
Title:
METHOD OF USING AN EUV MASK DURING EUV PHOTOLITHOGRAPHY PROCESSES
100
Patent #:
Issue Dt:
12/20/2016
Application #:
14711380
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
11/17/2016
Title:
FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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