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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 132 of 146
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Patent #:	9425315	Issue Dt:	08/23/2016	Application #:	14811921	Filing Dt:	07/29/2015
Publication #:	US20160064544	Pub Dt:	03/03/2016
Title:	FINFET SEMICONDUCTOR DEVICE WITH ISOLATED FINS MADE OF ALTERNATIVE CHANNEL MATERIALS

Patent #:	9318342	Issue Dt:	04/19/2016	Application #:	14811987	Filing Dt:	07/29/2015
Publication #:	US20150340238	Pub Dt:	11/26/2015
Title:	METHODS OF REMOVING FINS FOR FINFET SEMICONDUCTOR DEVICES

Patent #:	10170330	Issue Dt:	01/01/2019	Application #:	14812046	Filing Dt:	07/29/2015
Publication #:	US20160163559	Pub Dt:	06/09/2016
Title:	METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE

Patent #:	9496354	Issue Dt:	11/15/2016	Application #:	14812150	Filing Dt:	07/29/2015
Publication #:	US20150333136	Pub Dt:	11/19/2015
Title:	Semiconductor Devices with Dummy Gate Structures Partially on Isolation Regions

Patent #:	9608110	Issue Dt:	03/28/2017	Application #:	14812245	Filing Dt:	07/29/2015
Publication #:	US20160111549	Pub Dt:	04/21/2016
Title:	METHODS OF FORMING A SEMICONDUCTOR CIRCUIT ELEMENT AND SEMICONDUCTOR CIRCUIT ELEMENT

Patent #:	9735064	Issue Dt:	08/15/2017	Application #:	14812317	Filing Dt:	07/29/2015
Publication #:	US20170032929	Pub Dt:	02/02/2017
Title:	CHARGE DYNAMICS EFFECT FOR DETECTION OF VOLTAGE CONTRAST DEFECT AND DETERMINATION OF SHORTING LOCATION

Patent #:	9785734	Issue Dt:	10/10/2017	Application #:	14812341	Filing Dt:	07/29/2015
Publication #:	US20170032071	Pub Dt:	02/02/2017
Title:	METHOD AND SYSTEM FOR ADJUSTING A CIRCUIT SYMBOL

Patent #:	9917195	Issue Dt:	03/13/2018	Application #:	14812425	Filing Dt:	07/29/2015
Publication #:	US20170033221	Pub Dt:	02/02/2017
Title:	HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS

Patent #:	9553194	Issue Dt:	01/24/2017	Application #:	14812653	Filing Dt:	07/29/2015
Publication #:	US20170033224	Pub Dt:	02/02/2017
Title:	METHOD FOR IMPROVED FIN PROFILE

Patent #:	9640423	Issue Dt:	05/02/2017	Application #:	14813254	Filing Dt:	07/30/2015
Publication #:	US20170033178	Pub Dt:	02/02/2017
Title:	INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION

Patent #:	9425189	Issue Dt:	08/23/2016	Application #:	14813292	Filing Dt:	07/30/2015
Title:	COMPACT FDSOI DEVICE WITH BULEX CONTACT EXTENDING THROUGH BURIED INSULATING LAYER ADJACENT GATE STRUCTURE FOR BACK-BIAS

Patent #:	9505611	Issue Dt:	11/29/2016	Application #:	14814083	Filing Dt:	07/30/2015
Title:	INTEGRATION OF ELECTROMECHANICAL AND CMOS DEVICES IN FRONT-END-OF-LINE USING REPLACEMENT METAL GATE PROCESS FLOW

Patent #:	9601495	Issue Dt:	03/21/2017	Application #:	14814322	Filing Dt:	07/30/2015
Publication #:	US20170033113	Pub Dt:	02/02/2017
Title:	THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH CO-FABRICATED ADJACENT CAPACITOR

Patent #:	9608112	Issue Dt:	03/28/2017	Application #:	14816337	Filing Dt:	08/03/2015
Publication #:	US20170040450	Pub Dt:	02/09/2017
Title:	BULEX CONTACTS IN ADVANCED FDSOI TECHNIQUES

Patent #:	10121711	Issue Dt:	11/06/2018	Application #:	14816708	Filing Dt:	08/03/2015
Publication #:	US20150340296	Pub Dt:	11/26/2015
Title:	PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE

Patent #:	9548388	Issue Dt:	01/17/2017	Application #:	14817504	Filing Dt:	08/04/2015
Publication #:	US20170040453	Pub Dt:	02/09/2017
Title:	FORMING FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9362403	Issue Dt:	06/07/2016	Application #:	14817628	Filing Dt:	08/04/2015
Publication #:	US20150340452	Pub Dt:	11/26/2015
Title:	BURIED FIN CONTACT STRUCTURES ON FINFET SEMICONDUCTOR DEVICES

Patent #:	9881738	Issue Dt:	01/30/2018	Application #:	14818342	Filing Dt:	08/05/2015
Publication #:	US20170040110	Pub Dt:	02/09/2017
Title:	CAPACITOR STRUCTURES WITH EMBEDDED ELECTRODES AND FABRICATION METHODS THEREOF

Patent #:	9460996	Issue Dt:	10/04/2016	Application #:	14818351	Filing Dt:	08/05/2015
Title:	INTEGRATED DEVICE WITH INDUCTIVE AND CAPACITIVE PORTIONS AND FABRICATION METHODS

Patent #:	9613861	Issue Dt:	04/04/2017	Application #:	14818419	Filing Dt:	08/05/2015
Publication #:	US20170040216	Pub Dt:	02/09/2017
Title:	DAMASCENE WIRES WITH TOP VIA STRUCTURES

Patent #:	9425194	Issue Dt:	08/23/2016	Application #:	14819646	Filing Dt:	08/06/2015
Publication #:	US20150340362	Pub Dt:	11/26/2015
Title:	TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS

Patent #:	9437282	Issue Dt:	09/06/2016	Application #:	14819784	Filing Dt:	08/06/2015
Title:	HIGH PERFORMANCE SENSE AMPLIFIER

Patent #:	9478538	Issue Dt:	10/25/2016	Application #:	14820661	Filing Dt:	08/07/2015
Title:	METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

Patent #:	9875940	Issue Dt:	01/23/2018	Application #:	14820701	Filing Dt:	08/07/2015
Publication #:	US20170040220	Pub Dt:	02/09/2017
Title:	METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

Patent #:	9337338	Issue Dt:	05/10/2016	Application #:	14820938	Filing Dt:	08/07/2015
Publication #:	US20150349089	Pub Dt:	12/03/2015
Title:	TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION

Patent #:	9711422	Issue Dt:	07/18/2017	Application #:	14821201	Filing Dt:	08/07/2015
Publication #:	US20150355253	Pub Dt:	12/10/2015
Title:	VISUALLY DETECTING ELECTROSTATIC DISCHARGE EVENTS

Patent #:	9758365	Issue Dt:	09/12/2017	Application #:	14821997	Filing Dt:	08/10/2015
Publication #:	US20150344293	Pub Dt:	12/03/2015
Title:	INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE

Patent #:	9768058	Issue Dt:	09/19/2017	Application #:	14822258	Filing Dt:	08/10/2015
Publication #:	US20170047242	Pub Dt:	02/16/2017
Title:	METHODS OF FORMING AIR GAPS IN METALLIZATION LAYERS ON INTEGRATED CIRCUIT PRODUCTS

Patent #:	9653356	Issue Dt:	05/16/2017	Application #:	14822340	Filing Dt:	08/10/2015
Publication #:	US20170047253	Pub Dt:	02/16/2017
Title:	METHODS OF FORMING SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES

Patent #:	9461111	Issue Dt:	10/04/2016	Application #:	14822345	Filing Dt:	08/10/2015
Publication #:	US20150349054	Pub Dt:	12/03/2015
Title:	DOUBLE/MULTIPLE FIN STRUCTURE FOR FINFET DEVICES

Patent #:	9570573	Issue Dt:	02/14/2017	Application #:	14822490	Filing Dt:	08/10/2015
Publication #:	US20170047418	Pub Dt:	02/16/2017
Title:	SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER

Patent #:	9595493	Issue Dt:	03/14/2017	Application #:	14822597	Filing Dt:	08/10/2015
Publication #:	US20170047282	Pub Dt:	02/16/2017
Title:	REDUCING LINER CORROSION DURING METALLIZATION OF SEMICONDUCTOR DEVICES

Patent #:	9397049	Issue Dt:	07/19/2016	Application #:	14822654	Filing Dt:	08/10/2015
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	9263516	Issue Dt:	02/16/2016	Application #:	14823319	Filing Dt:	08/11/2015
Publication #:	US20160049468	Pub Dt:	02/18/2016
Title:	PRODUCT COMPRISED OF FINFET DEVICES WITH SINGLE DIFFUSION BREAK ISOLATION STRUCTURES

Patent #:	9613909	Issue Dt:	04/04/2017	Application #:	14824181	Filing Dt:	08/12/2015
Publication #:	US20170047290	Pub Dt:	02/16/2017
Title:	METHODS AND DEVICES FOR METAL FILLING PROCESSES

Patent #:	10158003	Issue Dt:	12/18/2018	Application #:	14824349	Filing Dt:	08/12/2015
Publication #:	US20170047411	Pub Dt:	02/16/2017
Title:	EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS

Patent #:	9837277	Issue Dt:	12/05/2017	Application #:	14824360	Filing Dt:	08/12/2015
Publication #:	US20170047256	Pub Dt:	02/16/2017
Title:	FORMING A CONTACT FOR A TALL FIN TRANSISTOR

Patent #:	NONE	Issue Dt:		Application #:	14824361	Filing Dt:	08/12/2015
Publication #:	US20150348830	Pub Dt:	12/03/2015
Title:	SHALLOW TRENCH ISOLATION

Patent #:	9472490	Issue Dt:	10/18/2016	Application #:	14824409	Filing Dt:	08/12/2015
Title:	IC STRUCTURE WITH RECESSED SOLDER BUMP AREA AND METHODS OF FORMING SAME

Patent #:	9466680	Issue Dt:	10/11/2016	Application #:	14825375	Filing Dt:	08/13/2015
Publication #:	US20150349075	Pub Dt:	12/03/2015
Title:	INTEGRATED MULTIPLE GATE LENGTH SEMICONDUCTOR DEVICE INCLUDING SELF-ALIGNED CONTACTS

Patent #:	9577042	Issue Dt:	02/21/2017	Application #:	14825949	Filing Dt:	08/13/2015
Publication #:	US20170047404	Pub Dt:	02/16/2017
Title:	SEMICONDUCTOR STRUCTURE WITH MULTILAYER III-V HETEROSTRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	14826250	Filing Dt:	08/14/2015
Publication #:	US20170046470	Pub Dt:	02/16/2017
Title:	PROCESS DESIGN KIT FOR EFFICIENT AND ACCURATE MISMATCH SIMULATION OF ANALOG CIRCUITS

Patent #:	9330982	Issue Dt:	05/03/2016	Application #:	14826276	Filing Dt:	08/14/2015
Title:	SEMICONDUCTOR DEVICE WITH DIFFUSION BARRIER FILM AND METHOD OF MANUFACTURING THE SAME

Patent #:	9373690	Issue Dt:	06/21/2016	Application #:	14826466	Filing Dt:	08/14/2015
Publication #:	US20150349076	Pub Dt:	12/03/2015
Title:	VARIABLE LENGTH MULTI-CHANNEL REPLACEMENT METAL GATE INCLUDING SILICON HARD MASK

Patent #:	9349864	Issue Dt:	05/24/2016	Application #:	14826477	Filing Dt:	08/14/2015
Title:	METHODS FOR SELECTIVELY FORMING A LAYER OF INCREASED DOPANT CONCENTRATION

Patent #:	9647086	Issue Dt:	05/09/2017	Application #:	14826803	Filing Dt:	08/14/2015
Publication #:	US20170047425	Pub Dt:	02/16/2017
Title:	EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL

Patent #:	9653573	Issue Dt:	05/16/2017	Application #:	14827510	Filing Dt:	08/17/2015
Publication #:	US20150357434	Pub Dt:	12/10/2015
Title:	REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL

Patent #:	9741623	Issue Dt:	08/22/2017	Application #:	14828652	Filing Dt:	08/18/2015
Publication #:	US20170053835	Pub Dt:	02/23/2017
Title:	DUAL LINER CMOS INTEGRATION METHODS FOR FINFET DEVICES

Patent #:	9589658	Issue Dt:	03/07/2017	Application #:	14828770	Filing Dt:	08/18/2015
Publication #:	US20170053705	Pub Dt:	02/23/2017
Title:	DISTURB FREE BITCELL AND ARRAY

Patent #:	9905671	Issue Dt:	02/27/2018	Application #:	14829843	Filing Dt:	08/19/2015
Publication #:	US20170053997	Pub Dt:	02/23/2017
Title:	FORMING A GATE CONTACT IN THE ACTIVE AREA

Patent #:	10134585	Issue Dt:	11/20/2018	Application #:	14830131	Filing Dt:	08/19/2015
Publication #:	US20160056033	Pub Dt:	02/25/2016
Title:	LOW TEMPERATURE ATOMIC LAYER DEPOSITION OF OXIDES ON COMPOUND SEMICONDUCTORS

Patent #:	NONE	Issue Dt:		Application #:	14830214	Filing Dt:	08/19/2015
Publication #:	US20170052014	Pub Dt:	02/23/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR PASSIVE DIE STRAIN MEASUREMENT

Patent #:	9735063	Issue Dt:	08/15/2017	Application #:	14830245	Filing Dt:	08/19/2015
Publication #:	US20170053836	Pub Dt:	02/23/2017
Title:	METHODS FOR FORMING FIN STRUCTURES

Patent #:	9647165	Issue Dt:	05/09/2017	Application #:	14830870	Filing Dt:	08/20/2015
Publication #:	US20170054049	Pub Dt:	02/23/2017
Title:	GERMANIUM PHOTODETECTOR WITH SOI DOPING SOURCE

Patent #:	NONE	Issue Dt:		Application #:	14831920	Filing Dt:	08/21/2015
Publication #:	US20170052458	Pub Dt:	02/23/2017
Title:	DIFFRACTIVE OVERLAY MARK

Patent #:	9825093	Issue Dt:	11/21/2017	Application #:	14832108	Filing Dt:	08/21/2015
Publication #:	US20170053966	Pub Dt:	02/23/2017
Title:	FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS

Patent #:	9570156	Issue Dt:	02/14/2017	Application #:	14832127	Filing Dt:	08/21/2015
Publication #:	US20170053694	Pub Dt:	02/23/2017
Title:	DATA AWARE WRITE SCHEME FOR SRAM

Patent #:	9349749	Issue Dt:	05/24/2016	Application #:	14832166	Filing Dt:	08/21/2015
Publication #:	US20150364491	Pub Dt:	12/17/2015
Title:	SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY

Patent #:	NONE	Issue Dt:		Application #:	14832246	Filing Dt:	08/21/2015
Publication #:	US20170053794	Pub Dt:	02/23/2017
Title:	AUTOMATIC CONTROL OF SPRAY BAR AND UNITS FOR CHEMICAL MECHANICAL POLISHING IN-SITU BRUSH CLEANING

Patent #:	9349598	Issue Dt:	05/24/2016	Application #:	14832530	Filing Dt:	08/21/2015
Publication #:	US20150357409	Pub Dt:	12/10/2015
Title:	GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN

Patent #:	NONE	Issue Dt:		Application #:	14833209	Filing Dt:	08/24/2015
Publication #:	US20170062399	Pub Dt:	03/02/2017
Title:	METHOD AND STRUCTURE FOR LOW-K FACE-TO-FACE BONDED WAFER DICING

Patent #:	9627272	Issue Dt:	04/18/2017	Application #:	14833813	Filing Dt:	08/24/2015
Publication #:	US20170062281	Pub Dt:	03/02/2017
Title:	PATTERNING SCHEME TO MINIMIZE DRY/WETS STRIP INDUCED DEVICE DEGRADATION

Patent #:	9583557	Issue Dt:	02/28/2017	Application #:	14835278	Filing Dt:	08/25/2015
Publication #:	US20160064472	Pub Dt:	03/03/2016
Title:	INTEGRATED CIRCUITS INCLUDING A MIMCAP DEVICE AND METHODS OF FORMING THE SAME FOR LONG AND CONTROLLABLE RELIABILITY LIFETIME

Patent #:	9385189	Issue Dt:	07/05/2016	Application #:	14835786	Filing Dt:	08/26/2015
Title:	FIN LINER INTEGRATION UNDER AGGRESSIVE PITCH

Patent #:	9431300	Issue Dt:	08/30/2016	Application #:	14837222	Filing Dt:	08/27/2015
Title:	MOL ARCHITECTURE ENABLING ULTRA-REGULAR CROSS COUPLE

Patent #:	9679959	Issue Dt:	06/13/2017	Application #:	14837288	Filing Dt:	08/27/2015
Publication #:	US20150364540	Pub Dt:	12/17/2015
Title:	CAPACITOR AND CONTACT STRUCTURES, AND FORMATION PROCESSES THEREOF

Patent #:	9589911	Issue Dt:	03/07/2017	Application #:	14837461	Filing Dt:	08/27/2015
Publication #:	US20170062354	Pub Dt:	03/02/2017
Title:	INTEGRATED CIRCUIT STRUCTURE WITH METAL CRACK STOP AND METHODS OF FORMING SAME

Patent #:	9589912	Issue Dt:	03/07/2017	Application #:	14837737	Filing Dt:	08/27/2015
Publication #:	US20170062355	Pub Dt:	03/02/2017
Title:	INTEGRATED CIRCUIT STRUCTURE WITH CRACK STOP AND METHOD OF FORMING SAME

Patent #:	9466753	Issue Dt:	10/11/2016	Application #:	14837812	Filing Dt:	08/27/2015
Title:	PHOTODETECTOR METHODS AND PHOTODETECTOR STRUCTURES

Patent #:	9330965	Issue Dt:	05/03/2016	Application #:	14837827	Filing Dt:	08/27/2015
Publication #:	US20150371896	Pub Dt:	12/24/2015
Title:	DOUBLE SELF ALIGNED VIA PATTERNING

Patent #:	9257334	Issue Dt:	02/09/2016	Application #:	14837865	Filing Dt:	08/27/2015
Publication #:	US20150364372	Pub Dt:	12/17/2015
Title:	DOUBLE SELF-ALIGNED VIA PATTERNING

Patent #:	NONE	Issue Dt:		Application #:	14838215	Filing Dt:	08/27/2015
Publication #:	US20170063357	Pub Dt:	03/02/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR USING TUNABLE TIMING CIRCUITS FOR FDSOI TECHNOLOGY

Patent #:	9613898	Issue Dt:	04/04/2017	Application #:	14838554	Filing Dt:	08/28/2015
Publication #:	US20170062333	Pub Dt:	03/02/2017
Title:	RAISED E-FUSE

Patent #:	10042969	Issue Dt:	08/07/2018	Application #:	14838705	Filing Dt:	08/28/2015
Publication #:	US20170061062	Pub Dt:	03/02/2017
Title:	RELIABILITY OF AN ELECTRONIC DEVICE

Patent #:	9698101	Issue Dt:	07/04/2017	Application #:	14839108	Filing Dt:	08/28/2015
Publication #:	US20170062325	Pub Dt:	03/02/2017
Title:	SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY

Patent #:	9564486	Issue Dt:	02/07/2017	Application #:	14839378	Filing Dt:	08/28/2015
Publication #:	US20150372080	Pub Dt:	12/24/2015
Title:	SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET

Patent #:	9817927	Issue Dt:	11/14/2017	Application #:	14841037	Filing Dt:	08/31/2015
Publication #:	US20170061044	Pub Dt:	03/02/2017
Title:	HARD MASK ETCH AND DIELECTRIC ETCH AWARE OVERLAP FOR VIA AND METAL LAYERS

Patent #:	9659785	Issue Dt:	05/23/2017	Application #:	14841951	Filing Dt:	09/01/2015
Publication #:	US20170062233	Pub Dt:	03/02/2017
Title:	FIN CUT FOR TAPER DEVICE

Patent #:	9666791	Issue Dt:	05/30/2017	Application #:	14841997	Filing Dt:	09/01/2015
Publication #:	US20160141489	Pub Dt:	05/19/2016
Title:	TOPOLOGICAL METHOD TO BUILD SELF-ALIGNED MTJ WITHOUT A MASK

Patent #:	9564447	Issue Dt:	02/07/2017	Application #:	14842345	Filing Dt:	09/01/2015
Publication #:	US20170062442	Pub Dt:	03/02/2017
Title:	METHODS FOR FABRICATING PROGRAMMABLE DEVICES AND RELATED STRUCTURES

Patent #:	9263290	Issue Dt:	02/16/2016	Application #:	14843085	Filing Dt:	09/02/2015
Publication #:	US20150380262	Pub Dt:	12/31/2015
Title:	SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH

Patent #:	9741625	Issue Dt:	08/22/2017	Application #:	14844163	Filing Dt:	09/03/2015
Publication #:	US20170069550	Pub Dt:	03/09/2017
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH STI STRUCTURES ON AN SOI SUBSTRATE

Patent #:	9385124	Issue Dt:	07/05/2016	Application #:	14845499	Filing Dt:	09/04/2015
Title:	METHODS OF FORMING REDUCED THICKNESS SPACERS IN CMOS BASED INTEGRATED CIRCUIT PRODUCTS

Patent #:	9704759	Issue Dt:	07/11/2017	Application #:	14845543	Filing Dt:	09/04/2015
Publication #:	US20170069547	Pub Dt:	03/09/2017
Title:	METHODS OF FORMING CMOS BASED INTEGRATED CIRCUIT PRODUCTS USING DISPOSABLE SPACERS

Patent #:	10038096	Issue Dt:	07/31/2018	Application #:	14847462	Filing Dt:	09/08/2015
Publication #:	US20170069759	Pub Dt:	03/09/2017
Title:	THREE-DIMENSIONAL FINFET TRANSISTOR WITH PORTION(S) OF THE FIN CHANNEL REMOVED IN GATE-LAST FLOW

Patent #:	9418935	Issue Dt:	08/16/2016	Application #:	14848558	Filing Dt:	09/09/2015
Title:	INTEGRATED CIRCUIT LINE ENDS FORMED USING ADDITIVE PROCESSING

Patent #:	10048311	Issue Dt:	08/14/2018	Application #:	14848804	Filing Dt:	09/09/2015
Publication #:	US20170067955	Pub Dt:	03/09/2017
Title:	DETECTION OF GATE-TO-SOURCE/DRAIN SHORTS

Patent #:	9564358	Issue Dt:	02/07/2017	Application #:	14849269	Filing Dt:	09/09/2015
Title:	FORMING RELIABLE CONTACTS ON TIGHT SEMICONDUCTOR PITCH

Patent #:	9478622	Issue Dt:	10/25/2016	Application #:	14849335	Filing Dt:	09/09/2015
Publication #:	US20150380502	Pub Dt:	12/31/2015
Title:	WRAP-AROUND CONTACT FOR FINFET

Patent #:	9589833	Issue Dt:	03/07/2017	Application #:	14850093	Filing Dt:	09/10/2015
Publication #:	US20170076978	Pub Dt:	03/16/2017
Title:	PREVENTING LEAKAGE INSIDE AIR-GAP SPACER DURING CONTACT FORMATION

Patent #:	9435947	Issue Dt:	09/06/2016	Application #:	14850381	Filing Dt:	09/10/2015
Publication #:	US20150378096	Pub Dt:	12/31/2015
Title:	INTEGRATION OF OPTICAL COMPONENTS IN INTEGRATED CIRCUITS BY SEPARATING TWO SUBSTRATES WITH AN INSULATION LAYER

Patent #:	10302414	Issue Dt:	05/28/2019	Application #:	14852897	Filing Dt:	09/14/2015
Publication #:	US20160076876	Pub Dt:	03/17/2016
Title:	SCATTEROMETRY METHOD AND SYSTEM

Patent #:	10020395	Issue Dt:	07/10/2018	Application #:	14853012	Filing Dt:	09/14/2015
Publication #:	US20170077297	Pub Dt:	03/16/2017
Title:	SEMICONDUCTOR DEVICE WITH GATE INSIDE U-SHAPED CHANNEL AND METHODS OF MAKING SUCH A DEVICE

Patent #:	9711644	Issue Dt:	07/18/2017	Application #:	14853073	Filing Dt:	09/14/2015
Publication #:	US20170077301	Pub Dt:	03/16/2017
Title:	METHODS OF MAKING SOURCE/DRAIN REGIONS POSITIONED INSIDE U-SHAPED SEMICONDUCTOR MATERIAL USING SOURCE/DRAIN PLACEHOLDER STRUCTURES

Patent #:	9590118	Issue Dt:	03/07/2017	Application #:	14853146	Filing Dt:	09/14/2015
Publication #:	US20170077314	Pub Dt:	03/16/2017
Title:	WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	10049942	Issue Dt:	08/14/2018	Application #:	14853373	Filing Dt:	09/14/2015
Publication #:	US20170076991	Pub Dt:	03/16/2017
Title:	ASYMMETRIC SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME

Patent #:	9553058	Issue Dt:	01/24/2017	Application #:	14854565	Filing Dt:	09/15/2015
Title:	WAFER BACKSIDE REDISTRIBUTION LAYER WARPAGE CONTROL

Patent #:	9412740	Issue Dt:	08/09/2016	Application #:	14855881	Filing Dt:	09/16/2015
Publication #:	US20160005733	Pub Dt:	01/07/2016
Title:	INTEGRATED CIRCUIT PRODUCT WITH A GATE HEIGHT REGISTRATION STRUCTURE

Patent #:	9903707	Issue Dt:	02/27/2018	Application #:	14857914	Filing Dt:	09/18/2015
Publication #:	US20170082423	Pub Dt:	03/23/2017
Title:	THREE-DIMENSIONAL SCATTEROMETRY FOR MEASURING DIELECTRIC THICKNESS

100

Patent #:	9508597	Issue Dt:	11/29/2016	Application #:	14858154	Filing Dt:	09/18/2015
Title:	3D FIN TUNNELING FIELD EFFECT TRANSISTOR

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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