USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 138 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146

Patent #:	NONE	Issue Dt:		Application #:	15168798	Filing Dt:	05/31/2016
Publication #:	US20170345559	Pub Dt:	11/30/2017
Title:	"Interleaved Transformer and Method of Making the Same"

Patent #:	9831174	Issue Dt:	11/28/2017	Application #:	15168899	Filing Dt:	05/31/2016
Publication #:	US20170345752	Pub Dt:	11/30/2017
Title:	DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT

Patent #:	NONE	Issue Dt:		Application #:	15168930	Filing Dt:	05/31/2016
Publication #:	US20170345766	Pub Dt:	11/30/2017
Title:	DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT WITH IMPROVED ADHESION

Patent #:	9799393	Issue Dt:	10/24/2017	Application #:	15169342	Filing Dt:	05/31/2016
Title:	METHODS, APPARATUS AND SYSTEM FOR PROVIDING NMOS-ONLY MEMORY CELLS

Patent #:	9837402	Issue Dt:	12/05/2017	Application #:	15170109	Filing Dt:	06/01/2016
Publication #:	US20170352654	Pub Dt:	12/07/2017
Title:	METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE

Patent #:	9691664	Issue Dt:	06/27/2017	Application #:	15170126	Filing Dt:	06/01/2016
Title:	DUAL THICK EG OXIDE INTEGRATION UNDER AGGRESSIVE SG FIN PITCH

Patent #:	10014299	Issue Dt:	07/03/2018	Application #:	15170134	Filing Dt:	06/01/2016
Publication #:	US20170092645	Pub Dt:	03/30/2017
Title:	FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9793341	Issue Dt:	10/17/2017	Application #:	15170224	Filing Dt:	06/01/2016
Title:	DEEP TRENCH CAPACITOR WITH METAL PLATE

Patent #:	9892970	Issue Dt:	02/13/2018	Application #:	15171314	Filing Dt:	06/02/2016
Publication #:	US20170352592	Pub Dt:	12/07/2017
Title:	INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME

Patent #:	9929085	Issue Dt:	03/27/2018	Application #:	15171320	Filing Dt:	06/02/2016
Publication #:	US20170352618	Pub Dt:	12/07/2017
Title:	INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME

Patent #:	9640636	Issue Dt:	05/02/2017	Application #:	15171795	Filing Dt:	06/02/2016
Title:	METHODS OF FORMING REPLACEMENT GATE STRUCTURES AND BOTTOM AND TOP SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE

Patent #:	9613962	Issue Dt:	04/04/2017	Application #:	15172201	Filing Dt:	06/03/2016
Publication #:	US20170062429	Pub Dt:	03/02/2017
Title:	FIN LINER INTEGRATION UNDER AGGRESSIVE PITCH

Patent #:	9530684	Issue Dt:	12/27/2016	Application #:	15172366	Filing Dt:	06/03/2016
Publication #:	US20160284586	Pub Dt:	09/29/2016
Title:	METHOD AND STRUCTURE TO SUPPRESS FINFET HEATING

Patent #:	10090240	Issue Dt:	10/02/2018	Application #:	15172551	Filing Dt:	06/03/2016
Publication #:	US20170352619	Pub Dt:	12/07/2017
Title:	INTERCONNECT STRUCTURE WITH CAPACITOR ELEMENT AND RELATED METHODS

Patent #:	9836570	Issue Dt:	12/05/2017	Application #:	15173756	Filing Dt:	06/06/2016
Publication #:	US20170351799	Pub Dt:	12/07/2017
Title:	SEMICONDUCTOR LAYOUT GENERATION

Patent #:	9780002	Issue Dt:	10/03/2017	Application #:	15173766	Filing Dt:	06/06/2016
Title:	THRESHOLD VOLTAGE AND WELL IMPLANTATION METHOD FOR SEMICONDUCTOR DEVICES

Patent #:	9859403	Issue Dt:	01/02/2018	Application #:	15174147	Filing Dt:	07/22/2016
Publication #:	US20180026118	Pub Dt:	01/25/2018
Title:	MULTIPLE STEP THIN FILM DEPOSITION METHOD FOR HIGH CONFORMALITY

Patent #:	10008500	Issue Dt:	06/26/2018	Application #:	15174273	Filing Dt:	06/06/2016
Publication #:	US20170352661	Pub Dt:	12/07/2017
Title:	SEMICONDUCTOR DEVICES

Patent #:	10146036	Issue Dt:	12/04/2018	Application #:	15175101	Filing Dt:	06/07/2016
Publication #:	US20170352145	Pub Dt:	12/07/2017
Title:	SEMICONDUCTOR WAFER INSPECTION USING CARE AREA GROUP-SPECIFIC THRESHOLD SETTINGS FOR DETECTING DEFECTS

Patent #:	9793169	Issue Dt:	10/17/2017	Application #:	15175187	Filing Dt:	06/07/2016
Title:	METHODS FOR FORMING MASK LAYERS USING A FLOWABLE CARBON-CONTAINING SILICON DIOXIDE MATERIAL

Patent #:	9892999	Issue Dt:	02/13/2018	Application #:	15175290	Filing Dt:	06/07/2016
Publication #:	US20170352611	Pub Dt:	12/07/2017
Title:	PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED DEVICE

Patent #:	9741613	Issue Dt:	08/22/2017	Application #:	15175308	Filing Dt:	06/07/2016
Title:	METHOD FOR PRODUCING SELF-ALIGNED LINE END VIAS AND RELATED DEVICE

Patent #:	9886998	Issue Dt:	02/06/2018	Application #:	15175466	Filing Dt:	06/07/2016
Publication #:	US20170352407	Pub Dt:	12/07/2017
Title:	SELF PRE-CHARGING MEMORY CIRCUITS

Patent #:	9812396	Issue Dt:	11/07/2017	Application #:	15175495	Filing Dt:	06/07/2016
Title:	INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES WITH MULTIPLE POWER RAILS AND REDUNDANCY

Patent #:	9640535	Issue Dt:	05/02/2017	Application #:	15175540	Filing Dt:	06/07/2016
Publication #:	US20160351566	Pub Dt:	12/01/2016
Title:	METHOD FOR FORMING SOURCE/DRAIN CONTACTS DURING CMOS INTEGRATION USING CONFINED EPITAXIAL GROWTH TECHNIQUES AND THE RESULTING SEMICONDUCTOR DEVICES

Patent #:	9799555	Issue Dt:	10/24/2017	Application #:	15175573	Filing Dt:	06/07/2016
Title:	COBALT INTERCONNECTS COVERED BY A METAL CAP

Patent #:	9716487	Issue Dt:	07/25/2017	Application #:	15175578	Filing Dt:	06/07/2016
Title:	LATENCY COMPENSATION NETWORK USING TIMING SLACK SENSORS

Patent #:	10078638	Issue Dt:	09/18/2018	Application #:	15175767	Filing Dt:	06/07/2016
Publication #:	US20170351666	Pub Dt:	12/07/2017
Title:	SECURE HYPER TRANSFER OF LARGE FILES

Patent #:	9735054	Issue Dt:	08/15/2017	Application #:	15175776	Filing Dt:	06/07/2016
Publication #:	US20170047252	Pub Dt:	02/16/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	9627257	Issue Dt:	04/18/2017	Application #:	15175835	Filing Dt:	06/07/2016
Publication #:	US20170047254	Pub Dt:	02/16/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	9842897	Issue Dt:	12/12/2017	Application #:	15176073	Filing Dt:	06/07/2016
Publication #:	US20160284802	Pub Dt:	09/29/2016
Title:	BULK FINFET WITH PARTIAL DIELECTRIC ISOLATION FEATURING A PUNCH-THROUGH STOPPING LAYER UNDER THE OXIDE

Patent #:	10007198	Issue Dt:	06/26/2018	Application #:	15176296	Filing Dt:	06/08/2016
Publication #:	US20170084475	Pub Dt:	03/23/2017
Title:	METHOD INCLUDING AN ADJUSTMENT OF A PLURALITY OF WAFER HANDLING ELEMENTS, SYSTEM INCLUDING A PLURALITY OF WAFER HANDLING ELEMENTS AND PHOTOLITHOGRAPHY TRACK

Patent #:	9842810	Issue Dt:	12/12/2017	Application #:	15176595	Filing Dt:	06/08/2016
Publication #:	US20170358541	Pub Dt:	12/14/2017
Title:	TILED-STRESS-ALLEVIATING PAD STRUCTURE

Patent #:	9805977	Issue Dt:	10/31/2017	Application #:	15176598	Filing Dt:	06/08/2016
Title:	INTEGRATED CIRCUIT STRUCTURE HAVING THROUGH-SILICON VIA AND METHOD OF FORMING SAME

Patent #:	NONE	Issue Dt:		Application #:	15177417	Filing Dt:	06/09/2016
Publication #:	US20170358565	Pub Dt:	12/14/2017
Title:	STANDARD CELL LAYOUT AND METHOD OF ARRANGING A PLURALITY OF STANDARD CELLS

Patent #:	9722024	Issue Dt:	08/01/2017	Application #:	15178134	Filing Dt:	06/09/2016
Title:	FORMATION OF SEMICONDUCTOR STRUCTURES EMPLOYING SELECTIVE REMOVAL OF FINS

Patent #:	9929253	Issue Dt:	03/27/2018	Application #:	15178853	Filing Dt:	06/10/2016
Publication #:	US20160284822	Pub Dt:	09/29/2016
Title:	METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWAL SPACERS FOR CONFINING EPITAXIAL GROWTH

Patent #:	10170591	Issue Dt:	01/01/2019	Application #:	15178871	Filing Dt:	06/10/2016
Publication #:	US20170358662	Pub Dt:	12/14/2017
Title:	SELF-ALIGNED FINFET FORMATION

Patent #:	9634110	Issue Dt:	04/25/2017	Application #:	15179393	Filing Dt:	06/10/2016
Publication #:	US20170084712	Pub Dt:	03/23/2017
Title:	POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	9793171	Issue Dt:	10/17/2017	Application #:	15179620	Filing Dt:	06/10/2016
Publication #:	US20160284599	Pub Dt:	09/29/2016
Title:	BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME

Patent #:	9741715	Issue Dt:	08/22/2017	Application #:	15179992	Filing Dt:	06/11/2016
Publication #:	US20170162565	Pub Dt:	06/08/2017
Title:	STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

Patent #:	9922883	Issue Dt:	03/20/2018	Application #:	15180158	Filing Dt:	06/13/2016
Publication #:	US20160293494	Pub Dt:	10/06/2016
Title:	METHOD FOR MAKING STRAINED SEMICONDUCTOR DEVICE AND RELATED METHODS

Patent #:	9559176	Issue Dt:	01/31/2017	Application #:	15180312	Filing Dt:	06/13/2016
Publication #:	US20160293718	Pub Dt:	10/06/2016
Title:	FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE METHOD AND DEVICE

Patent #:	9978622	Issue Dt:	05/22/2018	Application #:	15180392	Filing Dt:	06/13/2016
Publication #:	US20160300744	Pub Dt:	10/13/2016
Title:	MOISTURE AND/OR ELECTRICALLY CONDUCTIVE REMAINS DETECTION FOR WAFERS AFTER RINSE / DRY PROCESS

Patent #:	9842933	Issue Dt:	12/12/2017	Application #:	15180422	Filing Dt:	06/13/2016
Publication #:	US20170358687	Pub Dt:	12/14/2017
Title:	FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES

Patent #:	10355020	Issue Dt:	07/16/2019	Application #:	15180860	Filing Dt:	06/13/2016
Publication #:	US20160293761	Pub Dt:	10/06/2016
Title:	FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS

Patent #:	9917081	Issue Dt:	03/13/2018	Application #:	15181676	Filing Dt:	06/14/2016
Publication #:	US20170154883	Pub Dt:	06/01/2017
Title:	SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR

Patent #:	NONE	Issue Dt:		Application #:	15181834	Filing Dt:	06/14/2016
Publication #:	US20170358691	Pub Dt:	12/14/2017
Title:	Reconfigurable MOS Varactor

Patent #:	10355086	Issue Dt:	07/16/2019	Application #:	15181843	Filing Dt:	06/14/2016
Publication #:	US20170033197	Pub Dt:	02/02/2017
Title:	HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS

Patent #:	9634004	Issue Dt:	04/25/2017	Application #:	15181992	Filing Dt:	06/14/2016
Publication #:	US20170069627	Pub Dt:	03/09/2017
Title:	FORMING RELIABLE CONTACTS ON TIGHT SEMICONDUCTOR PITCH

Patent #:	9762245	Issue Dt:	09/12/2017	Application #:	15182068	Filing Dt:	06/14/2016
Title:	SEMICONDUCTOR STRUCTURE WITH BACK-GATE SWITCHING

Patent #:	NONE	Issue Dt:		Application #:	15182487	Filing Dt:	06/14/2016
Publication #:	US20170358585	Pub Dt:	12/14/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR FABRICATING SELF-ALIGNED CONTACT USING BLOCK-TYPE HARD MASK

Patent #:	10008408	Issue Dt:	06/26/2018	Application #:	15182794	Filing Dt:	06/15/2016
Publication #:	US20170365509	Pub Dt:	12/21/2017
Title:	DEVICES AND METHODS OF FORMING ASYMMETRIC LINE/SPACE WITH BARRIERLESS METALLIZATION

Patent #:	9876089	Issue Dt:	01/23/2018	Application #:	15183390	Filing Dt:	06/15/2016
Publication #:	US20170025526	Pub Dt:	01/26/2017
Title:	HIGH-K AND P-TYPE WORK FUNCTION METAL FIRST FABRICATION PROCESS HAVING IMPROVED ANNEALING PROCESS FLOWS

Patent #:	10095826	Issue Dt:	10/09/2018	Application #:	15184164	Filing Dt:	06/16/2016
Publication #:	US20170364626	Pub Dt:	12/21/2017
Title:	FEED-FORWARD FOR SILICON INSPECTIONS (DFM2CFM : DESIGN TO SILICON) & FEED-BACK FOR WEAKPOINT PREDICTOR DECKS (CFM2DFM : SILICON TO DESIGN) GUIDED BY MARKER CLASSIFICATION, SAMPLING, AND HIGHER DIMENSIONAL ANALYSIS

Patent #:	9691513	Issue Dt:	06/27/2017	Application #:	15185185	Filing Dt:	06/17/2016
Title:	PEDESTAL ALIGNMENT TOOL FOR AN ORIENTER PEDESTAL OF AN ION IMPLANT DEVICE

Patent #:	9634088	Issue Dt:	04/25/2017	Application #:	15185267	Filing Dt:	06/17/2016
Title:	JUNCTION FORMATION WITH REDUCED Ceff FOR 22NM FDSOI DEVICES

Patent #:	9923076	Issue Dt:	03/20/2018	Application #:	15185593	Filing Dt:	06/17/2016
Publication #:	US20170365680	Pub Dt:	12/21/2017
Title:	GATE PATTERNING FOR AC AND DC PERFORMANCE BOOST

Patent #:	9905661	Issue Dt:	02/27/2018	Application #:	15185801	Filing Dt:	06/17/2016
Publication #:	US20160293715	Pub Dt:	10/06/2016
Title:	SEMICONDUCTOR STRUCTURE HAVING SOURCE/DRAIN GOUGING IMMUNITY

Patent #:	9859006	Issue Dt:	01/02/2018	Application #:	15185956	Filing Dt:	06/17/2016
Publication #:	US20170365341	Pub Dt:	12/21/2017
Title:	ALGORITHMIC N SEARCH/M WRITE TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)

Patent #:	9929290	Issue Dt:	03/27/2018	Application #:	15187048	Filing Dt:	06/20/2016
Publication #:	US20170365725	Pub Dt:	12/21/2017
Title:	ELECTRICAL AND OPTICAL VIA CONNECTIONS ON A SAME CHIP

Patent #:	9679985	Issue Dt:	06/13/2017	Application #:	15187080	Filing Dt:	06/20/2016
Title:	DEVICES AND METHODS OF IMPROVING DEVICE PERFORMANCE THROUGH GATE CUT LAST PROCESS

Patent #:	9964847	Issue Dt:	05/08/2018	Application #:	15187126	Filing Dt:	06/20/2016
Publication #:	US20170365471	Pub Dt:	12/21/2017
Title:	MASK SUBSTRATE STRUCTURE

Patent #:	9847408	Issue Dt:	12/19/2017	Application #:	15187860	Filing Dt:	06/21/2016
Publication #:	US20170365695	Pub Dt:	12/21/2017
Title:	FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS

Patent #:	9966735	Issue Dt:	05/08/2018	Application #:	15188419	Filing Dt:	06/21/2016
Publication #:	US20160301192	Pub Dt:	10/13/2016
Title:	III-V LASERS WITH INTEGRATED SILICON PHOTONIC CIRCUITS

Patent #:	9577040	Issue Dt:	02/21/2017	Application #:	15189079	Filing Dt:	06/22/2016
Publication #:	US20160308005	Pub Dt:	10/20/2016
Title:	FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE

Patent #:	9852982	Issue Dt:	12/26/2017	Application #:	15189432	Filing Dt:	06/22/2016
Publication #:	US20170373005	Pub Dt:	12/28/2017
Title:	ANTI-FUSES WITH REDUCED PROGRAMMING VOLTAGES

Patent #:	9685529	Issue Dt:	06/20/2017	Application #:	15189476	Filing Dt:	06/22/2016
Title:	III-V NFETs INCLUDING CHANNEL BARRIER LAYERS TO REDUCE BAND-TO-BAND LEAKAGE CURRENT

Patent #:	9964605	Issue Dt:	05/08/2018	Application #:	15190323	Filing Dt:	06/23/2016
Publication #:	US20170371002	Pub Dt:	12/28/2017
Title:	METHODS FOR CROSSED-FINS FINFET DEVICE FOR SENSING AND MEASURING MAGNETIC FIELDS

Patent #:	9640765	Issue Dt:	05/02/2017	Application #:	15190365	Filing Dt:	06/23/2016
Publication #:	US20160336515	Pub Dt:	11/17/2016
Title:	CARBON NANOTUBE DEVICE

Patent #:	10797154	Issue Dt:	10/06/2020	Application #:	15190778	Filing Dt:	06/23/2016
Publication #:	US20170125292	Pub Dt:	05/04/2017
Title:	TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS

Patent #:	9853006	Issue Dt:	12/26/2017	Application #:	15191723	Filing Dt:	06/24/2016
Publication #:	US20160307860	Pub Dt:	10/20/2016
Title:	SEMICONDUCTOR DEVICE CONTACT STRUCTURE HAVING STACKED NICKEL, COPPER, AND TIN LAYERS

Patent #:	9824970	Issue Dt:	11/21/2017	Application #:	15193300	Filing Dt:	06/27/2016
Title:	METHODS THAT USE AT LEAST A DUAL DAMASCENE PROCESS AND, OPTIONALLY, A SINGLE DAMASCENE PROCESS TO FORM INTERCONNECTS WITH HYBRID METALLIZATION AND THE RESULTING STRUCTURES

Patent #:	9911634	Issue Dt:	03/06/2018	Application #:	15193502	Filing Dt:	06/27/2016
Publication #:	US20170372924	Pub Dt:	12/28/2017
Title:	SELF-CONTAINED METROLOGY WAFER CARRIER SYSTEMS

Patent #:	NONE	Issue Dt:		Application #:	15193700	Filing Dt:	06/27/2016
Publication #:	US20170373019	Pub Dt:	12/28/2017
Title:	METHOD TO MITIGATE CHIP PACKAGE INTERACTION RISK ON DIE CORNER USING REINFORCING TILES

Patent #:	9608003	Issue Dt:	03/28/2017	Application #:	15193770	Filing Dt:	06/27/2016
Publication #:	US20160307926	Pub Dt:	10/20/2016
Title:	INTEGRATED CIRCUIT PRODUCT WITH BULK AND SOI SEMICONDUCTOR DEVICES

Patent #:	9711511	Issue Dt:	07/18/2017	Application #:	15193867	Filing Dt:	06/27/2016
Title:	VERTICAL CHANNEL TRANSISTOR-BASED SEMICONDUCTOR MEMORY STRUCTURE

Patent #:	10276674	Issue Dt:	04/30/2019	Application #:	15194682	Filing Dt:	06/28/2016
Publication #:	US20170373161	Pub Dt:	12/28/2017
Title:	METHOD OF FORMING A GATE CONTACT STRUCTURE AND SOURCE/DRAIN CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE

Patent #:	10651135	Issue Dt:	05/12/2020	Application #:	15195029	Filing Dt:	06/28/2016
Publication #:	US20170373024	Pub Dt:	12/28/2017
Title:	TAMPER DETECTION FOR A CHIP PACKAGE

Patent #:	NONE	Issue Dt:		Application #:	15195988	Filing Dt:	06/28/2016
Publication #:	US20170373144	Pub Dt:	12/28/2017
Title:	NOVEL STI PROCESS FOR SDB DEVICES

Patent #:	10643893	Issue Dt:	05/05/2020	Application #:	15196335	Filing Dt:	06/29/2016
Publication #:	US20180006140	Pub Dt:	01/04/2018
Title:	SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY

Patent #:	10157827	Issue Dt:	12/18/2018	Application #:	15196371	Filing Dt:	06/29/2016
Publication #:	US20180005901	Pub Dt:	01/04/2018
Title:	SEMICONDUCTOR CONTACT

Patent #:	10024914	Issue Dt:	07/17/2018	Application #:	15196915	Filing Dt:	06/29/2016
Publication #:	US20180003768	Pub Dt:	01/04/2018
Title:	DIAGNOSING FAILURE LOCATIONS OF AN INTEGRATED CIRCUIT WITH LOGIC BUILT-IN SELF-TEST

Patent #:	9825157	Issue Dt:	11/21/2017	Application #:	15196920	Filing Dt:	06/29/2016
Title:	HETEROJUNCTION BIPOLAR TRANSISTOR WITH STRESS COMPONENT

Patent #:	9882052	Issue Dt:	01/30/2018	Application #:	15197892	Filing Dt:	06/30/2016
Publication #:	US20180006155	Pub Dt:	01/04/2018
Title:	FORMING DEFECT-FREE RELAXED SIGE FINS

Patent #:	9876077	Issue Dt:	01/23/2018	Application #:	15197944	Filing Dt:	06/30/2016
Publication #:	US20180006111	Pub Dt:	01/04/2018
Title:	METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC PRODUCTS COMPRISING FINFET DEVICES

Patent #:	10038091	Issue Dt:	07/31/2018	Application #:	15198038	Filing Dt:	06/30/2016
Publication #:	US20170317209	Pub Dt:	11/02/2017
Title:	SEMICONDUCTOR DEVICE AND METHOD

Patent #:	9887192	Issue Dt:	02/06/2018	Application #:	15198044	Filing Dt:	06/30/2016
Publication #:	US20180006023	Pub Dt:	01/04/2018
Title:	INTERCONNECTS FOR VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS

Patent #:	9929152	Issue Dt:	03/27/2018	Application #:	15198309	Filing Dt:	06/30/2016
Publication #:	US20180006024	Pub Dt:	01/04/2018
Title:	VERTICAL TRANSISTORS AND METHODS OF FORMING SAME

Patent #:	NONE	Issue Dt:		Application #:	15198570	Filing Dt:	06/30/2016
Publication #:	US20180005826	Pub Dt:	01/04/2018
Title:	FORMING A SILICON BASED LAYER IN A TRENCH TO PREVENT CORNER ROUNDING

Patent #:	10846452	Issue Dt:	11/24/2020	Application #:	15200475	Filing Dt:	07/01/2016
Publication #:	US20180004883	Pub Dt:	01/04/2018
Title:	METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING

Patent #:	10236212	Issue Dt:	03/19/2019	Application #:	15200716	Filing Dt:	07/01/2016
Publication #:	US20170125541	Pub Dt:	05/04/2017
Title:	SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

Patent #:	9966315	Issue Dt:	05/08/2018	Application #:	15201771	Filing Dt:	07/05/2016
Publication #:	US20180012813	Pub Dt:	01/11/2018
Title:	ADVANCED PROCESS CONTROL METHODS FOR PROCESS-AWARE DIMENSION TARGETING

Patent #:	NONE	Issue Dt:		Application #:	15201838	Filing Dt:	07/05/2016
Publication #:	US20160315162	Pub Dt:	10/27/2016
Title:	CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH

Patent #:	9941278	Issue Dt:	04/10/2018	Application #:	15202764	Filing Dt:	07/06/2016
Publication #:	US20180012887	Pub Dt:	01/11/2018
Title:	METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE REGION OF A SEMICONDUCTOR

Patent #:	9824921	Issue Dt:	11/21/2017	Application #:	15202817	Filing Dt:	07/06/2016
Title:	METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE A SEMICONDUCTOR ACTIVE REGION HAVING HIGH-K DIELECTRIC GATE CAPS

Patent #:	9607893	Issue Dt:	03/28/2017	Application #:	15202949	Filing Dt:	07/06/2016
Title:	METHOD OF FORMING SELF-ALIGNED METAL LINES AND VIAS

Patent #:	9966430	Issue Dt:	05/08/2018	Application #:	15202983	Filing Dt:	07/06/2016
Publication #:	US20170084690	Pub Dt:	03/23/2017
Title:	STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)

Patent #:	9818823	Issue Dt:	11/14/2017	Application #:	15202994	Filing Dt:	07/06/2016
Publication #:	US20170084756	Pub Dt:	03/23/2017
Title:	STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)

100

Patent #:	9768065	Issue Dt:	09/19/2017	Application #:	15203084	Filing Dt:	07/06/2016
Title:	INTERCONNECT STRUCTURES WITH VARIABLE DOPANT LEVELS

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

Search Results as of: 05/09/2024 03:19 PM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6