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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 14 of 146
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Patent #:	6804234	Issue Dt:	10/12/2004	Application #:	09809016	Filing Dt:	03/16/2001
Title:	EXTERNAL CPU ASSIST WHEN PERFORMING A NETWORK ADDRESS LOOKUP

Patent #:	6432763	Issue Dt:	08/13/2002	Application #:	09809133	Filing Dt:	03/15/2001
Title:	FIELD EFFECT TRANSISTOR HAVING DOPED GATE WITH PREVENTION OF CONTAMINATION FROM THE GATE DURING IMPLANTATION

Patent #:	6610608	Issue Dt:	08/26/2003	Application #:	09809300	Filing Dt:	03/16/2001
Title:	PLASMA ETCHING USING COMBINATION OF CHF3 AND CH3F

Patent #:	6593175	Issue Dt:	07/15/2003	Application #:	09809710	Filing Dt:	03/14/2001
Publication #:	US20020048970	Pub Dt:	04/25/2002
Title:	METHOD OF CONTROLLING A SHAPE OF AN OXIDE LAYER FORMED ON A SUBSTRATE

Patent #:	6593637	Issue Dt:	07/15/2003	Application #:	09809754	Filing Dt:	03/13/2001
Title:	METHOD FOR ESTABLISHING COMPONENT ISOLATION REGIONS IN SOI SEMICONDUCTOR DEVICE

Patent #:	6822248	Issue Dt:	11/23/2004	Application #:	09809766	Filing Dt:	03/15/2001
Publication #:	US20020130274	Pub Dt:	09/19/2002
Title:	SPATIAL PHASE LOCKING WITH SHAPED ELECTRON BEAM LITHOGRAPHY

Patent #:	6436744	Issue Dt:	08/20/2002	Application #:	09809888	Filing Dt:	03/16/2001
Title:	METHOD AND STRUCTURE FOR CREATING HIGH DENSITY BURIED CONTACT FOR USE WITH SOI PROCESSES FOR HIGH PERFORMANCE LOGIC

Patent #:	6591411	Issue Dt:	07/08/2003	Application #:	09810075	Filing Dt:	03/15/2001
Publication #:	US20020133799	Pub Dt:	09/19/2002
Title:	APPARATUS AND METHOD FOR DETERMINING BUFFERED STEINER TREES FOR COMPLEX CIRCUITS

Patent #:	6489850	Issue Dt:	12/03/2002	Application #:	09810133	Filing Dt:	03/16/2001
Publication #:	US20020130722	Pub Dt:	09/19/2002
Title:	CROSSTALK SUPPRESSION IN DIFFERENTIAL AC COUPLED MULTICHANNEL IC AMPLIFIERS

Patent #:	6444513	Issue Dt:	09/03/2002	Application #:	09810348	Filing Dt:	03/19/2001
Publication #:	US20020132415	Pub Dt:	09/19/2002
Title:	METAL GATE STACK WITH ETCH STOP LAYER HAVING IMPLANTED METAL SPECIES

Patent #:	6470476	Issue Dt:	10/22/2002	Application #:	09810763	Filing Dt:	03/16/2001
Publication #:	US20020133787	Pub Dt:	09/19/2002
Title:	SUBSTITUTION OF NON-MINIMUM GROUNDRULE CELLS FOR NON-CRITICAL MINIMUM GROUNDRULE CELLS TO INCREASE YIELD

Patent #:	6492210	Issue Dt:	12/10/2002	Application #:	09810771	Filing Dt:	03/16/2001
Publication #:	US20020048862	Pub Dt:	04/25/2002
Title:	FULLY SELF-ALIGNED FET TECHNOLOGY

Patent #:	6617220	Issue Dt:	09/09/2003	Application #:	09810856	Filing Dt:	03/16/2001
Publication #:	US20020132438	Pub Dt:	09/19/2002
Title:	METHOD FOR FABRICATING AN EPITAXIAL BASE BIPLOAR TRANSISTOR WITH RAISED EXTRINSIC BASE

Patent #:	6589860	Issue Dt:	07/08/2003	Application #:	09811190	Filing Dt:	03/16/2001
Title:	SYSTEM AND METHOD FOR CALIBRATING ELECTRON BEAM DEFECT INSPECTION TOOL

Patent #:	6703853	Issue Dt:	03/09/2004	Application #:	09811501	Filing Dt:	03/19/2001
Title:	TEST CONTACT MECHANISM

Patent #:	6506649	Issue Dt:	01/14/2003	Application #:	09811706	Filing Dt:	03/19/2001
Publication #:	US20020132431	Pub Dt:	09/19/2002
Title:	METHOD FOR FORMING NOTCH GATE HAVING SELF-ALIGNED RAISED SOURCE/DRAIN STRUCTURE

Patent #:	6528363	Issue Dt:	03/04/2003	Application #:	09811707	Filing Dt:	03/19/2001
Publication #:	US20020132394	Pub Dt:	09/19/2002
Title:	FABRICATION OF NOTCHED GATES BY PASSIVATING PARTIALLY ETCHED GATE SIDEWALLS AND THEN USING AN ISOTROPIC ETCH

Patent #:	6593197	Issue Dt:	07/15/2003	Application #:	09811733	Filing Dt:	03/19/2001
Publication #:	US20020048890	Pub Dt:	04/25/2002
Title:	SIDEWALL SPACER BASED FET ALIGNMENT TECHNOLOGY

Patent #:	6455919	Issue Dt:	09/24/2002	Application #:	09811979	Filing Dt:	03/19/2001
Publication #:	US20020130392	Pub Dt:	09/19/2002
Title:	INTERNALLY BALLASTED SILICON GERMANIUM TRANSISTOR

Patent #:	6482660	Issue Dt:	11/19/2002	Application #:	09812006	Filing Dt:	03/19/2001
Publication #:	US20020132377	Pub Dt:	09/19/2002
Title:	EFFECTIVE CHANNEL LENGTH CONTROL USING ION IMPLANT FEED FORWARD

Patent #:	6395609	Issue Dt:	05/28/2002	Application #:	09812095	Filing Dt:	03/19/2001
Title:	METHOD FOR FABRICATING A BIPOLAR JUNCTION TRANSISTOR WITH TUNNELING CURRENT THROUGH THE GATE OF A FIELD EFFECT TRANSISTOR AS BASE CURRENT

Patent #:	6642152	Issue Dt:	11/04/2003	Application #:	09812206	Filing Dt:	03/19/2001
Title:	METHOD FOR ULTRA THIN RESIST LINEWIDTH REDUCTION USING IMPLANTATION

Patent #:	6555892	Issue Dt:	04/29/2003	Application #:	09812372	Filing Dt:	03/20/2001
Publication #:	US20020056887	Pub Dt:	05/16/2002
Title:	SEMICONDUCTOR DEVICE WITH REDUCED LINE-TO-LINE CAPACITANCE AND CROSS TALK NOISE

Patent #:	6376343	Issue Dt:	04/23/2002	Application #:	09812695	Filing Dt:	03/21/2001
Title:	REDUCTION OF METAL SILICIDE/SILICON INTERFACE ROUGHNESS BY DOPANT IMPLANTATION PROCESSING

Patent #:	6417912	Issue Dt:	07/09/2002	Application #:	09814231	Filing Dt:	03/21/2001
Title:	METHOD AND APPARATUS FOR CONTROLLING OPTICAL PARAMETERS IN A STEPPER

Patent #:	6352930	Issue Dt:	03/05/2002	Application #:	09814636	Filing Dt:	03/22/2001
Title:	Bilayer anti-reflective coating and etch hard mask

Patent #:	6579614	Issue Dt:	06/17/2003	Application #:	09814766	Filing Dt:	03/23/2001
Publication #:	US20010019737	Pub Dt:	09/06/2001
Title:	STRUCTURE HAVING REFRACTORY METAL FILM ON A SUBSTRATE

Patent #:	6570259	Issue Dt:	05/27/2003	Application #:	09814789	Filing Dt:	03/22/2001
Publication #:	US20020135063	Pub Dt:	09/26/2002
Title:	APPARATUS TO REDUCE THERMAL FATIGUE STRESS ON FLIP CHIP SOLDER CONNECTIONS

Patent #:	7072300	Issue Dt:	07/04/2006	Application #:	09814812	Filing Dt:	03/23/2001
Title:	ACTION TAG GENERATION WITHIN A NETWORK BASED ON PRIORITY OR DIFFERENTIAL SERVICES INFORMATION

Patent #:	6728213	Issue Dt:	04/27/2004	Application #:	09814815	Filing Dt:	03/23/2001
Title:	SELECTIVE ADMISSION CONTROL IN A NETWORK DEVICE

Patent #:	6963536	Issue Dt:	11/08/2005	Application #:	09814816	Filing Dt:	03/23/2001
Title:	ADMISSION CONTROL IN A NETWORK DEVICE

Patent #:	6738731	Issue Dt:	05/18/2004	Application #:	09815445	Filing Dt:	03/22/2001
Title:	METHOD AND APPARATUS FOR USING TOOL STATE INFORMATION TO IDENTIFY FAULTY WAFERS

Patent #:	6664026	Issue Dt:	12/16/2003	Application #:	09815540	Filing Dt:	03/22/2001
Publication #:	US20020136990	Pub Dt:	09/26/2002
Title:	METHOD OF MANUFACTURING HIGH ASPECT RATIO PHOTOLITHOGRAPHIC FEATURES

Patent #:	6518643	Issue Dt:	02/11/2003	Application #:	09816278	Filing Dt:	03/23/2001
Publication #:	US20020135043	Pub Dt:	09/26/2002
Title:	TRI-LAYER DIELECTRIC FUSE CAP FOR LASER DELETION

Patent #:	6566242	Issue Dt:	05/20/2003	Application #:	09816977	Filing Dt:	03/23/2001
Title:	DUAL DAMASCENE COPPER INTERCONNECT TO A DAMASCENE TUNGSTEN WIRING LEVEL

Patent #:	6713874	Issue Dt:	03/30/2004	Application #:	09817050	Filing Dt:	03/27/2001
Title:	SEMICONDUCTOR DEVICES WITH DUAL NATURE CAPPING/ARC LAYERS ON ORGANIC -DOPED SILICA GLASS INTERLAYER DIELECTRICS

Patent #:	6797604	Issue Dt:	09/28/2004	Application #:	09817120	Filing Dt:	03/27/2001
Publication #:	US20020142562	Pub Dt:	10/03/2002
Title:	METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY

Patent #:	6562248	Issue Dt:	05/13/2003	Application #:	09817518	Filing Dt:	03/26/2001
Title:	ACTIVE CONTROL OF PHASE SHIFT MASK ETCHING PROCESS

Patent #:	6709935	Issue Dt:	03/23/2004	Application #:	09817580	Filing Dt:	03/26/2001
Title:	METHOD OF LOCALLY FORMING A SILICON/GERMANIUM CHANNEL LAYER

Patent #:	6514867	Issue Dt:	02/04/2003	Application #:	09817586	Filing Dt:	03/26/2001
Title:	METHOD OF CREATING NARROW TRENCH LINES USING HARD MASK

Patent #:	6387758	Issue Dt:	05/14/2002	Application #:	09817625	Filing Dt:	03/26/2001
Title:	METHOD OF MAKING VERTICAL FIELD EFFECT TRANSISTOR HAVING CHANNEL LENGTH DETERMINED BY THE THICKNESS OF A LAYER OF DUMMY MATERIAL

Patent #:	6650422	Issue Dt:	11/18/2003	Application #:	09817820	Filing Dt:	03/26/2001
Publication #:	US20020135781	Pub Dt:	09/26/2002
Title:	SCATTEROMETRY TECHNIQUES TO ASCERTAIN ASYMMETRY PROFILE OF FEATURES AND GENERATE FEEDBACK OR FEEDFORWARD PROCESS CONTROL DATA ASSOCIATED THEREWITH

Patent #:	6583488	Issue Dt:	06/24/2003	Application #:	09817858	Filing Dt:	03/26/2001
Title:	LOW DENSITY, TENSILE STRESS REDUCING MATERIAL FOR STI TRENCH FILL

Patent #:	6534373	Issue Dt:	03/18/2003	Application #:	09817919	Filing Dt:	03/26/2001
Title:	MOS TRANSISTOR WITH REDUCED FLOATING BODY EFFECT

Patent #:	6534179	Issue Dt:	03/18/2003	Application #:	09818458	Filing Dt:	03/27/2001
Publication #:	US20030003305	Pub Dt:	01/02/2003
Title:	HALOGEN FREE TRIAZINES, BISMALEIMIDE/EPOXY POLYMERS, PREPREGS MADE THEREFROM FOR CIRCUIT BOARDS AND RESIN COATED ARTICLES, AND USE

Patent #:	6716571	Issue Dt:	04/06/2004	Application #:	09819343	Filing Dt:	03/28/2001
Publication #:	US20020139773	Pub Dt:	10/03/2002
Title:	SELECTIVE PHOTORESIST HARDENING TO FACILITATE LATERAL TRIMMING

Patent #:	6653231	Issue Dt:	11/25/2003	Application #:	09819344	Filing Dt:	03/28/2001
Publication #:	US20020160628	Pub Dt:	10/31/2002
Title:	PROCESS FOR REDUCING THE CRITICAL DIMENSIONS OF INTEGRATED CIRCUIT DEVICE FEATURES

Patent #:	6815359	Issue Dt:	11/09/2004	Application #:	09819552	Filing Dt:	03/28/2001
Publication #:	US20020142607	Pub Dt:	10/03/2002
Title:	PROCESS FOR IMPROVING THE ETCH STABILITY OF ULTRA-THIN PHOTORESIST

Patent #:	6589709	Issue Dt:	07/08/2003	Application #:	09819692	Filing Dt:	03/28/2001
Title:	PROCESS FOR PREVENTING DEFORMATION OF PATTERNED PHOTORESIST FEATURES

Patent #:	6574127	Issue Dt:	06/03/2003	Application #:	09820592	Filing Dt:	03/29/2001
Publication #:	US20020141219	Pub Dt:	10/03/2002
Title:	SYSTEM AND METHOD FOR REDUCING NOISE OF CONGESTED DATALINES IN AN EDRAM

Patent #:	6699727	Issue Dt:	03/02/2004	Application #:	09821675	Filing Dt:	03/29/2001
Title:	METHOD FOR PRIORITIZING PRODUCTION LOTS BASED ON GRADE ESTIMATES AND OUTPUT REQUIREMENTS

Patent #:	6660607	Issue Dt:	12/09/2003	Application #:	09822587	Filing Dt:	03/30/2001
Publication #:	US20020139996	Pub Dt:	10/03/2002
Title:	METHOD FOR FABRICATING HETEROJUNCTION BIPOLAR TRANSISTORS

Patent #:	6563578	Issue Dt:	05/13/2003	Application #:	09824112	Filing Dt:	04/02/2001
Publication #:	US20020142493	Pub Dt:	10/03/2002
Title:	IN-SITU THICKNESS MEASUREMENT FOR USE IN SEMICONDUCTOR PROCESSING

Patent #:	6707684	Issue Dt:	03/16/2004	Application #:	09824135	Filing Dt:	04/02/2001
Title:	METHOD AND APPARATUS FOR DIRECT CONNECTION BETWEEN TWO INTEGRATED CIRCUITS VIA A CONNECTOR

Patent #:	6602723	Issue Dt:	08/05/2003	Application #:	09824285	Filing Dt:	04/02/2001
Title:	METHOD OF INTEGRATING SCATTEROMETRY METROLOGY STRUCTURES DIRECTLY INTO DIE DESIGN

Patent #:	6892314	Issue Dt:	05/10/2005	Application #:	09824389	Filing Dt:	04/02/2001
Publication #:	US20020144189	Pub Dt:	10/03/2002
Title:	METHOD AND SYSTEM OF AUTOMATIC DELAY DETECTION AND RECEIVER ADJUSTMENT FOR SYNCHRONOUS BUS INTERFACE

Patent #:	6664180	Issue Dt:	12/16/2003	Application #:	09824415	Filing Dt:	04/02/2001
Title:	METHOD OF FORMING SMALLER TRENCH LINE WIDTH USING A SPACER HARD MASK

Patent #:	6514849	Issue Dt:	02/04/2003	Application #:	09824420	Filing Dt:	04/02/2001
Title:	METHOD OF FORMING SMALLER CONTACT SIZE USING A SPACER HARD MASK

Patent #:	6358843	Issue Dt:	03/19/2002	Application #:	09824421	Filing Dt:	04/02/2001
Title:	Method of making ultra small vias for integrated circuits

Patent #:	6462687	Issue Dt:	10/08/2002	Application #:	09824566	Filing Dt:	04/03/2001
Publication #:	US20020140590	Pub Dt:	10/03/2002
Title:	HIGH PERFORMANCE DELTA SIGMA ADC USING A FEEDBACK NRZ SIN DAC

Patent #:	6410938	Issue Dt:	06/25/2002	Application #:	09824932	Filing Dt:	04/03/2001
Title:	SEMICONDUCTOR-ON-INSULATOR DEVICE WITH NITRIDED BURIED OXIDE AND METHOD OF FABRICATING

Patent #:	6807617	Issue Dt:	10/19/2004	Application #:	09824995	Filing Dt:	04/02/2001
Publication #:	US20020144080	Pub Dt:	10/03/2002
Title:	DESCRIPTOR TABLE STORING SEGMENT DESCRIPTORS OF VARYING SIZE

Patent #:	6579159	Issue Dt:	06/17/2003	Application #:	09825018	Filing Dt:	04/03/2001
Publication #:	US20010018320	Pub Dt:	08/30/2001
Title:	CHEMICAL PLANAR HEAD DAMPENING SYSTEM

Patent #:	6635518	Issue Dt:	10/21/2003	Application #:	09825704	Filing Dt:	04/04/2001
Publication #:	US20020145174	Pub Dt:	10/10/2002
Title:	SOI FET AND METHOD FOR CREATING FET BODY CONNECTIONS WITH HIGH-QUALITY MATCHING CHARACTERISTICS AND NO AREA PENALTY FOR PARTIALLY DEPLETED SOI TECHNOLOGIES

Patent #:	7631160	Issue Dt:	12/08/2009	Application #:	09825905	Filing Dt:	04/04/2001
Publication #:	US20020147916	Pub Dt:	10/10/2002
Title:	METHOD AND APPARATUS FOR SECURING PORTIONS OF MEMORY

Patent #:	6458662	Issue Dt:	10/01/2002	Application #:	09826551	Filing Dt:	04/04/2001
Title:	METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING AN ASYMMETRICAL DUAL-GATE SILICON-GERMANIUM (SIGE) CHANNEL MOSFET AND A DEVICE THEREBY FORMED

Patent #:	6614316	Issue Dt:	09/02/2003	Application #:	09826591	Filing Dt:	04/05/2001
Publication #:	US20020145473	Pub Dt:	10/10/2002
Title:	FRACTIONAL INTEGRATION AND PROPORTIONAL MULTIPLIER CONTROL TO ACHIEVE DESIRED LOOP DYNAMICS

Patent #:	6753612	Issue Dt:	06/22/2004	Application #:	09827014	Filing Dt:	04/05/2001
Publication #:	US20020145203	Pub Dt:	10/10/2002
Title:	ECONOMICAL HIGH DENSITY CHIP CARRIER

Patent #:	6751151	Issue Dt:	06/15/2004	Application #:	09827073	Filing Dt:	04/05/2001
Publication #:	US20020174298	Pub Dt:	11/21/2002
Title:	ULTRA HIGH-SPEED DDP-SRAM CACHE

Patent #:	6724069	Issue Dt:	04/20/2004	Application #:	09827160	Filing Dt:	04/05/2001
Publication #:	US20020145200	Pub Dt:	10/10/2002
Title:	SPIN-ON CAP LAYER, AND SEMICONDUCTOR DEVICE CONTAINING SAME

Patent #:	6440834	Issue Dt:	08/27/2002	Application #:	09827871	Filing Dt:	04/06/2001
Publication #:	US20010014509	Pub Dt:	08/16/2001
Title:	METHOD AND STRUCTURE FOR A SEMICONDUCTOR FUSE

Patent #:	6815997	Issue Dt:	11/09/2004	Application #:	09829160	Filing Dt:	04/09/2001
Publication #:	US20020070789	Pub Dt:	06/13/2002
Title:	FIELD EFFECT TRANSISTOR SQUARE MULTIPLIER

Patent #:	6757857	Issue Dt:	06/29/2004	Application #:	09829630	Filing Dt:	04/10/2001
Publication #:	US20020147949	Pub Dt:	10/10/2002
Title:	ALTERNATING CURRENT BUILT IN SELF TEST (AC BIST) WITH VARIABLE DATA RECEIVER VOLTAGE REFERENCE FOR PERFORMING HIGH-SPEED AC MEMORY SUBSYSTEM SELF-TEST

Patent #:	6522304	Issue Dt:	02/18/2003	Application #:	09832557	Filing Dt:	04/11/2001
Publication #:	US20020149530	Pub Dt:	10/17/2002
Title:	DUAL DAMASCENE HORN ANTENNA

Patent #:	6480991	Issue Dt:	11/12/2002	Application #:	09832623	Filing Dt:	04/11/2001
Publication #:	US20030005398	Pub Dt:	01/02/2003
Title:	TIMING-DRIVEN GLOBAL PLACEMENT BASED ON GEOMETRY-AWARE TIMING BUDGETS

Patent #:	6350639	Issue Dt:	02/26/2002	Application #:	09832684	Filing Dt:	04/10/2001
Title:	METHOD FOR FORMING SIMPLIFIED GRADED LDD TRANSISTOR USING CONTROLLED POLYSILICON GATE PROFILE

Patent #:	6509201	Issue Dt:	01/21/2003	Application #:	09832697	Filing Dt:	04/11/2001
Title:	METHOD AND APPARATUS FOR MONITORING WAFER STRESS

Patent #:	6563300	Issue Dt:	05/13/2003	Application #:	09832781	Filing Dt:	04/11/2001
Title:	METHOD AND APPARATUS FOR FAULT DETECTION USING MULTIPLE TOOL ERROR SIGNALS

Patent #:	6573197	Issue Dt:	06/03/2003	Application #:	09833550	Filing Dt:	04/12/2001
Publication #:	US20020151142	Pub Dt:	10/17/2002
Title:	THERMALLY STABLE POLY-SI/HIGH DIELECTRIC CONSTANT MATERIAL INTERFACES

Patent #:	6495772	Issue Dt:	12/17/2002	Application #:	09834280	Filing Dt:	04/12/2001
Publication #:	US20020148637	Pub Dt:	10/17/2002
Title:	HIGH PERFORMANCE DENSE WIRE FOR PRINTED CIRCUIT BOARD

Patent #:	6465084	Issue Dt:	10/15/2002	Application #:	09834281	Filing Dt:	04/12/2001
Publication #:	US20020150741	Pub Dt:	10/17/2002
Title:	METHOD AND STRUCTURE FOR PRODUCING Z-AXIS INTERCONNECTION ASSEMBLY OF PRINTED WIRING BOARD ELEMENTS

Patent #:	6492662	Issue Dt:	12/10/2002	Application #:	09835732	Filing Dt:	04/16/2001
Publication #:	US20020151130	Pub Dt:	10/17/2002
Title:	T-RAM STRUCTURE HAVING DUAL VERTICAL DEVICES AND METHOD FOR FABRICATING THE SAME

Patent #:	6779165	Issue Dt:	08/17/2004	Application #:	09836164	Filing Dt:	04/18/2001
Publication #:	US20010042236	Pub Dt:	11/15/2001
Title:	SPACING VIOLATION CHECKER

Patent #:	6524163	Issue Dt:	02/25/2003	Application #:	09837603	Filing Dt:	04/18/2001
Title:	METHOD AND APPARATUS FOR CONTROLLING A POLISHING PROCESS BASED ON SCATTEROMETRY DERIVED FILM THICKNESS VARIATION

Patent #:	6383888	Issue Dt:	05/07/2002	Application #:	09837712	Filing Dt:	04/18/2001
Title:	METHOD AND APPARATUS FOR SELECTING WAFER ALIGNMENT MARKS BASED ON FILM THICKNESS VARIATION

Patent #:	6670655	Issue Dt:	12/30/2003	Application #:	09837839	Filing Dt:	04/18/2001
Publication #:	US20020155671	Pub Dt:	10/24/2002
Title:	SOI CMOS DEVICE WITH BODY TO GATE CONNECTION

Patent #:	6358826	Issue Dt:	03/19/2002	Application #:	09838389	Filing Dt:	04/19/2001
Title:	DEVICE IMPROVEMENT BY LOWERING LDD RESISTANCE WITH NEW SPACER/SILICIDE PROCESS

Patent #:	6531720	Issue Dt:	03/11/2003	Application #:	09838417	Filing Dt:	04/19/2001
Publication #:	US20020153535	Pub Dt:	10/24/2002
Title:	DUAL SIDEWALL SPACER FOR A SELF-ALIGNED EXTRINSIC BASE IN SIGE HETEROJUNCTION BIPOLAR TRANSISTORS

Patent #:	6635839	Issue Dt:	10/21/2003	Application #:	09838672	Filing Dt:	04/19/2001
Title:	SEMICONDUCTOR ANALYSIS ARRANGEMENT AND METHOD THEREFOR

Patent #:	6750119	Issue Dt:	06/15/2004	Application #:	09838892	Filing Dt:	04/20/2001
Publication #:	US20020182423	Pub Dt:	12/05/2002
Title:	EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD

Patent #:	6800933	Issue Dt:	10/05/2004	Application #:	09840019	Filing Dt:	04/23/2001
Title:	INTEGRATED CIRCUIT COOLING DEVICE

Patent #:	6711700	Issue Dt:	03/23/2004	Application #:	09840345	Filing Dt:	04/23/2001
Publication #:	US20020156939	Pub Dt:	10/24/2002
Title:	METHOD AND APPARATUS TO MONITOR THE RUN STATE OF A MULTI-PARTITIONED COMPUTER SYSTEM

Patent #:	6684305	Issue Dt:	01/27/2004	Application #:	09841469	Filing Dt:	04/24/2001
Title:	MULTIPROCESSOR SYSTEM IMPLEMENTING VIRTUAL MEMORY USING A SHARED MEMORY, AND A PAGE REPLACEMENT METHOD FOR MAINTAINING PAGED MEMORY COHERENCE

Patent #:	6383824	Issue Dt:	05/07/2002	Application #:	09843111	Filing Dt:	04/25/2001
Title:	METHOD OF USING SCATTEROMETRY MEASUREMENTS TO CONTROL DEPOSITION PROCESSES

Patent #:	6829682	Issue Dt:	12/07/2004	Application #:	09843504	Filing Dt:	04/26/2001
Publication #:	US20020161967	Pub Dt:	10/31/2002
Title:	DESTRUCTIVE READ ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORIES

Patent #:	6506650	Issue Dt:	01/14/2003	Application #:	09843782	Filing Dt:	04/27/2001
Title:	METHOD OF FABRICATION BASED ON SOLID-PHASE EPITAXY FOR A MOSFET TRANSISTOR WITH A CONTROLLED DOPANT PROFILE

Patent #:	6780735	Issue Dt:	08/24/2004	Application #:	09843783	Filing Dt:	04/30/2001
Publication #:	US20020160587	Pub Dt:	10/31/2002
Title:	METHOD TO INCREASE CARBON AND BORON DOPING CONCENTRATIONS IN SI AND SIGE FILMS

Patent #:	6515333	Issue Dt:	02/04/2003	Application #:	09843958	Filing Dt:	04/27/2001
Title:	REMOVAL OF HEAT FROM SOI DEVICE

Patent #:	6384631	Issue Dt:	05/07/2002	Application #:	09844183	Filing Dt:	04/27/2001
Title:	VOLTAGE LEVEL SHIFTER WITH HIGH IMPEDANCE TRI-STATE OUTPUT AND METHOD OF OPERATION

100

Patent #:	6528412	Issue Dt:	03/04/2003	Application #:	09844727	Filing Dt:	04/30/2001
Title:	DEPOSITING AN ADHESION SKIN LAYER AND A CONFORMAL SEED LAYER TO FILL AN INTERCONNECT OPENING

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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