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Patent #:
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08/28/2018
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15386507
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Filing Dt:
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12/21/2016
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Publication #:
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Pub Dt:
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06/21/2018
| | | | |
Title:
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WAFERS AND DEVICE STRUCTURES WITH BODY CONTACTS
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10/23/2018
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15387120
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12/21/2016
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Publication #:
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Pub Dt:
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06/21/2018
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Title:
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INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP
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03/27/2018
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15387933
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12/22/2016
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Title:
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TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS
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05/15/2018
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15387984
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12/22/2016
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Title:
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LOW-K DIELECTRIC SPACER FOR A GATE CUT
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09/04/2018
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15388136
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12/22/2016
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06/28/2018
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Title:
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TEST STRUCTURE FOR TESTING VIA RESISTANCE AND METHOD
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03/27/2018
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15388400
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12/22/2016
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Title:
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MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT
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07/10/2018
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15388530
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12/22/2016
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Pub Dt:
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06/28/2018
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Title:
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CORROSION AND/OR ETCH PROTECTION LAYER FOR CONTACTS AND INTERCONNECT METALLIZATION INTEGRATION
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04/10/2018
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15388772
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12/22/2016
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Title:
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FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS
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07/09/2019
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15389632
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12/23/2016
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06/28/2018
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Title:
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INTEGRATED CIRCUIT STRUCTURE INCLUDING POWER RAIL AND TAPPING WIRE WITH METHOD OF FORMING SAME
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02/13/2018
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15392042
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12/28/2016
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Title:
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CRACK PREVENT AND STOP FOR THIN GLASS SUBSTRATES
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07/03/2018
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15393400
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12/29/2016
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07/05/2018
| | | | |
Title:
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METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE
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NONE
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15393488
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12/29/2016
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07/05/2018
| | | | |
Title:
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METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED DEVICE
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11/21/2017
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15395036
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12/30/2016
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Title:
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SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-UP TRANSISTORS
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04/03/2018
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15396743
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01/02/2017
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04/20/2017
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Title:
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HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS
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10/24/2017
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15397004
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01/03/2017
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Title:
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SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-DOWN TRANSISTORS
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Patent #:
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08/15/2017
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15397021
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01/03/2017
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Title:
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SRAM BITCELL STRUCTURES FACILITATING BIASING OF PASS GATE TRANSISTORS
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Patent #:
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10/16/2018
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15397028
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01/03/2017
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Pub Dt:
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07/05/2018
| | | | |
Title:
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NANOSECOND ACCURACY UNDER PRECISION TIME PROTOCOL FOR ETHERNET BY USING HIGH ACCURACY TIMESTAMP ASSIST DEVICE
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NONE
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15397967
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01/04/2017
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Publication #:
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Pub Dt:
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07/05/2018
| | | | |
Title:
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METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND RESULTING STRUCTURE
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03/13/2018
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15397978
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01/04/2017
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Title:
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DIFFUSION BREAK FORMING AFTER SOURCE/DRAIN FORMING AND RELATED IC STRUCTURE
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Patent #:
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10/24/2017
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15398335
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01/04/2017
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Title:
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METHOD OF FORMING INNER SPACERS ON A NANO-SHEET/WIRE DEVICE
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07/09/2019
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15398946
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01/05/2017
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Publication #:
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Pub Dt:
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07/05/2018
| | | | |
Title:
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SILICON-CONTROLLED RECTIFIERS HAVING A CATHODE COUPLED BY A CONTACT WITH A DIODE TRIGGER
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Patent #:
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02/12/2019
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15399200
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01/05/2017
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Publication #:
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Pub Dt:
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07/05/2018
| | | | |
Title:
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Structure with Local Contact for Shorting a Gate Electrode to a Source/Drain Region
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Patent #:
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02/13/2018
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15401281
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01/09/2017
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Title:
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STRUCTURES WITH CONTACT TRENCHES AND ISOLATION TRENCHES
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Issue Dt:
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08/20/2019
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15401299
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01/09/2017
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Publication #:
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Pub Dt:
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07/12/2018
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Title:
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CREATING KNOWLEDGE BASE FOR OPTICAL PROXIMITY CORRECTION TO REDUCE SUB-RESOLUTION ASSIST FEATURE PRINTING
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Patent #:
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12/18/2018
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15404754
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01/12/2017
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Publication #:
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Pub Dt:
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07/12/2018
| | | | |
Title:
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SEMICONDUCTOR MEMORY DEVICES HAVING AN UNDERCUT SOURCE/DRAIN REGION
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Patent #:
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NONE
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15405026
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Filing Dt:
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01/12/2017
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Publication #:
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Pub Dt:
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07/12/2018
| | | | |
Title:
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BUFFER LAYER TO INHIBIT WORMHOLES IN SEMICONDUCTOR FABRICATION
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Patent #:
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12/04/2018
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15405448
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01/13/2017
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Publication #:
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Pub Dt:
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07/19/2018
| | | | |
Title:
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MOBILE DISPENSE DEVICE FOR CHEMICALS USED IN MICRO-PROCESSING
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Patent #:
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Issue Dt:
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08/21/2018
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15405495
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01/13/2017
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Publication #:
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Pub Dt:
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07/19/2018
| | | | |
Title:
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SEMICONDUCTOR DEVICE STRUCTURE
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Patent #:
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11/07/2017
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15405789
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01/13/2017
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Title:
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METHODS TO CONTROL FIN TIP PLACEMENT
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05/21/2019
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15406350
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01/13/2017
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Publication #:
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Pub Dt:
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07/19/2018
| | | | |
Title:
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CLOCK SYNCHRONIZATON USING CODEWORD MARKER
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Patent #:
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NONE
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15407407
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Filing Dt:
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01/17/2017
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Publication #:
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Pub Dt:
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07/19/2018
| | | | |
Title:
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METAL GATE FORMATION USING AN ENERGY REMOVAL FILM
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Issue Dt:
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03/05/2019
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15407960
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01/17/2017
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Publication #:
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Pub Dt:
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07/19/2018
| | | | |
Title:
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SELF-ALIGNED JUNCTION STRUCTURES
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Patent #:
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07/17/2018
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15408540
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Filing Dt:
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01/18/2017
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Publication #:
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Pub Dt:
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07/19/2018
| | | | |
Title:
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AIR-GAP GATE SIDEWALL SPACER AND METHOD
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Patent #:
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Issue Dt:
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05/14/2019
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15408883
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01/18/2017
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Pub Dt:
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07/19/2018
| | | | |
Title:
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EMBEDDED METAL-INSULATOR-METAL (MIM) DECOUPLING CAPACITOR IN MONOLITIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) STRUCTURE
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01/16/2018
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15410032
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01/19/2017
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Title:
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METHOD OF FORMING MANDREL AND NON-MANDREL METAL LINES HAVING VARIABLE WIDTHS
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Patent #:
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07/17/2018
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15410159
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01/19/2017
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Publication #:
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Pub Dt:
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07/19/2018
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Title:
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FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD
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Patent #:
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01/16/2018
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15412193
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Filing Dt:
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01/23/2017
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Title:
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NON-GEOMETRIC SCALING CURRENT STEERING DIGITAL TO ANALOG CONVERTER
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Patent #:
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Issue Dt:
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02/27/2018
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15412598
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Filing Dt:
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01/23/2017
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Publication #:
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Pub Dt:
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05/11/2017
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Title:
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ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs
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Issue Dt:
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10/23/2018
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15413710
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Filing Dt:
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01/24/2017
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Pub Dt:
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07/26/2018
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Title:
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RECESSING OF LINER AND CONDUCTOR FOR VIA FORMATION
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Patent #:
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Issue Dt:
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03/06/2018
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15413823
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Filing Dt:
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01/24/2017
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Title:
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SIDEWALL SPACER PATTERN FORMATION METHOD
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Patent #:
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Issue Dt:
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01/09/2018
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15416152
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01/26/2017
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Title:
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STRUCTURE AND METHOD FOR INHIBITING COBALT DIFFUSION
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Issue Dt:
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12/11/2018
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15417848
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01/27/2017
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Pub Dt:
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05/11/2017
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Title:
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ADVANCED MOSFET CONTACT STRUCTURE TO REDUCE METAL-SEMICONDUCTOR INTERFACE RESISTANCE
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03/26/2019
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15418001
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01/27/2017
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Pub Dt:
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08/02/2018
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Title:
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CIRCUIT DESIGN HAVING ALIGNED POWER STAPLES
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Issue Dt:
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05/15/2018
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15418015
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01/27/2017
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Pub Dt:
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05/25/2017
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Title:
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MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY
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Patent #:
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Issue Dt:
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05/07/2019
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15418996
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Filing Dt:
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01/30/2017
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Pub Dt:
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05/18/2017
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Title:
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DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME
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Issue Dt:
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06/26/2018
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15419346
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01/30/2017
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Pub Dt:
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05/18/2017
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Title:
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GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS
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Issue Dt:
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10/16/2018
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15420362
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01/31/2017
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Pub Dt:
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08/02/2018
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Title:
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METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE
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Issue Dt:
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08/08/2017
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15420467
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01/31/2017
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Pub Dt:
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05/18/2017
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Title:
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INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER
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Patent #:
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Issue Dt:
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01/22/2019
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15420749
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01/31/2017
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Pub Dt:
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08/02/2018
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Title:
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INSITU TOOL HEALTH AND RECIPE QUALITY MONITORING ON A CDSEM
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Issue Dt:
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06/19/2018
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15420794
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Filing Dt:
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01/31/2017
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Title:
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CHIP INTEGRATION INCLUDING VERTICAL FIELD-EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS
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02/13/2018
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15420967
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01/31/2017
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Pub Dt:
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05/18/2017
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Title:
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SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS
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Patent #:
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Issue Dt:
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06/25/2019
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15421698
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02/01/2017
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Pub Dt:
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05/18/2017
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Title:
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SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF
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08/14/2018
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15421737
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02/01/2017
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Pub Dt:
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05/25/2017
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Title:
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EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING
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01/01/2019
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15422689
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02/15/2017
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Pub Dt:
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08/16/2018
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Title:
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DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY
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06/12/2018
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15422923
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02/02/2017
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Pub Dt:
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08/24/2017
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Title:
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METAL LAYER TIP TO TIP SHORT
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09/25/2018
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15423006
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02/02/2017
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Pub Dt:
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08/02/2018
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Title:
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DIODE-TRIGGERED SCHOTTKY SILICON-CONTROLLED RECTIFIER FOR FIN-FET ELECTROSTATIC DISCHARGE CONTROL
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09/04/2018
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15423326
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02/02/2017
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Publication #:
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Pub Dt:
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08/02/2018
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Title:
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METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE
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09/12/2017
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15423647
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Filing Dt:
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02/03/2017
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Title:
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ACTIVE AREA SHAPES REDUCING DEVICE SIZE
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03/06/2018
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15423945
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Filing Dt:
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02/03/2017
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Publication #:
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Pub Dt:
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05/25/2017
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Title:
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POC PROCESS FLOW FOR CONFORMAL RECESS FILL
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Issue Dt:
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11/05/2019
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15424200
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02/03/2017
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Pub Dt:
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08/09/2018
| | | | |
Title:
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EXTREME ULTRAVIOLET MIRRORS AND MASKS WITH IMPROVED REFLECTIVITY
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01/01/2019
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15424379
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02/03/2017
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Pub Dt:
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08/09/2018
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Title:
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VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS
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04/17/2018
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15425338
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Filing Dt:
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02/06/2017
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Publication #:
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Pub Dt:
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05/25/2017
| | | | |
Title:
|
FORMING ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE
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|
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Patent #:
|
|
Issue Dt:
|
11/28/2017
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Application #:
|
15425366
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Filing Dt:
|
02/06/2017
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Title:
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EMBEDDED DRAM CELLS HAVING CAPACITORS WITHIN TRENCH SILICIDE TRENCHES OF A SEMICONDUCTOR STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15425384
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Filing Dt:
|
02/06/2017
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Publication #:
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Pub Dt:
|
08/09/2018
| | | | |
Title:
|
TRENCH ISOLATION FORMATION FROM THE SUBSTRATE BACK SIDE USING LAYER TRANSFER
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|
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Patent #:
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|
Issue Dt:
|
01/15/2019
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Application #:
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15425478
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Filing Dt:
|
02/06/2017
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Publication #:
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Pub Dt:
|
08/09/2018
| | | | |
Title:
|
DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR FORMING CHAMFER-LESS VIAS
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Patent #:
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Issue Dt:
|
04/03/2018
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Application #:
|
15426573
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Filing Dt:
|
02/07/2017
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Publication #:
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Pub Dt:
|
05/25/2017
| | | | |
Title:
|
HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
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Patent #:
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|
Issue Dt:
|
09/18/2018
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Application #:
|
15426728
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Filing Dt:
|
02/07/2017
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Publication #:
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|
Pub Dt:
|
05/25/2017
| | | | |
Title:
|
SEMICONDUCTOR CIRCUIT ELEMENT
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|
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Patent #:
|
|
Issue Dt:
|
03/30/2021
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Application #:
|
15427128
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Filing Dt:
|
02/08/2017
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Publication #:
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Pub Dt:
|
08/09/2018
| | | | |
Title:
|
FINFET ESD DEVICE WITH SCHOTTKY DIODE
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|
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Patent #:
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|
Issue Dt:
|
06/19/2018
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Application #:
|
15427156
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Filing Dt:
|
02/08/2017
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Publication #:
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Pub Dt:
|
05/25/2017
| | | | |
Title:
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STRUCTURE FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS
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|
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Patent #:
|
|
Issue Dt:
|
03/30/2021
|
Application #:
|
15427182
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Filing Dt:
|
02/08/2017
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Publication #:
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|
Pub Dt:
|
08/09/2018
| | | | |
Title:
|
Heterojunction Bipolar Transistors With Stress Material For Improved Mobility
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|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15427403
|
Filing Dt:
|
02/08/2017
|
Publication #:
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|
Pub Dt:
|
08/09/2018
| | | | |
Title:
|
INTEGRATION OF VERTICAL FIELD-EFFECT TRANSISTORS AND SADDLE FIN-TYPE FIELD EFFECT TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
04/17/2018
|
Application #:
|
15427594
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Filing Dt:
|
02/08/2017
|
Title:
|
VERTICAL PILLAR-TYPE FIELD EFFECT TRANSISTOR AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15428312
|
Filing Dt:
|
02/09/2017
|
Publication #:
|
|
Pub Dt:
|
06/01/2017
| | | | |
Title:
|
TRI-GATE FINFET DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15428449
|
Filing Dt:
|
02/09/2017
|
Publication #:
|
|
Pub Dt:
|
08/09/2018
| | | | |
Title:
|
CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO STRAIN RELAXATION IN STANDARD CELL LIBRARY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2020
|
Application #:
|
15428509
|
Filing Dt:
|
02/09/2017
|
Publication #:
|
|
Pub Dt:
|
05/25/2017
| | | | |
Title:
|
MEMORY DEVICE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15428604
|
Filing Dt:
|
02/09/2017
|
Publication #:
|
|
Pub Dt:
|
06/01/2017
| | | | |
Title:
|
RAISED E-FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2018
|
Application #:
|
15429502
|
Filing Dt:
|
02/10/2017
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2019
|
Application #:
|
15430039
|
Filing Dt:
|
02/10/2017
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
VARIABLE SPACE MANDREL CUT FOR SELF ALIGNED DOUBLE PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2018
|
Application #:
|
15430170
|
Filing Dt:
|
02/10/2017
|
Title:
|
CIRCUIT AND METHOD FOR DETECTING TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) SHORTS AND SIGNAL-MARGIN TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2023
|
Application #:
|
15430596
|
Filing Dt:
|
02/13/2017
|
Publication #:
|
|
Pub Dt:
|
06/01/2017
| | | | |
Title:
|
COUPLING INDUCTORS IN AN IC DEVICE USING INTERCONNECTING ELEMENTS WITH SOLDER CAPS AND RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2018
|
Application #:
|
15430647
|
Filing Dt:
|
02/13/2017
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
GATE CUT INTEGRATION AND RELATED DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2017
|
Application #:
|
15431334
|
Filing Dt:
|
02/13/2017
|
Title:
|
SELF-ALIGNED SACRIFICIAL EPITAXIAL CAPPING FOR TRENCH SILICIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
15431915
|
Filing Dt:
|
02/14/2017
|
Title:
|
INTEGRATED CIRCUIT PACKAGE WITH THERMALLY CONDUCTIVE PILLAR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15432372
|
Filing Dt:
|
02/14/2017
|
Publication #:
|
|
Pub Dt:
|
06/08/2017
| | | | |
Title:
|
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15432560
|
Filing Dt:
|
02/14/2017
|
Publication #:
|
|
Pub Dt:
|
06/01/2017
| | | | |
Title:
|
WAFER HANDLER AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15432710
|
Filing Dt:
|
02/14/2017
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE WITH GATE HEIGHT SCALING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2020
|
Application #:
|
15433099
|
Filing Dt:
|
02/15/2017
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
RAPID HEATING PROCESS IN THE PRODUCTION OF SEMICONDUCTOR COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2020
|
Application #:
|
15433141
|
Filing Dt:
|
02/15/2017
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
TRANSISTORS AND METHODS OF FORMING TRANSISTORS USING VERTICAL NANOWIRES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2019
|
Application #:
|
15433188
|
Filing Dt:
|
02/15/2017
|
Publication #:
|
|
Pub Dt:
|
08/16/2018
| | | | |
Title:
|
FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15433330
|
Filing Dt:
|
02/15/2017
|
Publication #:
|
|
Pub Dt:
|
06/08/2017
| | | | |
Title:
|
METAL GATE STRUCTURE AND METHOD OF FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2017
|
Application #:
|
15434205
|
Filing Dt:
|
02/16/2017
|
Title:
|
SELF-ALIGNED WRAP-AROUND CONTACTS FOR NANOSHEET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
15436281
|
Filing Dt:
|
02/17/2017
|
Title:
|
METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2019
|
Application #:
|
15437057
|
Filing Dt:
|
02/20/2017
|
Publication #:
|
|
Pub Dt:
|
06/08/2017
| | | | |
Title:
|
SUBSTRATE RESISTOR WITH OVERLYING GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2017
|
Application #:
|
15437065
|
Filing Dt:
|
02/20/2017
|
Title:
|
SKIP VIA STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15437100
|
Filing Dt:
|
02/20/2017
|
Title:
|
METAL INTERCONNECTS FOR SUPER (SKIP) VIA INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2018
|
Application #:
|
15437837
|
Filing Dt:
|
02/21/2017
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
METHODS FOR GATE FORMATION IN CIRCUIT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15439444
|
Filing Dt:
|
02/22/2017
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2018
|
Application #:
|
15440072
|
Filing Dt:
|
02/23/2017
|
Title:
|
SILICON NITRIDE CESL REMOVAL WITHOUT GATE CAP HEIGHT LOSS AND RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2017
|
Application #:
|
15441345
|
Filing Dt:
|
02/24/2017
|
Publication #:
|
|
Pub Dt:
|
06/08/2017
| | | | |
Title:
|
Germanium Photodetector with SOI Doping Source
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2018
|
Application #:
|
15443335
|
Filing Dt:
|
02/27/2017
|
Title:
|
DUAL MANDRELS TO ENABLE VARIABLE FIN PITCH
|
|