skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 144 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
1
Patent #:
10096488
Issue Dt:
10/09/2018
Application #:
15608283
Filing Dt:
05/30/2017
Publication #:
US20170263733
Pub Dt:
09/14/2017
Title:
FINFET SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SAME
2
Patent #:
9893154
Issue Dt:
02/13/2018
Application #:
15609295
Filing Dt:
05/31/2017
Publication #:
US20170294515
Pub Dt:
10/12/2017
Title:
RECESS LINER FOR SILICON GERMANIUM FIN FORMATION
3
Patent #:
10037919
Issue Dt:
07/31/2018
Application #:
15609603
Filing Dt:
05/31/2017
Title:
INTEGRATED SINGLE-GATED VERTICAL FIELD EFFECT TRANSISTOR (VFET) AND INDEPENDENT DOUBLE-GATED VFET
4
Patent #:
9922973
Issue Dt:
03/20/2018
Application #:
15611184
Filing Dt:
06/01/2017
Title:
SWITCHES WITH DEEP TRENCH DEPLETION AND ISOLATION STRUCTURES
5
Patent #:
10008385
Issue Dt:
06/26/2018
Application #:
15612335
Filing Dt:
06/02/2017
Title:
ENLARGED SACRIFICIAL GATE CAPS FOR FORMING SELF-ALIGNED CONTACTS
6
Patent #:
9859217
Issue Dt:
01/02/2018
Application #:
15614925
Filing Dt:
06/06/2017
Title:
MIDDLE OF THE LINE (MOL) METAL CONTACTS
7
Patent #:
10090209
Issue Dt:
10/02/2018
Application #:
15615072
Filing Dt:
06/06/2017
Publication #:
US20170271213
Pub Dt:
09/21/2017
Title:
METHODS OF PREDICTING UNITY GAIN FREQUENCY WITH DIRECT CURRENT AND/OR LOW FREQUENCY PARAMETERS
8
Patent #:
10068660
Issue Dt:
09/04/2018
Application #:
15615660
Filing Dt:
06/06/2017
Publication #:
US20170271032
Pub Dt:
09/21/2017
Title:
METHODS, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF WRITE-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY
9
Patent #:
9960248
Issue Dt:
05/01/2018
Application #:
15616653
Filing Dt:
06/07/2017
Publication #:
US20180026113
Pub Dt:
01/25/2018
Title:
FIN-BASED RF DIODES
10
Patent #:
9956845
Issue Dt:
05/01/2018
Application #:
15618197
Filing Dt:
06/09/2017
Publication #:
US20170274730
Pub Dt:
09/28/2017
Title:
SYSTEM AND METHOD TO ADJUST VEHICLE TEMPERATURE BASED ON DRIVER LOCATION
11
Patent #:
9941163
Issue Dt:
04/10/2018
Application #:
15618880
Filing Dt:
06/09/2017
Publication #:
US20170278753
Pub Dt:
09/28/2017
Title:
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
12
Patent #:
9905673
Issue Dt:
02/27/2018
Application #:
15620082
Filing Dt:
06/12/2017
Publication #:
US20170278949
Pub Dt:
09/28/2017
Title:
STRESS MEMORIZATION AND DEFECT SUPPRESSION TECHNIQUES FOR NMOS TRANSISTOR DEVICES
13
Patent #:
10295592
Issue Dt:
05/21/2019
Application #:
15621529
Filing Dt:
06/13/2017
Publication #:
US20170276726
Pub Dt:
09/28/2017
Title:
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING
14
Patent #:
NONE
Issue Dt:
Application #:
15622549
Filing Dt:
06/14/2017
Publication #:
US20170330933
Pub Dt:
11/16/2017
Title:
AIR GAPS FORMED BY POROUS SILICON REMOVAL
15
Patent #:
9911736
Issue Dt:
03/06/2018
Application #:
15622949
Filing Dt:
06/14/2017
Title:
METHOD OF FORMING FIELD EFFECT TRANSISTORS WITH REPLACEMENT METAL GATES AND CONTACTS AND RESULTING STRUCTURE
16
Patent #:
10056334
Issue Dt:
08/21/2018
Application #:
15623691
Filing Dt:
06/15/2017
Publication #:
US20170287837
Pub Dt:
10/05/2017
Title:
DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD
17
Patent #:
9887133
Issue Dt:
02/06/2018
Application #:
15623758
Filing Dt:
06/15/2017
Publication #:
US20170294349
Pub Dt:
10/12/2017
Title:
TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
18
Patent #:
10002792
Issue Dt:
06/19/2018
Application #:
15624156
Filing Dt:
06/15/2017
Publication #:
US20170287785
Pub Dt:
10/05/2017
Title:
HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
19
Patent #:
9929236
Issue Dt:
03/27/2018
Application #:
15624762
Filing Dt:
06/16/2017
Title:
ACTIVE AREA SHAPES REDUCING DEVICE SIZE
20
Patent #:
9960113
Issue Dt:
05/01/2018
Application #:
15625035
Filing Dt:
06/16/2017
Publication #:
US20170294378
Pub Dt:
10/12/2017
Title:
METHOD TO FABRICATE A HIGH PERFORMANCE CAPACITOR IN A BACK END OF LINE (BEOL)
21
Patent #:
10083861
Issue Dt:
09/25/2018
Application #:
15625360
Filing Dt:
06/16/2017
Publication #:
US20170287776
Pub Dt:
10/05/2017
Title:
HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
22
Patent #:
10054630
Issue Dt:
08/21/2018
Application #:
15625609
Filing Dt:
06/16/2017
Publication #:
US20170292986
Pub Dt:
10/12/2017
Title:
METHODS, APPARATUS AND SYSTEM FOR SCREENING PROCESS SPLITS FOR TECHNOLOGY DEVELOPMENT
23
Patent #:
10170553
Issue Dt:
01/01/2019
Application #:
15626241
Filing Dt:
06/19/2017
Publication #:
US20170288033
Pub Dt:
10/05/2017
Title:
SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR
24
Patent #:
10128333
Issue Dt:
11/13/2018
Application #:
15627973
Filing Dt:
06/20/2017
Publication #:
US20170288016
Pub Dt:
10/05/2017
Title:
FINFET WITH ISOLATED SOURCE AND DRAIN
25
Patent #:
NONE
Issue Dt:
Application #:
15628984
Filing Dt:
06/21/2017
Publication #:
US20170338226
Pub Dt:
11/23/2017
Title:
CONTROLLING WITHIN-DIE UNIFORMITY USING DOPED POLISHING MATERIAL
26
Patent #:
10014209
Issue Dt:
07/03/2018
Application #:
15630546
Filing Dt:
06/22/2017
Publication #:
US20170294338
Pub Dt:
10/12/2017
Title:
METHODS, APPARATUS AND SYSTEM FOR LOCAL ISOLATION FORMATION FOR FINFET DEVICES
27
Patent #:
10084068
Issue Dt:
09/25/2018
Application #:
15631385
Filing Dt:
06/23/2017
Publication #:
US20170358666
Pub Dt:
12/14/2017
Title:
SELF-ALIGNED FINFET FORMATION
28
Patent #:
10002859
Issue Dt:
06/19/2018
Application #:
15632909
Filing Dt:
06/26/2017
Title:
FIN-FET RESONANT BODY TRANSISTOR
29
Patent #:
9899363
Issue Dt:
02/20/2018
Application #:
15632927
Filing Dt:
06/26/2017
Title:
FIN-FET RESONANT BODY TRANSISTOR
30
Patent #:
9966272
Issue Dt:
05/08/2018
Application #:
15632931
Filing Dt:
06/26/2017
Title:
METHODS FOR NITRIDE PLANARIZATION USING DIELECTRIC
31
Patent #:
10170353
Issue Dt:
01/01/2019
Application #:
15634091
Filing Dt:
06/27/2017
Publication #:
US20170294336
Pub Dt:
10/12/2017
Title:
DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS
32
Patent #:
10269707
Issue Dt:
04/23/2019
Application #:
15634135
Filing Dt:
06/27/2017
Publication #:
US20170294385
Pub Dt:
10/12/2017
Title:
SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)
33
Patent #:
9799652
Issue Dt:
10/24/2017
Application #:
15635288
Filing Dt:
06/28/2017
Title:
SEMICONDUCTOR STRUCTURE WITH A DOPANT IMPLANT REGION HAVING A LINEARLY GRADED CONDUCTIVITY LEVEL AND METHOD OF FORMING THE STRUCTURE
34
Patent #:
10038065
Issue Dt:
07/31/2018
Application #:
15639095
Filing Dt:
06/30/2017
Publication #:
US20170309714
Pub Dt:
10/26/2017
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION
35
Patent #:
10211094
Issue Dt:
02/19/2019
Application #:
15641861
Filing Dt:
07/05/2017
Publication #:
US20170301767
Pub Dt:
10/19/2017
Title:
HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS
36
Patent #:
10134730
Issue Dt:
11/20/2018
Application #:
15642507
Filing Dt:
07/06/2017
Publication #:
US20170309628
Pub Dt:
10/26/2017
Title:
FINFET DEVICE WITH ENLARGED CHANNEL REGIONS
37
Patent #:
9824935
Issue Dt:
11/21/2017
Application #:
15643036
Filing Dt:
07/06/2017
Publication #:
US20170301589
Pub Dt:
10/19/2017
Title:
METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT
38
Patent #:
10224342
Issue Dt:
03/05/2019
Application #:
15644968
Filing Dt:
07/10/2017
Publication #:
US20170309643
Pub Dt:
10/26/2017
Title:
TUNABLE CAPACITOR FOR FDSOI APPLICATIONS
39
Patent #:
9831132
Issue Dt:
11/28/2017
Application #:
15645395
Filing Dt:
07/10/2017
Publication #:
US20170309522
Pub Dt:
10/26/2017
Title:
METHODS FOR FORMING FIN STRUCTURES
40
Patent #:
9960184
Issue Dt:
05/01/2018
Application #:
15645686
Filing Dt:
07/10/2017
Publication #:
US20170317108
Pub Dt:
11/02/2017
Title:
FDSOI - CAPACITOR
41
Patent #:
10062647
Issue Dt:
08/28/2018
Application #:
15646325
Filing Dt:
07/11/2017
Publication #:
US20170309573
Pub Dt:
10/26/2017
Title:
INTERCONNECT STRUCTURE HAVING TUNGSTEN CONTACT COPPER WIRING
42
Patent #:
10121665
Issue Dt:
11/06/2018
Application #:
15646570
Filing Dt:
07/11/2017
Publication #:
US20170316944
Pub Dt:
11/02/2017
Title:
SHORT-CHANNEL NFET DEVICE
43
Patent #:
10026655
Issue Dt:
07/17/2018
Application #:
15647453
Filing Dt:
07/12/2017
Publication #:
US20170316985
Pub Dt:
11/02/2017
Title:
DUAL LINER CMOS INTEGRATION METHODS FOR FINFET DEVICES
44
Patent #:
10157996
Issue Dt:
12/18/2018
Application #:
15648889
Filing Dt:
07/13/2017
Publication #:
US20170345914
Pub Dt:
11/30/2017
Title:
METHODS FOR FORMING INTEGRATED CIRCUITS THAT INCLUDE A DUMMY GATE STRUCTURE
45
Patent #:
9991352
Issue Dt:
06/05/2018
Application #:
15651282
Filing Dt:
07/17/2017
Title:
METHODS OF FORMING A NANO-SHEET TRANSISTOR DEVICE WITH A THICKER GATE STACK AND THE RESULTING DEVICE
46
Patent #:
9984936
Issue Dt:
05/29/2018
Application #:
15651621
Filing Dt:
07/17/2017
Title:
METHODS OF FORMING AN ISOLATED NANO-SHEET TRANSISTOR DEVICE AND THE RESULTING DEVICE
47
Patent #:
10199220
Issue Dt:
02/05/2019
Application #:
15652413
Filing Dt:
07/18/2017
Publication #:
US20180190483
Pub Dt:
07/05/2018
Title:
SEMICONDUCTOR STRUCTURE HAVING INSULATOR PILLARS AND SEMICONDUCTOR MATERIAL ON SUBSTRATE
48
Patent #:
10249710
Issue Dt:
04/02/2019
Application #:
15652873
Filing Dt:
07/18/2017
Publication #:
US20170317169
Pub Dt:
11/02/2017
Title:
METHODS, APPARATUS, AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS
49
Patent #:
10115633
Issue Dt:
10/30/2018
Application #:
15653127
Filing Dt:
07/18/2017
Publication #:
US20170352591
Pub Dt:
12/07/2017
Title:
METHOD FOR PRODUCING SELF-ALIGNED LINE END VIAS AND RELATED DEVICE
50
Patent #:
10530589
Issue Dt:
01/07/2020
Application #:
15653497
Filing Dt:
07/18/2017
Publication #:
US20170324569
Pub Dt:
11/09/2017
Title:
Method, Apparatus and System for Security Application for Integrated Circuit Devices
51
Patent #:
10535674
Issue Dt:
01/14/2020
Application #:
15653661
Filing Dt:
07/19/2017
Publication #:
US20170317097
Pub Dt:
11/02/2017
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE
52
Patent #:
10245667
Issue Dt:
04/02/2019
Application #:
15654130
Filing Dt:
07/19/2017
Publication #:
US20170312841
Pub Dt:
11/02/2017
Title:
CHIP JOINING BY INDUCTION HEATING
53
Patent #:
10008491
Issue Dt:
06/26/2018
Application #:
15655274
Filing Dt:
07/20/2017
Title:
LOW CAPACITANCE ELECTROSTATIC DISCHARGE (ESD) DEVICES
54
Patent #:
9991363
Issue Dt:
06/05/2018
Application #:
15657594
Filing Dt:
07/24/2017
Title:
CONTACT ETCH STOP LAYER WITH SACRIFICIAL POLYSILICON LAYER
55
Patent #:
9947804
Issue Dt:
04/17/2018
Application #:
15657659
Filing Dt:
07/24/2017
Title:
METHODS OF FORMING NANOSHEET TRANSISTOR WITH DIELECTRIC ISOLATION OF SOURCE-DRAIN REGIONS AND RELATED STRUCTURE
56
Patent #:
10325862
Issue Dt:
06/18/2019
Application #:
15657666
Filing Dt:
07/24/2017
Publication #:
US20180019214
Pub Dt:
01/18/2018
Title:
WAFER RIGIDITY WITH REINFORCEMENT STRUCTURE
57
Patent #:
10103083
Issue Dt:
10/16/2018
Application #:
15658438
Filing Dt:
07/25/2017
Publication #:
US20180053707
Pub Dt:
02/22/2018
Title:
INTEGRATED CIRCUITS WITH PELTIER COOLING PROVIDED BY BACK-END WIRING
58
Patent #:
10345694
Issue Dt:
07/09/2019
Application #:
15658721
Filing Dt:
07/25/2017
Publication #:
US20170322486
Pub Dt:
11/09/2017
Title:
MODEL-BASED GENERATION OF DUMMY FEATURES
59
Patent #:
10014828
Issue Dt:
07/03/2018
Application #:
15659352
Filing Dt:
07/25/2017
Title:
TRANSMITTER SYSTEM AND METHOD OF CALIBRATION
60
Patent #:
9960226
Issue Dt:
05/01/2018
Application #:
15661504
Filing Dt:
07/27/2017
Publication #:
US20170323937
Pub Dt:
11/09/2017
Title:
HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
61
Patent #:
10229918
Issue Dt:
03/12/2019
Application #:
15662594
Filing Dt:
07/28/2017
Publication #:
US20180138187
Pub Dt:
05/17/2018
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING
62
Patent #:
9984919
Issue Dt:
05/29/2018
Application #:
15664584
Filing Dt:
07/31/2017
Title:
INVERTED DAMASCENE INTERCONNECT STRUCTURES
63
Patent #:
10083967
Issue Dt:
09/25/2018
Application #:
15665979
Filing Dt:
08/01/2017
Publication #:
US20170358581
Pub Dt:
12/14/2017
Title:
NON-VOLATILE MEMORY DEVICE EMPLOYING A DEEP TRENCH CAPACITOR
64
Patent #:
10319642
Issue Dt:
06/11/2019
Application #:
15667305
Filing Dt:
08/02/2017
Publication #:
US20180012812
Pub Dt:
01/11/2018
Title:
HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION
65
Patent #:
10043893
Issue Dt:
08/07/2018
Application #:
15668012
Filing Dt:
08/03/2017
Title:
POST GATE SILICON GERMANIUM CHANNEL CONDENSATION AND METHOD FOR PRODUCING THE SAME
66
Patent #:
10163955
Issue Dt:
12/25/2018
Application #:
15671223
Filing Dt:
08/08/2017
Publication #:
US20170358619
Pub Dt:
12/14/2017
Title:
PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS
67
Patent #:
NONE
Issue Dt:
Application #:
15674763
Filing Dt:
08/11/2017
Publication #:
US20180012760
Pub Dt:
01/11/2018
Title:
DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC
68
Patent #:
NONE
Issue Dt:
Application #:
15674859
Filing Dt:
08/11/2017
Publication #:
US20170365721
Pub Dt:
12/21/2017
Title:
DIODES AND FABRICATION METHODS THEREOF
69
Patent #:
10374090
Issue Dt:
08/06/2019
Application #:
15675970
Filing Dt:
08/14/2017
Publication #:
US20170345934
Pub Dt:
11/30/2017
Title:
REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS
70
Patent #:
10050125
Issue Dt:
08/14/2018
Application #:
15676300
Filing Dt:
08/14/2017
Title:
VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH AN ETCHED-THROUGH SOURCE/DRAIN CAVITY
71
Patent #:
10714616
Issue Dt:
07/14/2020
Application #:
15678206
Filing Dt:
08/16/2017
Publication #:
US20180012988
Pub Dt:
01/11/2018
Title:
FINFET HAVING A GATE STRUCTURE IN A TRENCH FEATURE IN A BENT FIN
72
Patent #:
9960077
Issue Dt:
05/01/2018
Application #:
15679848
Filing Dt:
08/17/2017
Title:
ULTRA-SCALE GATE CUT PILLAR WITH OVERLAY IMMUNITY AND METHOD FOR PRODUCING THE SAME
73
Patent #:
10014180
Issue Dt:
07/03/2018
Application #:
15681654
Filing Dt:
08/21/2017
Title:
TUNGSTEN GATE AND METHOD FOR FORMING
74
Patent #:
NONE
Issue Dt:
Application #:
15683228
Filing Dt:
08/22/2017
Publication #:
US20180019337
Pub Dt:
01/18/2018
Title:
METHOD AND STRUCTURE OF FORMING SELF-ALIGNED RMG GATE FOR VFET
75
Patent #:
10079605
Issue Dt:
09/18/2018
Application #:
15683369
Filing Dt:
08/22/2017
Publication #:
US20170359070
Pub Dt:
12/14/2017
Title:
SEMICONDUCTOR STRUCTURE WITH BACK-GATE SWITCHING
76
Patent #:
10056368
Issue Dt:
08/21/2018
Application #:
15686523
Filing Dt:
08/25/2017
Publication #:
US20180006019
Pub Dt:
01/04/2018
Title:
FIN DIODE WITH INCREASED JUNCTION AREA
77
Patent #:
10854510
Issue Dt:
12/01/2020
Application #:
15687455
Filing Dt:
08/26/2017
Publication #:
US20170372949
Pub Dt:
12/28/2017
Title:
TITANIUM SILICIDE FORMATION IN A NARROW SOURCE-DRAIN CONTACT
78
Patent #:
10014215
Issue Dt:
07/03/2018
Application #:
15689413
Filing Dt:
08/29/2017
Publication #:
US20180012798
Pub Dt:
01/11/2018
Title:
METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE A SEMICONDUCTOR ACTIVE REGION HAVING HIGH-K DIELECTRIC GATE CAPS
79
Patent #:
10340189
Issue Dt:
07/02/2019
Application #:
15689565
Filing Dt:
08/29/2017
Publication #:
US20170365682
Pub Dt:
12/21/2017
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
80
Patent #:
10304741
Issue Dt:
05/28/2019
Application #:
15689645
Filing Dt:
08/29/2017
Publication #:
US20170365521
Pub Dt:
12/21/2017
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
81
Patent #:
10192802
Issue Dt:
01/29/2019
Application #:
15689701
Filing Dt:
08/29/2017
Publication #:
US20170365537
Pub Dt:
12/21/2017
Title:
THIN FILM BASED FAN OUT AND MULTI DIE PACKAGE PLATFORM
82
Patent #:
10297597
Issue Dt:
05/21/2019
Application #:
15689711
Filing Dt:
08/29/2017
Publication #:
US20180096998
Pub Dt:
04/05/2018
Title:
COMPOSITE ISOLATION STRUCTURES FOR A FIN-TYPE FIELD EFFECT TRANSISTOR
83
Patent #:
10559743
Issue Dt:
02/11/2020
Application #:
15690828
Filing Dt:
08/30/2017
Publication #:
US20170365775
Pub Dt:
12/21/2017
Title:
BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
84
Patent #:
10037911
Issue Dt:
07/31/2018
Application #:
15692666
Filing Dt:
08/31/2017
Publication #:
US20180005873
Pub Dt:
01/04/2018
Title:
DEVICE LAYER TRANSFER WITH A PRESERVED HANDLE WAFER SECTION
85
Patent #:
10243074
Issue Dt:
03/26/2019
Application #:
15693938
Filing Dt:
09/01/2017
Publication #:
US20180102432
Pub Dt:
04/12/2018
Title:
VERTICAL VACUUM CHANNEL TRANSISTOR
86
Patent #:
10431682
Issue Dt:
10/01/2019
Application #:
15693952
Filing Dt:
09/01/2017
Publication #:
US20180102433
Pub Dt:
04/12/2018
Title:
VERTICAL VACUUM CHANNEL TRANSISTOR
87
Patent #:
10535379
Issue Dt:
01/14/2020
Application #:
15695457
Filing Dt:
09/05/2017
Publication #:
US20170365302
Pub Dt:
12/21/2017
Title:
LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY
88
Patent #:
10049985
Issue Dt:
08/14/2018
Application #:
15698793
Filing Dt:
09/08/2017
Publication #:
US20170373007
Pub Dt:
12/28/2017
Title:
CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME
89
Patent #:
9953872
Issue Dt:
04/24/2018
Application #:
15699138
Filing Dt:
09/08/2017
Publication #:
US20180012805
Pub Dt:
01/11/2018
Title:
SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS
90
Patent #:
9929049
Issue Dt:
03/27/2018
Application #:
15699322
Filing Dt:
09/08/2017
Publication #:
US20170372959
Pub Dt:
12/28/2017
Title:
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
91
Patent #:
NONE
Issue Dt:
Application #:
15701480
Filing Dt:
09/12/2017
Publication #:
US20170373000
Pub Dt:
12/28/2017
Title:
METHOD OF FORMING AN INTEGRATED CIRCUIT WITH DUAL DAMASCENE INTERCONNECTS HAVING HYBRID METALLIZATION AND THE RESULTING STRUCTURE
92
Patent #:
10340369
Issue Dt:
07/02/2019
Application #:
15703484
Filing Dt:
09/13/2017
Publication #:
US20180006143
Pub Dt:
01/04/2018
Title:
TUNNELING FIELD EFFECT TRANSISTOR
93
Patent #:
NONE
Issue Dt:
Application #:
15703601
Filing Dt:
09/13/2017
Publication #:
US20180005893
Pub Dt:
01/04/2018
Title:
METHODS FOR FORMING MASK LAYERS USING A FLOWABLE CARBON-CONTAINING SILICON DIOXIDE MATERIAL
94
Patent #:
10366996
Issue Dt:
07/30/2019
Application #:
15704598
Filing Dt:
09/14/2017
Publication #:
US20180012895
Pub Dt:
01/11/2018
Title:
STABLE AND RELIABLE FINFET SRAM WITH IMPROVED BETA RATIO
95
Patent #:
10762136
Issue Dt:
09/01/2020
Application #:
15705886
Filing Dt:
09/15/2017
Publication #:
US20190087435
Pub Dt:
03/21/2019
Title:
TAG-BASED, USER DIRECTED MEDIA RECOMMENDATIONS
96
Patent #:
10053794
Issue Dt:
08/21/2018
Application #:
15708281
Filing Dt:
09/19/2017
Publication #:
US20180016699
Pub Dt:
01/18/2018
Title:
ELECTROPLATING SYSTEM AND METHOD OF USING ELECTROPLATING SYSTEM FOR CONTROLLING CONCENTRATION OF ORGANIC ADDITIVES IN ELECTROPLATING SOLUTION
97
Patent #:
10665586
Issue Dt:
05/26/2020
Application #:
15708911
Filing Dt:
09/19/2017
Publication #:
US20180006028
Pub Dt:
01/04/2018
Title:
METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE
98
Patent #:
10522655
Issue Dt:
12/31/2019
Application #:
15711674
Filing Dt:
09/21/2017
Publication #:
US20180012973
Pub Dt:
01/11/2018
Title:
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPACER WIDTHS & DUAL RAISED SOURCE DRAIN EXPITAXIAL SILICON AND TRIPLE-NITRIDE SPACER INTEGRATION ENABLING HIGH-VOLTAGE EG DEVICE ON FDSOI
99
Patent #:
NONE
Issue Dt:
Application #:
15711714
Filing Dt:
09/21/2017
Publication #:
US20180012647
Pub Dt:
01/11/2018
Title:
METHODS, APPARATUS AND SYSTEM FOR PROVIDING NMOS-ONLY MEMORY CELLS
100
Patent #:
10529917
Issue Dt:
01/07/2020
Application #:
15712109
Filing Dt:
09/21/2017
Publication #:
US20180123027
Pub Dt:
05/03/2018
Title:
High Energy Barrier Perpendicular Magnetic Tunnel Junction Element With Reduced Temperature Sensitivity
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

Search Results as of: 05/09/2024 05:55 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT