skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 146 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
1
Patent #:
10680085
Issue Dt:
06/09/2020
Application #:
15911415
Filing Dt:
03/05/2018
Publication #:
US20180190797
Pub Dt:
07/05/2018
Title:
TRANSISTOR STRUCTURE WITH VARIED GATE CROSS-SECTIONAL AREA
2
Patent #:
10361281
Issue Dt:
07/23/2019
Application #:
15911892
Filing Dt:
03/05/2018
Publication #:
US20180197972
Pub Dt:
07/12/2018
Title:
METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
3
Patent #:
10186524
Issue Dt:
01/22/2019
Application #:
15912141
Filing Dt:
03/05/2018
Publication #:
US20180197882
Pub Dt:
07/12/2018
Title:
FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS
4
Patent #:
10529858
Issue Dt:
01/07/2020
Application #:
15913194
Filing Dt:
03/06/2018
Publication #:
US20180197980
Pub Dt:
07/12/2018
Title:
FINFET WITH MERGE-FREE FINS
5
Patent #:
10886419
Issue Dt:
01/05/2021
Application #:
15913344
Filing Dt:
03/06/2018
Publication #:
US20180198000
Pub Dt:
07/12/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR AND METHOD FOR THE FORMATION THEREOF
6
Patent #:
10535551
Issue Dt:
01/14/2020
Application #:
15919744
Filing Dt:
03/13/2018
Publication #:
US20180204761
Pub Dt:
07/19/2018
Title:
LATERAL PiN DIODES AND SCHOTTKY DIODES
7
Patent #:
10163526
Issue Dt:
12/25/2018
Application #:
15920677
Filing Dt:
03/14/2018
Publication #:
US20180233216
Pub Dt:
08/16/2018
Title:
CIRCUIT AND METHOD FOR DETECTING TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) SHORTS AND SIGNAL-MARGIN TESTING
8
Patent #:
NONE
Issue Dt:
Application #:
15921715
Filing Dt:
03/15/2018
Publication #:
US20180204926
Pub Dt:
07/19/2018
Title:
METHODS FOR FORMING MOSFETS USING SELECTIVE UNDERCUT AT GATE CONDUCTOR AND GATE INSULATOR CORNER
9
Patent #:
10388731
Issue Dt:
08/20/2019
Application #:
15925051
Filing Dt:
03/19/2018
Publication #:
US20180212024
Pub Dt:
07/26/2018
Title:
STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)
10
Patent #:
10514393
Issue Dt:
12/24/2019
Application #:
15933443
Filing Dt:
03/23/2018
Publication #:
US20180217184
Pub Dt:
08/02/2018
Title:
GIMBAL ASSEMBLY TEST SYSTEM AND METHOD
11
Patent #:
10879112
Issue Dt:
12/29/2020
Application #:
15933449
Filing Dt:
03/23/2018
Publication #:
US20180211871
Pub Dt:
07/26/2018
Title:
SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE
12
Patent #:
10217869
Issue Dt:
02/26/2019
Application #:
15936149
Filing Dt:
03/26/2018
Publication #:
US20180219096
Pub Dt:
08/02/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL
13
Patent #:
10340362
Issue Dt:
07/02/2019
Application #:
15938412
Filing Dt:
03/28/2018
Publication #:
US20180219079
Pub Dt:
08/02/2018
Title:
SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
14
Patent #:
10644136
Issue Dt:
05/05/2020
Application #:
15945578
Filing Dt:
04/04/2018
Publication #:
US20180233585
Pub Dt:
08/16/2018
Title:
MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE
15
Patent #:
NONE
Issue Dt:
Application #:
15947479
Filing Dt:
04/06/2018
Publication #:
US20180233415
Pub Dt:
08/16/2018
Title:
FINFET DEVICE AND METHOD OF MANUFACTURING
16
Patent #:
10325812
Issue Dt:
06/18/2019
Application #:
15950291
Filing Dt:
04/11/2018
Publication #:
US20180233413
Pub Dt:
08/16/2018
Title:
GRAPHENE CONTACTS ON SOURCE/DRAIN REGIONS OF FINFET DEVICES
17
Patent #:
10446421
Issue Dt:
10/15/2019
Application #:
15951547
Filing Dt:
04/12/2018
Publication #:
US20180231957
Pub Dt:
08/16/2018
Title:
CRYSTAL OSCILLATOR AND THE USE THEREOF IN SEMICONDUCTOR FABRICATION
18
Patent #:
10446435
Issue Dt:
10/15/2019
Application #:
15951557
Filing Dt:
04/12/2018
Publication #:
US20180233401
Pub Dt:
08/16/2018
Title:
LOCAL TRAP-RICH ISOLATION
19
Patent #:
10395995
Issue Dt:
08/27/2019
Application #:
15956082
Filing Dt:
04/18/2018
Publication #:
US20180233417
Pub Dt:
08/16/2018
Title:
DUAL LINER SILICIDE
20
Patent #:
NONE
Issue Dt:
Application #:
15956090
Filing Dt:
04/18/2018
Publication #:
US20180233566
Pub Dt:
08/16/2018
Title:
FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

Search Results as of: 05/08/2024 11:25 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT