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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
12/02/2003
Application #:
09969675
Filing Dt:
10/03/2001
Publication #:
Pub Dt:
05/15/2003
Title:
AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM
2
Patent #:
Issue Dt:
07/20/2004
Application #:
09971820
Filing Dt:
10/05/2001
Publication #:
Pub Dt:
04/10/2003
Title:
PROCESS FOR REMOVING DOPANT IONS FROM A SUBSTRATE
3
Patent #:
Issue Dt:
04/22/2003
Application #:
09971840
Filing Dt:
10/05/2001
Publication #:
Pub Dt:
04/10/2003
Title:
COLUMN REDUNDANCY SYSTEM AND METHOD FOR EMBEDDED DRAM DEVICES WITH MULTIBANKING CAPABILITY
4
Patent #:
Issue Dt:
06/17/2003
Application #:
09974217
Filing Dt:
10/09/2001
Title:
MANUFACTURING METHOD FOR FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE
5
Patent #:
Issue Dt:
05/07/2002
Application #:
09974568
Filing Dt:
10/10/2001
Title:
INSULATING AND CAPPING STRUCTURE WITH PRESERVATION OF THE LOW DIELECTRIC CONSTANT OF THE INSULATING LAYER
6
Patent #:
Issue Dt:
03/04/2003
Application #:
09974986
Filing Dt:
10/11/2001
Title:
INTERLEAVED FEEDFORWARD VCO AND PLL
7
Patent #:
Issue Dt:
02/01/2005
Application #:
09975213
Filing Dt:
10/11/2001
Publication #:
Pub Dt:
04/17/2003
Title:
ELECTRICAL COUPLING OF SUBSTRATES BY CONDUCTIVE BUTTONS
8
Patent #:
Issue Dt:
06/29/2004
Application #:
09975435
Filing Dt:
10/11/2001
Publication #:
Pub Dt:
06/05/2003
Title:
PATTERNED SOI REGIONS ON SEMICONDUCTOR CHIPS
9
Patent #:
Issue Dt:
03/25/2003
Application #:
09977423
Filing Dt:
10/15/2001
Publication #:
Pub Dt:
04/17/2003
Title:
METHOD AND RING OSCILLATOR FOR EVALUATING DYNAMIC CIRCUITS
10
Patent #:
Issue Dt:
05/13/2003
Application #:
09977922
Filing Dt:
10/15/2001
Title:
PREPARATION OF COMPOSITE HIGH-K DIELECTRICS
11
Patent #:
Issue Dt:
05/06/2003
Application #:
09977928
Filing Dt:
10/15/2001
Title:
PREPARATION OF COMPOSITE HIGH-K / STANDARD-K DIELECTRICS FOR SEMICONDUCTOR DEVICES
12
Patent #:
Issue Dt:
04/27/2004
Application #:
09978351
Filing Dt:
10/15/2001
Publication #:
Pub Dt:
05/22/2003
Title:
TAGGING AND ARBITRATION MECHANISM IN AN INPUT/OUTPUT NODE OF A COMPUTER SYSTEM
13
Patent #:
Issue Dt:
01/20/2004
Application #:
09978378
Filing Dt:
10/15/2001
Publication #:
Pub Dt:
05/15/2003
Title:
VIRTUAL CHANNEL BUFFER BYPASS FOR AN I/O NODE OF A COMPUTER SYSTEM
14
Patent #:
Issue Dt:
03/30/2004
Application #:
09981618
Filing Dt:
10/15/2001
Title:
APPARATUS AND METHOD FOR ALLOCATING BUFFER SPACE
15
Patent #:
Issue Dt:
04/01/2003
Application #:
09989585
Filing Dt:
11/20/2001
Title:
METHOD FOR LIMITING DIVOT FORMATION IN POST SHALLOW TRENCH ISOLATION PROCESSES
16
Patent #:
Issue Dt:
03/16/2004
Application #:
09992447
Filing Dt:
11/16/2001
Publication #:
Pub Dt:
05/22/2003
Title:
METHOD AND APPARATUS FOR UTILIZING INTEGRATED METROLOGY DATA AS FEED-FORWARD DATA
17
Patent #:
Issue Dt:
11/18/2003
Application #:
09994340
Filing Dt:
11/26/2001
Publication #:
Pub Dt:
05/29/2003
Title:
PROCESS FOR FORMING A DAMASCENE STRUCTURE
18
Patent #:
Issue Dt:
04/13/2010
Application #:
09994395
Filing Dt:
11/26/2001
Publication #:
Pub Dt:
01/08/2004
Title:
METHOD OF USING TERNARY COPPER ALLOY TO OBTAIN A LOW RESISTANCE AND LARGE GRAIN SIZE INTERCONNECT
19
Patent #:
Issue Dt:
06/22/2004
Application #:
09994954
Filing Dt:
11/27/2001
Publication #:
Pub Dt:
04/11/2002
Title:
METHOD AND STRUCTURE FOR REDUCTION OF CONTACT RESISTANCE OF METAL SILICIDES USING A METAL-GERMANIUM ALLOY
20
Patent #:
Issue Dt:
01/31/2006
Application #:
09996053
Filing Dt:
11/28/2001
Publication #:
Pub Dt:
09/26/2002
Title:
ANALOG UNIDIRECTIONAL SERIAL LINK ARCHITECTURE
21
Patent #:
Issue Dt:
12/28/2004
Application #:
09996148
Filing Dt:
11/28/2001
Publication #:
Pub Dt:
05/29/2003
Title:
MICRO-ELECTROMECHANICAL SWITCH HAVING A CONDUCTIVE COMPRESSIBLE ELECTRODE
22
Patent #:
Issue Dt:
11/18/2003
Application #:
09996731
Filing Dt:
11/30/2001
Publication #:
Pub Dt:
03/21/2002
Title:
METHOD FOR INCREASING A VERY-LARGE-SCALE-INTEGRATED (VLSI) CAPACITOR SIZE ON BULK SILICON AND SILICON-ON-INSULATOR (SOI) WAFERS AND STRUCTURE FORMED THEREBY
23
Patent #:
Issue Dt:
04/29/2003
Application #:
09997904
Filing Dt:
11/30/2001
Title:
METHOD OF PHOTOLITHOGRAPHIC CRITICAL BY USING RETICLE MEASUREMENTS IN A CONTROL ALGORITHM
24
Patent #:
Issue Dt:
11/30/2004
Application #:
10000093
Filing Dt:
12/04/2001
Publication #:
Pub Dt:
06/13/2002
Title:
FLAT TYPE FLUORESCENT LAMP
25
Patent #:
Issue Dt:
07/08/2003
Application #:
10000198
Filing Dt:
11/02/2001
Publication #:
Pub Dt:
05/30/2002
Title:
SEMICONDUCTOR DEVICE OF AN EMBEDDED DRAM ON SOI SUBSTRATE
26
Patent #:
Issue Dt:
03/18/2003
Application #:
10000493
Filing Dt:
10/23/2001
Title:
CHEMICAL FEATURE DOUBLING PROCESS
27
Patent #:
Issue Dt:
01/21/2003
Application #:
10000695
Filing Dt:
11/15/2001
Title:
METHOD FOR FORMING HIGH PERFORMANCE CMOS DEVICES WITH ELEVATED SIDEWALL SPACERS
28
Patent #:
Issue Dt:
06/19/2007
Application #:
10002185
Filing Dt:
12/05/2001
Title:
ARRANGEMENT FOR INITIALIZING DIGITAL EQUALIZER SETTINGS BASED ON COMPARING DIGITAL EQUALIZER OUTPUTS TO PRESCRIBED EQUALIZER OUTPUTS
29
Patent #:
Issue Dt:
03/18/2003
Application #:
10005295
Filing Dt:
12/04/2001
Title:
SYSTEM FOR GENERATING A REFERENCE VOLTAGE
30
Patent #:
Issue Dt:
11/18/2003
Application #:
10005951
Filing Dt:
12/03/2001
Publication #:
Pub Dt:
05/09/2002
Title:
RECESSED BOND PAD
31
Patent #:
Issue Dt:
02/24/2004
Application #:
10006076
Filing Dt:
12/06/2001
Publication #:
Pub Dt:
06/12/2003
Title:
FRAMEWORK FOR MULTIPLE-ENGINE BASED VERIFICATION TOOLS FOR INTEGRATED CIRCUITS
32
Patent #:
Issue Dt:
08/05/2003
Application #:
10006969
Filing Dt:
12/04/2001
Publication #:
Pub Dt:
06/13/2002
Title:
METHOD FOR NON-CONTACT STRESS EVALUATION OF WAFER GATE DIELECTRIC RELIABILITY
33
Patent #:
Issue Dt:
10/12/2004
Application #:
10008383
Filing Dt:
12/06/2001
Publication #:
Pub Dt:
06/12/2003
Title:
BIPOLAR DEVICE HAVING NON-UNIFORM DEPTH BASE-EMITTER JUNCTION
34
Patent #:
Issue Dt:
10/12/2004
Application #:
10010392
Filing Dt:
12/07/2001
Title:
APPARATUS FOR SUPPRESSING PACKAGED SEMICONDUCTOR CHIP CURVATURE WHILE MINIMIZING THERMAL IMPEDANCE AND MAXIMIZING SPEED/RELIABILITY
35
Patent #:
Issue Dt:
11/23/2004
Application #:
10010569
Filing Dt:
11/13/2001
Title:
MEMORY MANAGEMENT SYSTEM AND METHOD FOR PROVIDING PHYSICAL ADDRESS BASED MEMORY ACCESS SECURITY
36
Patent #:
Issue Dt:
09/16/2008
Application #:
10011151
Filing Dt:
12/05/2001
Title:
SYSTEM AND METHOD FOR HANDLING DEVICE ACCESSES TO A MEMORY PROVIDING INCREASED MEMORY ACCESS SECURITY
37
Patent #:
Issue Dt:
11/22/2005
Application #:
10011351
Filing Dt:
12/04/2001
Publication #:
Pub Dt:
06/05/2003
Title:
FINFET SRAM CELL USING LOW MOBILITY PLANE FOR CELL STABILITY AND METHOD FOR FORMING
38
Patent #:
Issue Dt:
12/02/2003
Application #:
10011846
Filing Dt:
12/04/2001
Publication #:
Pub Dt:
06/05/2003
Title:
MULTIPLE-PLANE FINFET CMOS
39
Patent #:
Issue Dt:
04/20/2004
Application #:
10012426
Filing Dt:
12/07/2001
Publication #:
Pub Dt:
05/02/2002
Title:
METHOD FOR MAKING PRINTED CIRCUIT BOARD HAVING LOW COEFFICIENT OF THEMAL EXPANSION POWER/GROUND PLANE
40
Patent #:
Issue Dt:
01/13/2004
Application #:
10013070
Filing Dt:
11/06/2001
Publication #:
Pub Dt:
05/23/2002
Title:
USER CONFIGURABLE MULTIVARIATE TIME SERIES REDUCTION TOOL CONTROL METHOD
41
Patent #:
Issue Dt:
12/02/2003
Application #:
10013354
Filing Dt:
12/13/2001
Title:
IN-SITU MONITORING DURING LASER THERMAL ANNEALING
42
Patent #:
Issue Dt:
06/29/2004
Application #:
10014064
Filing Dt:
12/10/2001
Title:
CMOS PROCESS WITH AN INTEGRATED, HIGH PERFORMANCE, SILICIDE AGGLOMERATION FUSE
43
Patent #:
Issue Dt:
10/21/2003
Application #:
10014660
Filing Dt:
11/07/2001
Publication #:
Pub Dt:
08/07/2003
Title:
METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SWITCHES ON CMOS COMPATIBLE SUBSTRATES
44
Patent #:
Issue Dt:
04/11/2006
Application #:
10014766
Filing Dt:
12/11/2001
Publication #:
Pub Dt:
11/07/2002
Title:
ORGANIC N-CHANNEL SEMICONDUCTOR DEVICE OF N,N' 3,4,9,10 PERYLENE TETRACARBOXYLIC DIIMIDE
45
Patent #:
Issue Dt:
09/02/2003
Application #:
10015239
Filing Dt:
12/13/2001
Publication #:
Pub Dt:
06/19/2003
Title:
MONOLITHICALLY INTEGRATED COLD POINT THERMOELECTRIC COOLER
46
Patent #:
Issue Dt:
05/06/2003
Application #:
10015987
Filing Dt:
12/13/2001
Title:
METHOD OF FORMING A RECESSED POLYSILICON FILLED TRENCH
47
Patent #:
Issue Dt:
08/27/2002
Application #:
10016025
Filing Dt:
12/12/2001
Title:
SYSTEM AND METHOD FOR CONSERVING POWER IN A CONTENT ADDRESSABLE MEMORY BY PROVIDING AN INDEPENDENT SEARCH LINE VOLTAGE
48
Patent #:
Issue Dt:
12/13/2005
Application #:
10016090
Filing Dt:
12/13/2001
Publication #:
Pub Dt:
06/19/2003
Title:
EMBEDDED INDUCTOR AND METHOD OF MAKING
49
Patent #:
Issue Dt:
09/23/2003
Application #:
10016252
Filing Dt:
12/10/2001
Title:
METAL BRIDGING MONITOR FOR ETCH AND CMP ENDPOINT DETECTION
50
Patent #:
Issue Dt:
02/04/2003
Application #:
10016410
Filing Dt:
12/07/2001
Title:
SEMICONDUCTOR DEVICE WITH COPPER-FILLED VIA INCLUDES A COPPER-ZINC ALLO FILM FOR REDUCED ELECTROMIGRATION OF COPPER
51
Patent #:
Issue Dt:
11/16/2004
Application #:
10016439
Filing Dt:
12/11/2001
Title:
METHOD OF EXTENDING THE AREAS OF CLEAR FIELD PHASE SHIFT GENERATION
52
Patent #:
Issue Dt:
08/17/2004
Application #:
10016605
Filing Dt:
10/30/2001
Publication #:
Pub Dt:
05/01/2003
Title:
VERTICAL DRAM PUNCHTHROUGH STOP SELF-ALIGNED TO STORAGE TRENCH
53
Patent #:
Issue Dt:
10/07/2003
Application #:
10016645
Filing Dt:
12/07/2001
Title:
METHOD OF REDUCING ELECTROMIGRATION BY ORDERING ZINC-DOPING IN AN ELECTROPLATED COPPER-ZINC INTERCONNECT AND A SEMICONDUCTOR DEVICE THEREBY FORMED
54
Patent #:
Issue Dt:
01/06/2004
Application #:
10016702
Filing Dt:
12/11/2001
Title:
METHOD OF ENHANCING CLEAR FIELD PHASE SHIFT MASKS BY ADDING PARALLEL LINE TO PHASE 0 REGION
55
Patent #:
Issue Dt:
10/19/2004
Application #:
10016772
Filing Dt:
12/10/2001
Publication #:
Pub Dt:
06/12/2003
Title:
METHOD AND SYSTEM FOR USE OF AN EMBEDDED FIELD PROGRAMMABLE GATE ARRAY INTERCONNECT FOR FLEXIBLE I/O CONNECTIVITY
56
Patent #:
Issue Dt:
06/29/2004
Application #:
10020551
Filing Dt:
10/30/2001
Publication #:
Pub Dt:
05/01/2003
Title:
METHOD AND APPARATUS FOR CASCADE CONTROL USING INTEGRATED METROLOGY
57
Patent #:
Issue Dt:
05/27/2003
Application #:
10020698
Filing Dt:
10/29/2001
Publication #:
Pub Dt:
04/18/2002
Title:
METHOD FOR IMPROVING PERFORMANCE OF ORGANIC SEMICONDUCTORS IN BOTTOM ELECTRODE STRUCTURE
58
Patent #:
Issue Dt:
01/14/2003
Application #:
10020931
Filing Dt:
12/19/2001
Title:
REMOVABLE SPACER TECHNIQUE
59
Patent #:
Issue Dt:
10/26/2004
Application #:
10021531
Filing Dt:
12/12/2001
Title:
MODEL BASED METAL OVERETCH CONTROL
60
Patent #:
Issue Dt:
03/02/2004
Application #:
10021828
Filing Dt:
12/12/2001
Title:
PHOTOSENSITIVE BOTTOM ANTI-REFLECTIVE COATING
61
Patent #:
Issue Dt:
01/20/2004
Application #:
10022162
Filing Dt:
12/17/2001
Publication #:
Pub Dt:
06/19/2003
Title:
SCANNING HEAT FLOW PROBE
62
Patent #:
Issue Dt:
11/11/2003
Application #:
10022321
Filing Dt:
12/13/2001
Title:
METHOD AND APPARATUS FOR COMBINING INTEGRATED AND OFFLINE METROLOGY FOR PROCESS CONTROL
63
Patent #:
Issue Dt:
04/27/2004
Application #:
10022847
Filing Dt:
12/20/2001
Title:
ELECTRICALLY PROGRAMMED MOS TRANSISTOR SOURCE/DRAIN SERIES RESISTANCE
64
Patent #:
Issue Dt:
09/07/2004
Application #:
10023098
Filing Dt:
12/17/2001
Title:
METHOD AND APPARATUS USING INTEGRATED METROLOGY DATA FOR PRE-PROCESS AND POST-PROCESS CONTROL
65
Patent #:
Issue Dt:
11/18/2003
Application #:
10024675
Filing Dt:
12/18/2001
Title:
METHOD AND APPARATUS FOR DETERMINING A SAMPLING PLAN BASED ON PROCESS AND EQUIPMENT FINGERPRINTING
66
Patent #:
Issue Dt:
01/03/2006
Application #:
10026029
Filing Dt:
12/18/2001
Publication #:
Pub Dt:
06/19/2003
Title:
OPTICAL APERTURE FOR DATA RECORDING HAVING TRANSMISSION ENHANCED BY SURFACE PLASMON RESONANCE
67
Patent #:
Issue Dt:
07/29/2003
Application #:
10026103
Filing Dt:
12/19/2001
Publication #:
Pub Dt:
06/19/2003
Title:
CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS
68
Patent #:
Issue Dt:
12/17/2002
Application #:
10026873
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/27/2002
Title:
MULTILAYER CAPACITANCE STRUCTURE AND CIRCUIT BOARD CONTAINING THE SAME AND METHOD OF FORMING THE SAME
69
Patent #:
Issue Dt:
04/06/2004
Application #:
10028840
Filing Dt:
12/20/2001
Title:
READ-MODIFY-WRITE FOR PARTIAL WRITES IN A MEMORY CONTROLLER
70
Patent #:
Issue Dt:
12/23/2008
Application #:
10032567
Filing Dt:
01/02/2002
Publication #:
Pub Dt:
12/12/2002
Title:
STATIC DETECTION OF A DATARACE CONDITION FOR MULTITHREADED OBJECT-ORIENTED APPLICATIONS
71
Patent #:
Issue Dt:
12/23/2003
Application #:
10033902
Filing Dt:
01/03/2002
Publication #:
Pub Dt:
07/03/2003
Title:
SEMICONDUCTOR-ON-INSULATOR LATERAL P-I-N PHOTODETECTOR WITH A REFLECTING MIRROR AND BACKSIDE CONTACT AND METHOD FOR FORMING THE SAME
72
Patent #:
Issue Dt:
09/14/2004
Application #:
10034163
Filing Dt:
12/27/2001
Publication #:
Pub Dt:
10/16/2003
Title:
PREPARATION OF STACK HIGH-K GATE DIELECTRICS WITH NITRIDED LAYER
73
Patent #:
Issue Dt:
09/14/2004
Application #:
10034560
Filing Dt:
12/27/2001
Title:
I/O NODE FOR A COMPUTER SYSTEM INCLUDING AN INTEGRATED GRAPHICS ENGINE
74
Patent #:
Issue Dt:
08/10/2004
Application #:
10034790
Filing Dt:
12/27/2001
Title:
METHOD AND APPARATUS FOR IDENTIFYING MISREGISTRATION IN A COMPLIMENTARY PHASE SHIFT MASK PROCESS
75
Patent #:
Issue Dt:
02/15/2005
Application #:
10034967
Filing Dt:
12/27/2001
Title:
I/O NODE FOR A COMPUTER SYSTEM INCLUDING AN INTEGRATED GRAPHICS ENGINE AND AN INTEGRATED I/O HUB
76
Patent #:
Issue Dt:
02/04/2003
Application #:
10037611
Filing Dt:
01/04/2002
Title:
METHOD FOR FABRICATION OF RELAXED SIGE BUFFER LAYERS ON SILICON-ON-INSULATORS AND STRUCTURES CONTAINING THE SAME
77
Patent #:
Issue Dt:
10/03/2006
Application #:
10038163
Filing Dt:
01/02/2002
Publication #:
Pub Dt:
07/03/2003
Title:
METHOD, SYSTEM, AND PROGRAM FOR SYNCHRONIZATION AND RESYNCHRONIZATION OF A DATA STREAM
78
Patent #:
Issue Dt:
09/21/2004
Application #:
10039525
Filing Dt:
11/07/2001
Title:
FEEDFORWARD TEMPERATURE CONTROL OF DEVICE UNDER TEST
79
Patent #:
Issue Dt:
08/31/2004
Application #:
10040002
Filing Dt:
11/07/2001
Title:
ELECTRICAL CONDUCTION ARRAY ON THE BOTTOM SIDE OF A TESTER THERMAL HEAD
80
Patent #:
Issue Dt:
09/02/2003
Application #:
10040325
Filing Dt:
11/07/2001
Title:
SURFACE PLASMON RESONANCE-BASED ENDPOINT DETECTION FOR CHEMICAL MECHANICAL PLANARIZATION (CMP)
81
Patent #:
Issue Dt:
02/10/2004
Application #:
10040446
Filing Dt:
01/09/2002
Publication #:
Pub Dt:
07/11/2002
Title:
POLYMERS AND USE THEREOF
82
Patent #:
Issue Dt:
10/21/2003
Application #:
10040839
Filing Dt:
01/07/2002
Publication #:
Pub Dt:
07/10/2003
Title:
METHOD OF FORMING METALLIC Z-INTERCONNECTS FOR LAMINATE CHIP PACKAGES AND BOARDS
83
Patent #:
Issue Dt:
05/27/2003
Application #:
10041120
Filing Dt:
01/08/2002
Publication #:
Pub Dt:
06/13/2002
Title:
MERGED SELF-ALIGNED SOURCE AND ONO CAPACITOR FOR SPLIT GATE NON-VOLATILE MEMORY
84
Patent #:
Issue Dt:
08/09/2011
Application #:
10041328
Filing Dt:
01/07/2002
Publication #:
Pub Dt:
07/10/2003
Title:
DEBRIS MINIMIZATION AND IMPROVED SPATIAL RESOLUTION IN PULSED LASER ABLATION OF MATERIALS
85
Patent #:
Issue Dt:
03/09/2004
Application #:
10041347
Filing Dt:
01/08/2002
Publication #:
Pub Dt:
07/10/2003
Title:
CONCURRENT ELECTRICAL SIGNAL WIRING OPTIMIZATION FOR AN ELECTRONIC PACKAGE
86
Patent #:
Issue Dt:
06/17/2003
Application #:
10041639
Filing Dt:
01/07/2002
Publication #:
Pub Dt:
07/11/2002
Title:
CHIP PACKAGING SYSTEM AND METHOD USING DEPOSITED DIAMOND FILM
87
Patent #:
Issue Dt:
11/08/2011
Application #:
10041671
Filing Dt:
01/10/2002
Publication #:
Pub Dt:
07/10/2003
Title:
NON-UNIQUE RESULTS IN DESIGN VERIFICATION BY TEST PROGRAMS
88
Patent #:
Issue Dt:
08/17/2004
Application #:
10042101
Filing Dt:
01/07/2002
Publication #:
Pub Dt:
07/10/2003
Title:
METHOD OF ANALYZING AND FILTERING TIMING RUNS USING COMMON TIMING CHARACTERISTICS
89
Patent #:
Issue Dt:
06/06/2006
Application #:
10042366
Filing Dt:
01/11/2002
Publication #:
Pub Dt:
07/17/2003
Title:
SYSTEM FOR ESTIMATING THE TEMPORAL VALIDITY OF LOCATION REPORTS THROUGH PATTERN ANALYSIS
90
Patent #:
Issue Dt:
07/08/2003
Application #:
10043060
Filing Dt:
01/08/2002
Publication #:
Pub Dt:
07/10/2003
Title:
ELECTRONIC PACKAGE
91
Patent #:
Issue Dt:
10/07/2003
Application #:
10044641
Filing Dt:
01/10/2002
Publication #:
Pub Dt:
07/10/2003
Title:
ADVANCED PROCESS CONTROL (APC) OF COPPER THICKNESS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OPTIMIZATION
92
Patent #:
Issue Dt:
04/13/2010
Application #:
10044667
Filing Dt:
01/11/2002
Title:
METHOD AND APPARATUS FOR LINEAR ADDRESS BASED PAGE LEVEL SECURITY SCHEME TO DETERMINE CURRENT SECURITY CONTEXT
93
Patent #:
Issue Dt:
12/04/2007
Application #:
10044707
Filing Dt:
01/11/2002
Title:
PROCESSING TASKS WITH FAILURE RECOVERY
94
Patent #:
Issue Dt:
03/04/2003
Application #:
10044892
Filing Dt:
01/11/2002
Title:
MOSFETS WITH DIFFERING GATE DIELECTRICS AND METHOD OF FORMATION
95
Patent #:
Issue Dt:
10/28/2003
Application #:
10045445
Filing Dt:
11/09/2001
Publication #:
Pub Dt:
05/15/2003
Title:
ELECTRON SCATTER IN A THIN MEMBRANE TO ELIMINATE DETECTOR SATURATION
96
Patent #:
Issue Dt:
05/18/2004
Application #:
10045711
Filing Dt:
01/14/2002
Publication #:
Pub Dt:
07/18/2002
Title:
ELECTRONIC STRUCTURES WITH REDUCED CAPACITANCE
97
Patent #:
Issue Dt:
06/29/2004
Application #:
10045895
Filing Dt:
10/29/2001
Publication #:
Pub Dt:
10/24/2002
Title:
METHOD OF FABRICATING COPPER-BASED SEMICONDUCTOR DEVICES USING A SACRIFICIAL DIELECTRIC LAYER
98
Patent #:
Issue Dt:
06/15/2010
Application #:
10047188
Filing Dt:
01/15/2002
Publication #:
Pub Dt:
03/18/2004
Title:
METHOD AND APPARATUS FOR MULTI-TABLE ACCESSING OF INPUT/OUTPUT DEVICES USING TARGET SECURITY
99
Patent #:
Issue Dt:
07/01/2003
Application #:
10047497
Filing Dt:
11/09/2001
Publication #:
Pub Dt:
05/15/2003
Title:
ELECTRONIC DEVICE SUBSTRATE ASSEMBLY WITH IMPERMEABLE BARRIER AND METHOD OF MAKING
100
Patent #:
Issue Dt:
05/18/2004
Application #:
10047965
Filing Dt:
01/15/2002
Publication #:
Pub Dt:
07/17/2003
Title:
ADVANCED BEOL INTERCONNECT STRUCTURES WITH LOW-K PE CVD CAP LAYER AND METHOD THEREOF
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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