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12/12/2002
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07/22/2003
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09/05/2002
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12/12/2002
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03/23/2004
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10/30/2003
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10/30/2003
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06/15/2004
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10134973
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Filing Dt:
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04/29/2002
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Title:
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SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE HAVING SELECTIVE DOPANT IMPLANT IN INSULATOR LAYER AND METHOD OF FABRICATING
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10134981
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Filing Dt:
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04/29/2002
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Title:
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SELECTIVE THICKENING OF THE SOURCE-DRAIN AND GATE AREAS OF FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10135008
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Filing Dt:
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04/29/2002
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Title:
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SEMICONDUCTOR-ON-INSULATOR DEVICE WITH THERMOELECTRIC COOLER ON SURFACE
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10135502
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Filing Dt:
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04/30/2002
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Title:
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HEAT SINK SUBASSEMBLY
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10138498
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Filing Dt:
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05/06/2002
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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HIGH SILICON CONTENT MONOMERS AND POLYMERS SUITABLE FOR 193 NM BILAYER RESISTS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10138712
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Filing Dt:
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05/03/2002
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Title:
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METHOD AND SYSTEM FOR CONTROLLING A PROCESS TOOL
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10139331
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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FLOATING GATE MEMORY DEVICE USING COMPOSITE MOLECULAR MATERIAL
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10139746
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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ADDRESABLE AND ELECTRICALLY REVERSIBLE MEMORY SWITCH
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10140517
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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AUTOMATED BUFFER INSERTION INCORPORATING CONGESTION RELIEF FOR USE IN CONNECTION WITH PHYSICAL DESIGN OF INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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10140549
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/13/2003
| | | | |
Title:
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SPLIT LOCAL AND CONTINUOUS BITLINE FOR FAST DOMINO READ SRAM
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10141279
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Filing Dt:
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05/08/2002
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Publication #:
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Pub Dt:
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09/12/2002
| | | | |
Title:
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GATE OXIDE STABILIZATION BY MEANS OF GERMANIUM COMPONENTS IN GATE CONDUCTOR
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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10143317
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Filing Dt:
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05/09/2002
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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METHOD FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10144402
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Filing Dt:
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05/13/2002
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Publication #:
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Pub Dt:
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11/21/2002
| | | | |
Title:
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METHODOLOGY FOR ELECTRICALLY INDUCED SELECTIVE BREAKDOWN OF NANOTUBES
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10144510
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Filing Dt:
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05/13/2002
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Publication #:
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Pub Dt:
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11/13/2003
| | | | |
Title:
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DISK SUBSTRATE WITH MONOSIZED MICROBUMPS
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10144574
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Filing Dt:
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05/13/2002
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Publication #:
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Pub Dt:
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09/12/2002
| | | | |
Title:
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MULTILEVEL INTERCONNECT STRUCTURE CONTAINING AIR GAPS AND METHOD FOR MAKING
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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10145018
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Filing Dt:
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05/15/2002
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
Title:
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CONTENT ADDRESSABLE MEMORY HAVING REDUCED POWER CONSUMPTION
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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10145519
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Filing Dt:
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05/14/2002
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Title:
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METHOD OF MAKING TRANSISTORS WITH GATE INSULATION LAYERS OF DIFFERING THICKNESS
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10145915
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Filing Dt:
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05/15/2002
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Title:
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SOI MOSFET AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10145928
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Filing Dt:
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05/15/2002
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Title:
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METHOD OF FORMING AN ELECTROLESS NUCLEATION LAYER ON A VIA BOTTOM
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10145942
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Filing Dt:
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05/15/2002
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Title:
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INTEGRATED PROCESS FOR DEPOSITING LAYER OF HIGH-K DIELECTRIC WITH IN-SITU CONTROL OF K VALUE AND THICKNESS OF HIGH-K DIELECTRIC LAYER
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Patent #:
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Issue Dt:
|
03/16/2004
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Application #:
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10145953
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Filing Dt:
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05/15/2002
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Title:
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SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10146029
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Filing Dt:
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05/16/2002
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Title:
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FORMATION OF HIGH-K GATE DIELECTRIC LAYERS FOR MOS DEVICES FABRICATED ON STRAINED LATTICE SEMICONDUCTOR SUBSTRATES WITH MINIMIZED STRESS RELAXATION
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10146154
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Filing Dt:
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05/15/2002
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Title:
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CONTENT ADDRESSABLE MEMORY (CAM) WITH ERROR CHECKING AND CORRECTION (ECC) CAPABILITY
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Patent #:
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Issue Dt:
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04/01/2008
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Application #:
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10146331
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Filing Dt:
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05/15/2002
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Publication #:
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Pub Dt:
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11/21/2002
| | | | |
Title:
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METHOD FOR PARALLEL SIMULATION ON A SINGLE MICROPROCESSOR USING META-MODELS
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10147150
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Filing Dt:
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05/16/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
Title:
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EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10147270
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Filing Dt:
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05/15/2002
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
Title:
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METHOD OF CONTROLLING GRAIN SIZE IN A POLYSILICON LAYER AND IN SEMICONDUCTOR DEVICES HAVING POLYSILICONE STRUCTURES
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Patent #:
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Issue Dt:
|
10/05/2004
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Application #:
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10150320
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Filing Dt:
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05/17/2002
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Title:
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METHOD AND APPARATUS FOR CONTROLLING COPPER BARRIER/SEED DEPOSITION PROCESSES
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Patent #:
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Issue Dt:
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07/28/2009
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Application #:
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10150783
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
|
12/19/2002
| | | | |
Title:
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INTRUSION DETECTION IN DATA PROCESSING SYSTEMS
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|
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Patent #:
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Issue Dt:
|
09/16/2003
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Application #:
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10151269
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Filing Dt:
|
05/20/2002
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Title:
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MOS TRANSISTORS WITH HIGH-K DIELECTRIC GATE INSULATOR FOR REDUCING REMOTE SCATTERING
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Patent #:
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Issue Dt:
|
02/10/2004
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Application #:
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10151946
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Filing Dt:
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05/22/2002
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Title:
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LOW TEMPERATURE SOLID-PHASE EPITAXY FABRICATION PROCESS FOR MOS DEVICES BUILT ON STRAINED SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10154274
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Filing Dt:
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05/22/2002
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Title:
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CREATING A PROCESS RECIPE BASED ON A DESIRED RESULT
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Patent #:
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Issue Dt:
|
04/12/2005
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Application #:
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10154796
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/27/2003
| | | | |
Title:
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NONVOLATILE MEMORY DEVICE UTILIZING SPIN-VALVE-TYPE DESIGNS AND CURRENT PULSES
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Patent #:
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Issue Dt:
|
09/16/2003
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Application #:
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10154871
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Filing Dt:
|
05/23/2002
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Title:
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SEMICONDUCTOR DEVICE FABRICATED BY REDUCING CARBON, SULPHUR, AND OXYGEN IMPURITIES IN A CALCIUM-DOPED COPPER SURFACE
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Patent #:
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Issue Dt:
|
09/02/2003
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Application #:
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10155044
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Filing Dt:
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05/24/2002
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Title:
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STRUCTURE , AND A METHOD OF REALIZING, FOR EFFICIENT HEAT REMOVAL ON SOI
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10159181
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
|
10/03/2002
| | | | |
Title:
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INTERCONNECTION STRUCTURE AND METHOD FOR FABRICATING SAME
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Patent #:
|
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Issue Dt:
|
11/30/2004
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Application #:
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10159921
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
|
12/04/2003
| | | | |
Title:
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PARAMETER VARIATION TOLERANT METHOD FOR CIRCUIT DESIGN OPTIMIZATION
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|
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Patent #:
|
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Issue Dt:
|
12/09/2003
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Application #:
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10160300
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Filing Dt:
|
05/30/2002
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Publication #:
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Pub Dt:
|
05/22/2003
| | | | |
Title:
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ON-CHIP DIAGNOSTIC SYSTEM, INTEGRATED CIRCUIT AND METHOD
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|