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Patent #:
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09/26/2000
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09200016
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11/25/1998
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Title:
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IN-SITU SION DEPOSITION/BAKE/TEOS DEPOSITION PROCESS FOR REDUCTION OF DEFECTS IN INTERLEVEL DIELECTRIC FOR INTEGRATED CIRCUIT INTERCONNECTS
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01/23/2001
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09201995
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Filing Dt:
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12/01/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE SHARED BETWEEN TWO SETS OF ACTIVE REGIONS AND FABRICATION THEREOF
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09/26/2000
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09203012
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Filing Dt:
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12/01/1998
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Title:
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SEMICONDUCTOR DEVICE AND FABRICATION METHOD USING A GERMANIUM SACRIFICIAL GATE ELECTRODE
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12/26/2000
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09203150
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Filing Dt:
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12/01/1998
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Title:
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THIN RESIST WITH AMORPHOUS SILICON HARD MASK FOR VIA ETCH APPLICATION
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09203283
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Filing Dt:
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12/01/1998
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Title:
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THIN RESIST WITH NITRIDE HARD MASK FOR VIA ETCH APPLICATION
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09203447
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Filing Dt:
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12/01/1998
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Title:
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METHOD FOR TRANSFERRING PATTERNS CREATED BY LITHOGRAPHY
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Issue Dt:
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12/19/2000
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09203450
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Filing Dt:
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12/01/1998
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Title:
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THIN RESIST WITH TRANSITION METAL HARD MASK FOR VIA ETCH APPLICATION
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Issue Dt:
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02/01/2000
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09203461
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Filing Dt:
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND NITRIDE/OXIDE HARD MASK FOR METAL ETCH
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Patent #:
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06/26/2001
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09203572
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12/02/1998
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Title:
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INTEGRATION OF LOW-K SIOF AS INTER-LAYER DIELECTRIC
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Issue Dt:
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01/23/2001
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09203754
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Filing Dt:
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12/02/1998
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Title:
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INTEGRATION OF LOW-K SIOF FOR DAMASCENE STRUCTURE
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12/05/2000
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09203774
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND SILICON/OXIDE HARD MASK FOR METAL ETCH
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Patent #:
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Issue Dt:
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09/26/2000
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09203926
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Filing Dt:
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12/02/1998
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Title:
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ELECTROMIGRATION-RESISTANT COPPER MICROSTRUCTURE AND PROCESS OF MAKING
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Patent #:
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04/06/2004
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09204025
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12/01/1998
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Title:
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APPARATUS AND METHOD FOR CURRENT DEMAND DISTRIBUTION IN ELECTRONIC SYSTEMS
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07/31/2001
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09204185
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12/03/1998
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Title:
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METHOD FOR FORMING ELECTROMIGRATION-RESISTANT STRUCTURES BY DOPING
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03/13/2001
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09204216
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND BARRIER METAL/OXIDE HARD MASK FOR METAL ETCH
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Patent #:
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01/16/2001
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09204458
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Filing Dt:
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12/02/1998
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Title:
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COMPOSITE LAMINATE CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME
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Patent #:
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10/23/2001
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09204630
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND SION/OXIDE HARD MASK FOR METAL ETCH
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01/09/2001
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09204651
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND OXIDE/NITRIDE HARD MASK FOR METAL ETCH
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Patent #:
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04/24/2001
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09204967
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Filing Dt:
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12/03/1998
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Title:
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METHOD OF MAKING AN ELEVATED SOURCE/DRAIN WITH ENHANCED GRADED SIDEWALLS FOR TRANSISTOR SCALING INTEGRATED WITH SPACER FORMATION
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Issue Dt:
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01/30/2001
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09204978
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Filing Dt:
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12/03/1998
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Title:
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MINIMIZING CACHE OVERHEAD BY STORING DATA FOR COMMUNICATIONS BETWEEN A PERIPHERAL DEVICE AND A HOST SYSTEM INTO SEPARATE LOCATIONS IN MEMORY
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02/06/2001
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09204998
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12/02/1998
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Title:
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METHOD OF FORMING A MOSFET TRANSISTOR WITH A SHALLOW ABRUPT RETROGRADE DOPANT PROFILE
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03/27/2001
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09205010
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12/04/1998
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Title:
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MARK PROTECTION WITH TRANSPARENT FILM
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12/26/2000
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09205068
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12/04/1998
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Title:
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ANTIREFLECTIVE COATING USED IN THE FABRICATION OF MICROCIRCUIT STRUCTURES IN 0.18 MICRON AND SMALLER TECHNOLOGIES
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12/21/1999
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09205321
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12/04/1998
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Title:
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ARGON DOPED EPITAXIAL LAYERS FOR INHIBITING PUNCHTHROUGH WITHIN A SEMICONDUCTOR DEVICE
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03/13/2001
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09205443
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12/04/1998
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Title:
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USE OF SACRIFICIAL DIELECTRIC STRUCTURE TO FORM SEMICONDUCTOR DEVICE WITH A SELF-ALIGNED THRESHOLD ADJUST AND OVERLYING LOW-RESISTANCE GATE
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11/28/2000
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09205444
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12/04/1998
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Title:
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PROCESSOR EMPLOYING MULTIPLE REGISTER SETS TO ELIMINATE INTERRUPTS
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Issue Dt:
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02/20/2001
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09205522
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12/03/1998
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Title:
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METHOD FOR FORMING A SHALLOW JUNCTION IN A SEMICONDUCTOR DEVICE USING ANTIMONY DIMER
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05/09/2000
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09205583
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12/04/1998
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Title:
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METHOD FOR FABRICATING DUAL LAYER PROTECTIVE BARRIER COPPER METALLIZATION
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Patent #:
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08/19/2003
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09205589
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12/04/1998
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Title:
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SINGLE POINT HIGH RESOLUTION TIME RESOLVED PHOTOEMISSION MICROSCOPY SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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12/26/2000
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09205616
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12/04/1998
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Title:
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METHOD OF MANUFACTURING MOSFET WITH DIFFERENTIAL GATE OXIDE THICKNESS ON THE SAME IC CHIP
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Patent #:
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Issue Dt:
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01/23/2001
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09205790
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12/04/1998
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Title:
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LITHOGRAPHY REFLECTIVE MASK
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04/11/2000
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09205791
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12/04/1998
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Title:
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BACKSIDE POLISH EUV MASK AND METHOD OF MANUFACTURE
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09/05/2000
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09205897
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12/04/1998
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Title:
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ILLUMINATION MODIFICATION SCHEME SYNTHESIS USING LENS CHARACTERIZATION DATA
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Patent #:
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08/07/2001
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09205898
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12/04/1998
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Title:
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METHODOLOGY FOR EXTRACTING EFFECTIVE LENS ABERRATIONS USING A NEURAL NETWORK
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11/07/2000
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09205934
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12/04/1998
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Title:
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DRAM CELL HAVING AN ANNULAR SIGNAL TRANSFER REGION
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02/13/2001
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09205935
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12/04/1998
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Title:
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MULTI-WAFER POLISHING TOOL
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01/11/2000
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09205958
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12/04/1998
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Title:
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REWORKABLE EUV MASK MATERIALS
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04/04/2000
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09205978
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12/04/1998
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Title:
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METHOD AND APPARATUS FOR OPTIMIZING MEMORY PERFORMANCE WITH OPPORTUNISTIC REFRESHING
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03/27/2001
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09206163
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12/07/1998
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PREVENTION OF CU DENDRITE FORMATION AND GROWTH
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Issue Dt:
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01/23/2001
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09206169
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12/07/1998
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Title:
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PREVENTING CU DENDRITE FORMATION AND GROWTH
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07/22/2003
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09206170
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12/07/1998
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CHEMICALLY PEVENTING CU DENDRITE FORMATION AND GROWTH BY IMMERSION
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03/26/2002
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09206550
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12/07/1998
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SEMICONDUCTOR TOPOGRAPHY HAVING IMPROVED ACTIVE DEVICE ISOLATION AND REDUCED DOPANT MIGRATION
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09/26/2000
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09206669
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12/07/1998
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METHOD FOR FORMING CONFORMAL BARRIER LAYERS
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Issue Dt:
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10/31/2000
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09206951
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12/08/1998
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING WITHOUT DAMAGING HSQ LAYER AND METAL PATTERN UTILIZING MULTIPLE DIELECTRIC LAYERS
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11/20/2001
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09207318
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12/07/1998
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Title:
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CHEMICALLY PREVENTING COPPER DENDRITE FORMATION AND GROWTH BY SPRAYING
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05/01/2001
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09207675
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12/09/1998
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Title:
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HIGH DENSITY CAPPING LAYERS WITH IMPROVED ADHESION TO COPPER INTERCONNECTS
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02/27/2001
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09207676
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12/09/1998
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H2 DIFFUSION BARRIER FORMATION BY NITROGEN INCORPORATION IN OXIDE LAYER
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06/05/2001
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09207680
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12/09/1998
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Title:
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METHOD OF FORMING COPPER/COPPER ALLOY INTERCONNECTION WITH REDUCED ELECTROMIGRATION
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01/21/2003
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09207971
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12/09/1998
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Title:
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METHOD AND SYSTEM FOR PAGE-STATE SENSITIVE MEMORY CONTROL AND ACCESS IN DATA PROCESSING SYSTEMS
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04/17/2001
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09208305
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12/09/1998
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Title:
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METHOD AND SYSTEM FOR ORIGIN-SENSITIVE MEMORY CONTROL AND ACCESS IN DATA PROCESSING SYSTEMS
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05/01/2001
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09208569
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12/09/1998
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METHOD AND SYSTEM FOR GENERATING AND UTILIZING SPECULATIVE MEMORY ACCESS REQUESTS IN DATA PROCESSING SYSTEMS
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10/19/1999
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09208597
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12/08/1998
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Title:
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MANUFACTURABLE CAPPING LAYER FOR THE FABRICATION OF COBALT SALICIDE STRUCTURES
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11/20/2001
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09208713
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Filing Dt:
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12/09/1998
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Title:
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METHOD AND SYSTEM FOR SELECTIVELY DISCONNECTING A REDUNDANT POWER DISTRIBUTION NETWORK TO IDENTIFY A SITE OF A SHORT
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12/04/2001
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09208909
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12/10/1998
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Title:
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PROGRAMMABLE STATE MACHINE
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03/04/2003
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09209119
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12/10/1998
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INITIALIZING AND SAVING PERIPHERAL DEVICE CONFIGURATION STATES OF A MICROCONTROLLER USING A UTILITY PROGRAM
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03/26/2002
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09209190
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12/10/1998
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METHOD AND APPARATUS FOR SAVING AND LOADING PERIPHERAL DEVICE STATES OF A MICROCONTROLLER VIA A SCAN PATH
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05/23/2000
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09209413
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12/10/1998
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METHOD AND APPARATUS FOR PREVENTING FORMATION OF BLACK SILICON ON EDGES OF WAFERS
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10/07/2003
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09217367
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12/21/1998
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FLEXIBLE PROBE/PROBE RESPONSE ROUTING FOR MAINTAINING COHERENCY
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Issue Dt:
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08/14/2001
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09217649
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Filing Dt:
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12/21/1998
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Title:
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MESSAGING SCHEME TO MAINTAIN CACHE COHERENCY AND CONSERVE SYSTEM MEMORY BANDWIDTH DURING A MEMORY READ OPERATION IN A MULTIPROCESSING COMPUTER SYSTEM
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12/05/2000
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09224766
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01/04/1999
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Title:
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ESD PROTECTION CIRCUIT FOR MULTIPLE POWER SUUPLY ENVIRONMENTS
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01/15/2002
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09224820
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01/04/1999
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ADDRESS SPACE CONVERSION TO RETAIN SOFTWARE COMPATIBILITY IN NEW ARCHITECTURES
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06/26/2001
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09224821
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01/04/1999
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COLLATION OF INTERRUPT CONTROL DEVICES
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06/04/2002
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09224822
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Filing Dt:
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01/04/1999
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Title:
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BANK HISTORY TABLE FOR IMPROVED PRE-CHARGE SCHEDULING OF RANDOM ACCESS MEMORY BANKS
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09/11/2001
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09225175
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01/04/1999
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Title:
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METHOD OF DEFINING COPPER SEED LAYER FOR SELECTIVE ELECTROLESS PLATING PROCESSING
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04/29/2003
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09225219
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01/04/1999
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Pub Dt:
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10/10/2002
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NETWORK TRANSCEIVER FOR STEERING NETWORK DATA TO SELECTED PATHS BASED ON DETERMINED LINK SPEEDS
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07/18/2000
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09225339
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01/05/1999
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Title:
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BLAZED GRATING MEASUREMENTS OF LITHOGRAPHIC LENS ABERATIONS
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08/24/2010
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09225388
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01/05/1999
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Title:
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METHOD AND APPARATUS FOR PATTERN MATCHING ON SINGLE AND MULTIPLE PATTERN STRUCTURES
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08/15/2000
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09225539
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01/05/1999
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METHOD OF FORMING RELIABLE COPPER INTERCONNECTS WITH IMPROVED HOLE FILLING
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06/20/2000
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09225541
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01/05/1999
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Title:
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LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID LINED INTERCONNECTION SYSTEM
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07/03/2001
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09225542
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01/05/1999
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Title:
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DUAL DAMASCENE ARRANGEMENT FOR METAL INTERCONNECTION WITH LOW K DIELECTRIC CONSTANT MATERIALS IN DIELECTRIC LAYERS
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07/18/2000
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09225595
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01/06/1999
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PROCESS FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING A SELF-ALIGNED SPACER
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08/15/2000
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09225597
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01/06/1999
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Title:
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APPARATUS AND METHOD FOR CONTROLLING POLISHING OF INTEGRATED CIRCUIT SUBSTRATES
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06/27/2000
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09225644
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01/05/1999
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Title:
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SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY HIGH PRESSURE DEPOSITION
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01/16/2001
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09225649
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01/05/1999
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Title:
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GRADED COMPOUND SEED LAYERS FOR SEMICONDUCTORS
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09225982
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Filing Dt:
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01/05/1999
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Title:
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PHYSICAL RENAME REGISTER FOR EFFICIENTLY STORING FLOATING POINT, INTEGER CONDITION CODE, AND MULTIMEDIA VALUES
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09226564
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Filing Dt:
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01/07/1999
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Title:
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HIGH PERFORMANCE TRANSISTOR FABRICATED ON A DIELECTRIC FILM AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09226765
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Filing Dt:
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01/06/1999
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Title:
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DUAL DAMASCENE STRUCTURE FORMED IN A SINGLE PHOTORESIST FILM
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09226881
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Filing Dt:
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01/07/1999
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Title:
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ULTRA SHALLOW EXTENSION FORMATION USING DISPOSABLE SPACERS
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09227067
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Filing Dt:
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01/05/1999
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Title:
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SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY HIGH TEMPERATURE DEPOSITION
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09227695
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Filing Dt:
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01/08/1999
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Title:
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SOI BASED TFT HAVING A GATE INSULATION LAYER THICKER THAN THE CHANNEL REGION
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09228347
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Filing Dt:
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01/11/1999
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Title:
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METHODOLOGY AND GRAPHICAL USER INTERFACE FOR BUILDING LOGIC SYNTHESIS COMMAND SCRIPTS USING MICRO-TEMPLATES
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09229264
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Filing Dt:
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01/13/1999
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Title:
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METHOD OF FORMING SUBMICRON-DIMENSIONED METAL PATTERNS
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09229590
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Filing Dt:
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01/13/1999
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Title:
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SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY PULSE LASER ANNEAL
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09231427
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Filing Dt:
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01/14/1999
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Title:
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METHOD OF FABRICATING A TRANSISTOR WITH A DIELECTRIC UNDERLAYER AND DEVICE INCORPORATING SAME
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09233215
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Filing Dt:
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01/20/1999
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Title:
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MECHANISM FOR CAPTURING AND REPORTING INTERRUPT EVENTS OF DIFFERENT CLOCK DOMAINS
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09233259
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Filing Dt:
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01/19/1999
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Title:
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SYSTEM FOR CANCELING SPECULATIVELY FETCHED INSTRUCTIONS FOLLOWING A BRANCH MIS-PREDICTION IN A MICROPROCESSOR
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09233849
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Filing Dt:
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01/19/1999
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Title:
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PROCESS FOR FORMING ANTI-REFLECTIVE FILM FOR SEMICONDUCTOR FABRICATION USING EXTREMELY SHORT WAVELENGTH DEEP ULTRAVIOLET PHOTOLITHOGRAPHY
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09234456
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Filing Dt:
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01/21/1999
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Title:
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INTERRUPT MANAGEMENT SYSTEM HAVING BATCH MECHANISM FOR HANDLING INTERRUPT EVENTS
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09234528
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Filing Dt:
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01/21/1999
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Title:
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MECHANISM TO PREVENT DATA LOSS IN CASE OF A POWER FAILURE WHILE A PC IS IN SUSPEND TO RAM STATE
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09234767
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Filing Dt:
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01/21/1999
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Title:
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METHODS AND APPARATUS FOR TIMING RECOVERY FROM A SAMPLED AND EQUALIZED DATA SIGNAL
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09234855
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Filing Dt:
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01/22/1999
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Title:
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CMOS TRANSISTOR DESIGN FOR SHARED N+/P+ ELECTRODE WITH ENHANCED DEVICE PERFORMANCE
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09234992
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Filing Dt:
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01/21/1999
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Title:
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METHOD AND APPARATUS FOR MEASURING CUMULATIVE DEFECTS
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09236025
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Filing Dt:
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01/22/1999
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Title:
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INSITU HARDMASK AND METAL ETCH IN A SINGLE ETCHER
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09236622
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Filing Dt:
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01/29/1999
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Title:
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AUTOMATIC DATA QUALITY ADJUSTMENT TO REDUCE RESPONSE TIME IN BROWSING
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09237258
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Filing Dt:
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01/26/1999
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Title:
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METHOD OF FORMING MULTIPLE LEVELS OF PATTERNED METALLIZATION
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09237573
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Filing Dt:
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01/26/1999
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Title:
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APPARATUS FOR FORMING A COPPER INTERCONNECT
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09237584
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Filing Dt:
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01/26/1999
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Title:
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COPPER/LOW DIELECTRIC INTERCONNECT FORMATION WITH REDUCED ELECTROMIGRATION
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09238047
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Filing Dt:
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01/27/1999
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Title:
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NETWORK SWITCHING SYSTEM HAVING OVERFLOW BYPASS IN INTERNAL RULES CHECKER
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|
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09238051
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Filing Dt:
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01/27/1999
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Title:
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HIGH PLANARITY HIGH-DENSITY IN-LAID METALLIZATION PATTERNS BY DAMASCENE-CMP PROCESSING
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09238081
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Filing Dt:
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01/26/1999
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Title:
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MULTI-LAYER GATE CONDUCTOR HAVING A DIFFUSION BARRIER IN THE BOTTOM LAYER
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