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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 24 of 146
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1
Patent #:
6841831
Issue Dt:
01/11/2005
Application #:
10461821
Filing Dt:
06/13/2003
Publication #:
US20030211681
Pub Dt:
11/13/2003
Title:
FULLY-DEPLETED SOI MOSFETS WITH LOW SOURCE AND DRAIN RESISTANCE AND MINIMAL OVERLAP CAPACITANCE USING A RECESSED CHANNEL DAMASCENE GATE PROCESS
2
Patent #:
6927414
Issue Dt:
08/09/2005
Application #:
10462933
Filing Dt:
06/17/2003
Publication #:
US20040256614
Pub Dt:
12/23/2004
Title:
HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF
3
Patent #:
7205604
Issue Dt:
04/17/2007
Application #:
10463038
Filing Dt:
06/17/2003
Publication #:
US20040157353
Pub Dt:
08/12/2004
Title:
ULTRA SCALABLE HIGH SPEED HETEROJUNCTION VERTICAL N-CHANNEL MISFETS AND METHODS THEREOF
4
Patent #:
6727135
Issue Dt:
04/27/2004
Application #:
10464339
Filing Dt:
06/18/2003
Publication #:
US20030209765
Pub Dt:
11/13/2003
Title:
ALL-IN-ONE DISPOSABLE/PERMANENT SPACER ELEVATED SOURCE/DRAIN, SELF-ALIGNED SILICIDE CMOS
5
Patent #:
6767779
Issue Dt:
07/27/2004
Application #:
10464400
Filing Dt:
06/19/2003
Publication #:
US20030213997
Pub Dt:
11/20/2003
Title:
ASYMMETRICAL MOSFET LAYOUT FOR HIGH CURRENTS AND HIGH SPEED OPERATION
6
Patent #:
6856025
Issue Dt:
02/15/2005
Application #:
10465506
Filing Dt:
06/19/2003
Publication #:
US20030215984
Pub Dt:
11/20/2003
Title:
CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS
7
Patent #:
7045851
Issue Dt:
05/16/2006
Application #:
10465797
Filing Dt:
06/20/2003
Publication #:
US20040256662
Pub Dt:
12/23/2004
Title:
NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME
8
Patent #:
7235464
Issue Dt:
06/26/2007
Application #:
10485419
Filing Dt:
02/02/2005
Publication #:
US20050124092
Pub Dt:
06/09/2005
Title:
PATTERNING METHOD
9
Patent #:
6995391
Issue Dt:
02/07/2006
Application #:
10499538
Filing Dt:
06/21/2004
Publication #:
US20050045873
Pub Dt:
03/03/2005
Title:
ELECTRODE STRUCTURE FOR ELECTRONIC AND OPTO-ELECTRONIC DEVICES
10
Patent #:
7256670
Issue Dt:
08/14/2007
Application #:
10523310
Filing Dt:
01/27/2005
Publication #:
US20060017533
Pub Dt:
01/26/2006
Title:
DIAPHRAGM ACTIVATED MICRO-ELECTROMECHANICAL SWITCH
11
Patent #:
7388259
Issue Dt:
06/17/2008
Application #:
10536483
Filing Dt:
05/24/2005
Publication #:
US20060057787
Pub Dt:
03/16/2006
Title:
STRAINED FINFET CMOS DEVICE STRUCTURES
12
Patent #:
7329111
Issue Dt:
02/12/2008
Application #:
10537238
Filing Dt:
05/31/2005
Publication #:
US20060093697
Pub Dt:
05/04/2006
Title:
METHOD AND DEVICE FOR FLOWING A LIQUID ON A SURFACE
13
Patent #:
7314700
Issue Dt:
01/01/2008
Application #:
10537259
Filing Dt:
05/31/2005
Publication #:
US20060127800
Pub Dt:
06/15/2006
Title:
HIGH SENSITIVITY RESIST COMPOSITIONS FOR ELECTRON-BASED LITHOGRAPHY
14
Patent #:
7087499
Issue Dt:
08/08/2006
Application #:
10539333
Filing Dt:
06/15/2005
Publication #:
US20060128071
Pub Dt:
06/15/2006
Title:
INTEGRATED ANTIFUSE STRUCTURE FOR FINFET AND CMOS DEVICES
15
Patent #:
7378710
Issue Dt:
05/27/2008
Application #:
10539335
Filing Dt:
06/15/2005
Publication #:
US20060068531
Pub Dt:
03/30/2006
Title:
FINFET SRAM CELL USING INVERTED FINFET THIN FILM TRANSISTORS
16
Patent #:
7872897
Issue Dt:
01/18/2011
Application #:
10552971
Filing Dt:
10/18/2006
Publication #:
US20070242548
Pub Dt:
10/18/2007
Title:
PROGRAMMABLE SEMICONDUCTOR DEVICE
17
Patent #:
7932549
Issue Dt:
04/26/2011
Application #:
10596022
Filing Dt:
05/25/2006
Publication #:
US20090014767
Pub Dt:
01/15/2009
Title:
CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS
18
Patent #:
7935613
Issue Dt:
05/03/2011
Application #:
10596569
Filing Dt:
06/16/2006
Publication #:
US20100013044
Pub Dt:
01/21/2010
Title:
THREE-DIMENSIONAL SILICON ON OXIDE DEVICE ISOLATION
19
Patent #:
7683428
Issue Dt:
03/23/2010
Application #:
10597288
Filing Dt:
07/19/2006
Publication #:
US20090200604
Pub Dt:
08/13/2009
Title:
VERTICAL FIN-FET MOS DEVICES
20
Patent #:
7504299
Issue Dt:
03/17/2009
Application #:
10597432
Filing Dt:
07/25/2006
Publication #:
US20080246069
Pub Dt:
10/09/2008
Title:
FOLDED NODE TRENCH CAPACITOR
21
Patent #:
7960095
Issue Dt:
06/14/2011
Application #:
10597904
Filing Dt:
08/11/2006
Publication #:
US20080227030
Pub Dt:
09/18/2008
Title:
USE OF MIXED BASES TO ENHANCE PATTERNED RESIST PROFILES ON CHROME OR SENSITIVE SUBSTRATES
22
Patent #:
7148559
Issue Dt:
12/12/2006
Application #:
10604003
Filing Dt:
06/20/2003
Publication #:
US20050001290
Pub Dt:
01/06/2005
Title:
SUBSTRATE ENGINEERING FOR OPTIMUM CMOS DEVICE PERFORMANCE
23
Patent #:
6780736
Issue Dt:
08/24/2004
Application #:
10604009
Filing Dt:
06/20/2003
Title:
METHOD FOR IMAGE REVERSAL OF IMPLANT RESIST USING A SINGLE PHOTOLITHOGRAPHY EXPOSURE AND STRUCTURES FORMED THEREBY
24
Patent #:
7352815
Issue Dt:
04/01/2008
Application #:
10604025
Filing Dt:
06/23/2003
Publication #:
US20040258166
Pub Dt:
12/23/2004
Title:
DATA TRANSCEIVER AND METHOD FOR EQUALIZING THE DATA EYE OF A DIFFERENTIAL INPUT DATA SIGNAL
25
Patent #:
7030031
Issue Dt:
04/18/2006
Application #:
10604056
Filing Dt:
06/24/2003
Publication #:
US20040266201
Pub Dt:
12/30/2004
Title:
METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH DIFFUSION BARRIER MATERIAL
26
Patent #:
7350160
Issue Dt:
03/25/2008
Application #:
10604059
Filing Dt:
06/24/2003
Publication #:
US20040268284
Pub Dt:
12/30/2004
Title:
METHOD OF DISPLAYING A GUARD RING WITHIN AN INTEGRATED CIRCUIT
27
Patent #:
7289658
Issue Dt:
10/30/2007
Application #:
10604063
Filing Dt:
06/24/2003
Publication #:
US20040268290
Pub Dt:
12/30/2004
Title:
REMOVAL OF RELATIVELY UNIMPORTANT SHAPES FROM A SET OF SHAPES
28
Patent #:
6969648
Issue Dt:
11/29/2005
Application #:
10604081
Filing Dt:
06/25/2003
Publication #:
US20050009268
Pub Dt:
01/13/2005
Title:
METHOD FOR FORMING BURIED PLATE OF TRENCH CAPACITOR
29
Patent #:
6992354
Issue Dt:
01/31/2006
Application #:
10604086
Filing Dt:
06/25/2003
Publication #:
US20040262688
Pub Dt:
12/30/2004
Title:
FINFET HAVING SUPPRESSED PARASITIC DEVICE CHARACTERISTICS
30
Patent #:
6882230
Issue Dt:
04/19/2005
Application #:
10604095
Filing Dt:
06/26/2003
Publication #:
US20040263259
Pub Dt:
12/30/2004
Title:
SYSTEM AND METHOD FOR CONTROL PARAMETER RE-CENTERING IN A CONTROLLED PHASE LOCK LOOP SYSTEM
31
Patent #:
7278083
Issue Dt:
10/02/2007
Application #:
10604141
Filing Dt:
06/27/2003
Publication #:
US20040268202
Pub Dt:
12/30/2004
Title:
METHOD AND SYSTEM FOR OPTIMIZED INSTRUCTION FETCH TO PROTECT AGAINST SOFT AND HARD ERRORS
32
Patent #:
7068564
Issue Dt:
06/27/2006
Application #:
10604168
Filing Dt:
06/29/2003
Publication #:
US20040264289
Pub Dt:
12/30/2004
Title:
TIMER LOCKOUT CIRCUIT FOR SYNCHRONOUS APPLICATIONS
33
Patent #:
6897674
Issue Dt:
05/24/2005
Application #:
10604186
Filing Dt:
06/30/2003
Publication #:
US20040263199
Pub Dt:
12/30/2004
Title:
ADAPTIVE INTEGRATED CIRCUIT BASED ON TRANSISTOR CURRENT MEASUREMENTS
34
Patent #:
6995376
Issue Dt:
02/07/2006
Application #:
10604204
Filing Dt:
07/01/2003
Publication #:
US20050001171
Pub Dt:
01/06/2005
Title:
SILICON-ON-INSULATOR LATCH-UP PULSE-RADIATION DETECTOR
35
Patent #:
6943405
Issue Dt:
09/13/2005
Application #:
10604206
Filing Dt:
07/01/2003
Publication #:
US20050001273
Pub Dt:
01/06/2005
Title:
INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS
36
Patent #:
6960820
Issue Dt:
11/01/2005
Application #:
10604212
Filing Dt:
07/01/2003
Publication #:
US20050012180
Pub Dt:
01/20/2005
Title:
BIPOLAR TRANSISTOR SELF-ALIGNMENT WITH RAISED EXTRINSIC BASE EXTENSION AND METHODS OF FORMING SAME
37
Patent #:
7131074
Issue Dt:
10/31/2006
Application #:
10604277
Filing Dt:
07/08/2003
Publication #:
US20050010887
Pub Dt:
01/13/2005
Title:
NESTED VOLTAGE ISLAND ARCHITECTURE
38
Patent #:
7202764
Issue Dt:
04/10/2007
Application #:
10604278
Filing Dt:
07/08/2003
Publication #:
US20050007217
Pub Dt:
01/13/2005
Title:
NOBLE METAL CONTACTS FOR MICRO-ELECTROMECHANICAL SWITCHES
39
Patent #:
7192874
Issue Dt:
03/20/2007
Application #:
10604367
Filing Dt:
07/15/2003
Publication #:
US20050014369
Pub Dt:
01/20/2005
Title:
METHOD FOR REDUCING FOREIGN MATERIAL CONCENTRATIONS IN ETCH CHAMBERS
40
Patent #:
6954387
Issue Dt:
10/11/2005
Application #:
10604375
Filing Dt:
07/15/2003
Publication #:
US20050013185
Pub Dt:
01/20/2005
Title:
DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER
41
Patent #:
6812105
Issue Dt:
11/02/2004
Application #:
10604382
Filing Dt:
07/16/2003
Title:
ULTRA-THIN CHANNEL DEVICE WITH RAISED SOURCE AND DRAIN AND SOLID SOURCE EXTENSION DOPING
42
Patent #:
7113749
Issue Dt:
09/26/2006
Application #:
10604419
Filing Dt:
07/18/2003
Publication #:
US20050013355
Pub Dt:
01/20/2005
Title:
SYSTEM AND METHOD FOR MEASURING A HIGH SPEED SIGNAL
43
Patent #:
7359947
Issue Dt:
04/15/2008
Application #:
10604583
Filing Dt:
07/31/2003
Publication #:
US20050027803
Pub Dt:
02/03/2005
Title:
AUTONOMIC E-MAIL PROCESSING SYSTEM AND METHOD
44
Patent #:
6833603
Issue Dt:
12/21/2004
Application #:
10604696
Filing Dt:
08/11/2003
Title:
DYNAMICALLY PATTERNED SHIELDED HIGH-Q INDUCTOR
45
Patent #:
6930004
Issue Dt:
08/16/2005
Application #:
10604731
Filing Dt:
08/13/2003
Publication #:
US20050037561
Pub Dt:
02/17/2005
Title:
SELF-ALIGNED DRAIN/CHANNEL JUNCTION IN VERTICAL PASS TRANSISTOR DRAM CELL DESIGN FOR DEVICE SCALING
46
Patent #:
6897712
Issue Dt:
05/24/2005
Application #:
10604799
Filing Dt:
08/18/2003
Publication #:
US20050040864
Pub Dt:
02/24/2005
Title:
APPARATUS AND METHOD FOR DETECTING LOSS OF HIGH-SPEED SIGNAL
47
Patent #:
7291568
Issue Dt:
11/06/2007
Application #:
10604905
Filing Dt:
08/26/2003
Publication #:
US20050048705
Pub Dt:
03/03/2005
Title:
METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC
48
Patent #:
6788591
Issue Dt:
09/07/2004
Application #:
10604909
Filing Dt:
08/26/2003
Title:
SYSTEM AND METHOD FOR DIRECT WRITE TO DYNAMIC RANDOM ACCESS MEMORY (DRAM) USING PFET BIT-SWITCH
49
Patent #:
6831866
Issue Dt:
12/14/2004
Application #:
10604911
Filing Dt:
08/26/2003
Title:
METHOD AND APPARATUS FOR READ BITLINE CLAMPING FOR GAIN CELL DRAM DEVICES
50
Patent #:
6921711
Issue Dt:
07/26/2005
Application #:
10605106
Filing Dt:
09/09/2003
Publication #:
US20050051854
Pub Dt:
03/10/2005
Title:
METHOD FOR FORMING METAL REPLACEMENT GATE OF HIGH PERFORMANCE
51
Patent #:
7410846
Issue Dt:
08/12/2008
Application #:
10605108
Filing Dt:
09/09/2003
Publication #:
US20050054145
Pub Dt:
03/10/2005
Title:
METHOD FOR REDUCED N+ DIFFUSION IN STRAINED SI ON SIGE SUBSTRATE
52
Patent #:
6821833
Issue Dt:
11/23/2004
Application #:
10605110
Filing Dt:
09/09/2003
Title:
METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY
53
Patent #:
6908850
Issue Dt:
06/21/2005
Application #:
10605130
Filing Dt:
09/10/2003
Publication #:
US20050055494
Pub Dt:
03/10/2005
Title:
STRUCTURE AND METHOD FOR SILICIDED METAL GATE TRANSISTORS
54
Patent #:
6906360
Issue Dt:
06/14/2005
Application #:
10605134
Filing Dt:
09/10/2003
Publication #:
US20050051851
Pub Dt:
03/10/2005
Title:
STRUCTURE AND METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS
55
Patent #:
7112535
Issue Dt:
09/26/2006
Application #:
10605439
Filing Dt:
09/30/2003
Publication #:
US20050070102
Pub Dt:
03/31/2005
Title:
PRECISION POLYSILICON RESISTOR PROCESS
56
Patent #:
7071532
Issue Dt:
07/04/2006
Application #:
10605440
Filing Dt:
09/30/2003
Publication #:
US20050067673
Pub Dt:
03/31/2005
Title:
ADJUSTABLE SELF-ALIGNED AIR GAP DIELECTRIC FOR LOW CAPACITANCE WIRING
57
Patent #:
6876028
Issue Dt:
04/05/2005
Application #:
10605444
Filing Dt:
09/30/2003
Publication #:
US20050067701
Pub Dt:
03/31/2005
Title:
METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION
58
Patent #:
7138701
Issue Dt:
11/21/2006
Application #:
10605483
Filing Dt:
10/02/2003
Publication #:
US20050073006
Pub Dt:
04/07/2005
Title:
ELECTROSTATIC DISCHARGE PROTECTION NETWORKS FOR TRIPLE WELL SEMICONDUCTOR DEVICES
59
Patent #:
7127560
Issue Dt:
10/24/2006
Application #:
10605616
Filing Dt:
10/14/2003
Publication #:
US20050080994
Pub Dt:
04/14/2005
Title:
METHOD OF DYNAMICALLY CONTROLLING CACHE SIZE
60
Patent #:
7119403
Issue Dt:
10/10/2006
Application #:
10605672
Filing Dt:
10/16/2003
Publication #:
US20050082634
Pub Dt:
04/21/2005
Title:
HIGH PERFORMANCE STRAINED CMOS DEVICES
61
Patent #:
7284230
Issue Dt:
10/16/2007
Application #:
10605849
Filing Dt:
10/30/2003
Publication #:
US20050094863
Pub Dt:
05/05/2005
Title:
SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
62
Patent #:
7292904
Issue Dt:
11/06/2007
Application #:
10605854
Filing Dt:
10/31/2003
Publication #:
US20050096771
Pub Dt:
05/05/2005
Title:
METHOD FOR SIZING PRODUCTION LOT STARTS WITHIN A LINEAR SYSTEM PROGRAMMING ENVIRONMENT
63
Patent #:
6861716
Issue Dt:
03/01/2005
Application #:
10605861
Filing Dt:
10/31/2003
Title:
LADDER-TYPE GATE STRUCTURE FOR FOUR-TERMINAL SOI SEMICONDUCTOR DEVICE
64
Patent #:
7064409
Issue Dt:
06/20/2006
Application #:
10605885
Filing Dt:
11/04/2003
Publication #:
US20050093091
Pub Dt:
05/05/2005
Title:
STRUCTURE AND PROGRAMMING OF LASER FUSE
65
Patent #:
7015582
Issue Dt:
03/21/2006
Application #:
10605891
Filing Dt:
11/04/2003
Publication #:
US20040195670
Pub Dt:
10/07/2004
Title:
DUMMY METAL FILL SHAPES FOR IMPROVED RELIABILITY OF HYBRID OXIDE/LOW-K DIELECTRICS
66
Patent #:
6962843
Issue Dt:
11/08/2005
Application #:
10605905
Filing Dt:
11/05/2003
Publication #:
US20050093074
Pub Dt:
05/05/2005
Title:
METHOD OF FABRICATING A FINFET
67
Patent #:
7153776
Issue Dt:
12/26/2006
Application #:
10605926
Filing Dt:
11/06/2003
Publication #:
US20040099954
Pub Dt:
05/27/2004
Title:
METHOD FOR REDUCING AMINE BASED CONTAMINANTS
68
Patent #:
6879448
Issue Dt:
04/12/2005
Application #:
10609237
Filing Dt:
06/26/2003
Publication #:
US20040264007
Pub Dt:
12/30/2004
Title:
APPARATUS FOR ACHROMATIZING OPTICAL BEAMS
69
Patent #:
6876252
Issue Dt:
04/05/2005
Application #:
10609360
Filing Dt:
06/28/2003
Publication #:
US20040263237
Pub Dt:
12/30/2004
Title:
NON-ABRUPT SWITCHING OF SLEEP TRANSISTOR OF POWER GATE STRUCTURE
70
Patent #:
6936882
Issue Dt:
08/30/2005
Application #:
10614001
Filing Dt:
07/08/2003
Title:
SELECTIVE SILICIDATION OF GATES IN SEMICONDUCTOR DEVICES TO ACHIEVE MULTIPLE THRESHOLD VOLTAGES
71
Patent #:
7045384
Issue Dt:
05/16/2006
Application #:
10614031
Filing Dt:
07/08/2003
Title:
METHOD FOR DETERMINING METAL WORK FUNCTION BY FORMATION OF SCHOTTKY DIODES WITH SHADOW MASK
72
Patent #:
7235436
Issue Dt:
06/26/2007
Application #:
10614051
Filing Dt:
07/08/2003
Title:
METHOD FOR DOPING STRUCTURES IN FINFET DEVICES
73
Patent #:
7694110
Issue Dt:
04/06/2010
Application #:
10614970
Filing Dt:
07/08/2003
Title:
SYSTEM AND METHOD OF IMPLEMENTING MICROCODE OPERATIONS AS SUBROUTINES
74
Patent #:
7321964
Issue Dt:
01/22/2008
Application #:
10615101
Filing Dt:
07/08/2003
Publication #:
US20050010744
Pub Dt:
01/13/2005
Title:
STORE-TO-LOAD FORWARDING BUFFER USING INDEXED LOOKUP
75
Patent #:
7235148
Issue Dt:
06/26/2007
Application #:
10616341
Filing Dt:
07/09/2003
Publication #:
US20040007313
Pub Dt:
01/15/2004
Title:
SELECTIVELY ROUGHENING CONDUCTORS FOR HIGH FREQUENCY PRINTED WIRING BOARDS
76
Patent #:
6901003
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Title:
REDUNDANT ARRAY ARCHITECTURE FOR WORD REPLACEMENT IN CAM
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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