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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
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Patent #:	6924182	Issue Dt:	08/02/2005	Application #:	10642375	Filing Dt:	08/15/2003
Title:	STRAINED SILICON MOSFET HAVING REDUCED LEAKAGE AND METHOD OF ITS FORMATION

Patent #:	8214169	Issue Dt:	07/03/2012	Application #:	10643193	Filing Dt:	08/18/2003
Publication #:	US20050043908	Pub Dt:	02/24/2005
Title:	CIRCUITS AND METHODS FOR CHARACTERIZING RANDOM VARIATIONS IN DEVICE CHARACTERISTICS IN SEMICONDUCTOR INTEGRATED CIRCUITS

Patent #:	7923785	Issue Dt:	04/12/2011	Application #:	10643461	Filing Dt:	08/18/2003
Publication #:	US20050040477	Pub Dt:	02/24/2005
Title:	FIELD EFFECT TRANSISTOR HAVING INCREASED CARRIER MOBILITY

Patent #:	6943097	Issue Dt:	09/13/2005	Application #:	10643534	Filing Dt:	08/19/2003
Publication #:	US20050042865	Pub Dt:	02/24/2005
Title:	ATOMIC LAYER DEPOSITION OF METALLIC CONTACTS, GATES AND DIFFUSION BARRIERS

Patent #:	6952113	Issue Dt:	10/04/2005	Application #:	10644211	Filing Dt:	08/20/2003
Publication #:	US20050040881	Pub Dt:	02/24/2005
Title:	METHOD OF REDUCING LEAKAGE CURRENT IN SUB ONE VOLT SOI CIRCUITS

Patent #:	6815277	Issue Dt:	11/09/2004	Application #:	10645063	Filing Dt:	08/21/2003
Publication #:	US20040038464	Pub Dt:	02/26/2004
Title:	MULTIPLE-PLANE FINFET CMOS

Patent #:	6987689	Issue Dt:	01/17/2006	Application #:	10645240	Filing Dt:	08/20/2003
Publication #:	US20050040455	Pub Dt:	02/24/2005
Title:	NON-VOLATILE MULTI-STABLE MEMORY DEVICE AND METHODS OF MAKING AND USING THE SAME

Patent #:	7405032	Issue Dt:	07/29/2008	Application #:	10645364	Filing Dt:	08/21/2003
Title:	COMBINATION OF NON-LITHOGRAPHIC SHRINK TECHNIQUES AND TRIM PROCESS FOR GATE FORMATION AND LINE-EDGE ROUGHNESS REDUCTION

Patent #:	7964237	Issue Dt:	06/21/2011	Application #:	10645384	Filing Dt:	08/21/2003
Publication #:	US20050042381	Pub Dt:	02/24/2005
Title:	FULLY AUTOMATED PASTE DISPENSE PROCESS FOR DISPENSING SMALL DOTS AND LINES

Patent #:	7172849	Issue Dt:	02/06/2007	Application #:	10646307	Filing Dt:	08/22/2003
Publication #:	US20050042538	Pub Dt:	02/24/2005
Title:	ANTIREFLECTIVE HARDMASK AND USES THEREOF

Patent #:	6815278	Issue Dt:	11/09/2004	Application #:	10647395	Filing Dt:	08/25/2003
Title:	ULTRA-THIN SILICON-ON-INSULATOR AND STRAINED-SILICON-DIRECT-ON-INSULATOR WITH HYBRID CRYSTAL ORIENTATIONS

Patent #:	8204719	Issue Dt:	06/19/2012	Application #:	10648179	Filing Dt:	08/26/2003
Publication #:	US20050049901	Pub Dt:	03/03/2005
Title:	METHODS AND SYSTEMS FOR MODEL-BASED MANAGEMENT USING ABSTRACT MODELS

Patent #:	7081673	Issue Dt:	07/25/2006	Application #:	10648884	Filing Dt:	08/27/2003
Publication #:	US20040207084	Pub Dt:	10/21/2004
Title:	MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES

Patent #:	6894390	Issue Dt:	05/17/2005	Application #:	10649049	Filing Dt:	08/27/2003
Publication #:	US20040164409	Pub Dt:	08/26/2004
Title:	SOFT ERROR RESISTANT SEMICONDUCTOR DEVICE

Patent #:	6920061	Issue Dt:	07/19/2005	Application #:	10649200	Filing Dt:	08/27/2003
Publication #:	US20050047196	Pub Dt:	03/03/2005
Title:	LOADLESS NMOS FOUR TRANSISTOR DYNAMIC DUAL VT SRAM CELL

Patent #:	6914303	Issue Dt:	07/05/2005	Application #:	10650229	Filing Dt:	08/28/2003
Publication #:	US20050048752	Pub Dt:	03/03/2005
Title:	ULTRA THIN CHANNEL MOSFET

Patent #:	7131080	Issue Dt:	10/31/2006	Application #:	10651150	Filing Dt:	08/28/2003
Publication #:	US20050049841	Pub Dt:	03/03/2005
Title:	SIMULATION MANAGEMENT SYSTEM

Patent #:	7395524	Issue Dt:	07/01/2008	Application #:	10651186	Filing Dt:	08/28/2003
Publication #:	US20050049740	Pub Dt:	03/03/2005
Title:	METHOD, SYSTEM AND PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE HAVING CLONE LATCH SUPPORT

Patent #:	7305600	Issue Dt:	12/04/2007	Application #:	10651874	Filing Dt:	08/29/2003
Publication #:	US20050047224	Pub Dt:	03/03/2005
Title:	PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME

Patent #:	6855963	Issue Dt:	02/15/2005	Application #:	10652400	Filing Dt:	08/29/2003
Publication #:	US20050045905	Pub Dt:	03/03/2005
Title:	ULTRA HIGH-SPEED SI/SIGE MODULATION-DOPED FIELD EFFECT TRANSISTORS ON ULTRA THIN SOI/SGOI SUBSTRATE

Patent #:	6876042	Issue Dt:	04/05/2005	Application #:	10653105	Filing Dt:	09/03/2003
Title:	ADDITIONAL GATE CONTROL FOR A DOUBLE-GATE MOSFET

Patent #:	6841228	Issue Dt:	01/11/2005	Application #:	10653295	Filing Dt:	09/03/2003
Publication #:	US20040081810	Pub Dt:	04/29/2004
Title:	STRUCTURE HAVING EMBEDDED FLUSH CIRCUITRY FEATURES AND METHOD OF FABRICATING

Patent #:	7378738	Issue Dt:	05/27/2008	Application #:	10653476	Filing Dt:	09/02/2003
Publication #:	US20050045997	Pub Dt:	03/03/2005
Title:	METHOD FOR PRODUCING SELF-ALIGNED MASK, ARTICLES PRODUCED BY SAME AND COMPOSITION FOR SAME

Patent #:	7117290	Issue Dt:	10/03/2006	Application #:	10653749	Filing Dt:	09/03/2003
Publication #:	US20050050277	Pub Dt:	03/03/2005
Title:	MICROTLB AND MICRO TAG FOR REDUCING POWER IN A PROCESSOR

Patent #:	6873184	Issue Dt:	03/29/2005	Application #:	10653802	Filing Dt:	09/03/2003
Title:	CIRCULAR BUFFER USING GROUPING FOR FIND FIRST FUNCTION

Patent #:	7014966	Issue Dt:	03/21/2006	Application #:	10653844	Filing Dt:	09/02/2003
Publication #:	US20050048223	Pub Dt:	03/03/2005
Title:	METHOD AND APPARATUS FOR ELIMINATION OF BUBBLES IN IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY SYSTEMS

Patent #:	6984593	Issue Dt:	01/10/2006	Application #:	10653912	Filing Dt:	09/04/2003
Publication #:	US20040041238	Pub Dt:	03/04/2004
Title:	BETA CONTROL USING A RAPID THERMAL OXIDATION

Patent #:	6989058	Issue Dt:	01/24/2006	Application #:	10654232	Filing Dt:	09/03/2003
Publication #:	US20050048778	Pub Dt:	03/03/2005
Title:	USE OF THIN SOI TO INHIBIT RELAXATION OF SIGE LAYERS

Patent #:	6955969	Issue Dt:	10/18/2005	Application #:	10654497	Filing Dt:	09/03/2003
Publication #:	US20050048743	Pub Dt:	03/03/2005
Title:	METHOD OF GROWING AS A CHANNEL REGION TO REDUCE SOURCE/DRAIN JUNCTION CAPACITANCE

Patent #:	7051300	Issue Dt:	05/23/2006	Application #:	10655390	Filing Dt:	09/04/2003
Title:	METHOD AND SYSTEM FOR ARCHITECTURAL POWER ESTIMATION

Patent #:	6821718	Issue Dt:	11/23/2004	Application #:	10657168	Filing Dt:	09/09/2003
Publication #:	US20040048204	Pub Dt:	03/11/2004
Title:	RADIATION SENSITIVE SILICON-CONTAINING NEGATIVE RESISTS AND USE THEREOF

Patent #:	7300796	Issue Dt:	11/27/2007	Application #:	10658859	Filing Dt:	09/09/2003
Publication #:	US20050054109	Pub Dt:	03/10/2005
Title:	PRESSURIZED OXYGEN FOR EVALUATION OF MOLDING COMPOUND STABILITY IN SEMICONDUCTOR PACKAGING

Patent #:	6928377	Issue Dt:	08/09/2005	Application #:	10658940	Filing Dt:	09/09/2003
Publication #:	US20050055173	Pub Dt:	03/10/2005
Title:	SELF-TEST ARCHITECTURE TO IMPLEMENT DATA COLUMN REDUNDANCY IN A RAM

Patent #:	6815296	Issue Dt:	11/09/2004	Application #:	10659950	Filing Dt:	09/11/2003
Publication #:	US20040046208	Pub Dt:	03/11/2004
Title:	POLYSILICON BACK-GATED SOI MOSFET FOR DYNAMIC THRESHOLD VOLTAGE CONTROL

Patent #:	7138669	Issue Dt:	11/21/2006	Application #:	10660048	Filing Dt:	09/11/2003
Publication #:	US20050051798	Pub Dt:	03/10/2005
Title:	SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATION

Patent #:	7170030	Issue Dt:	01/30/2007	Application #:	10660477	Filing Dt:	09/12/2003
Publication #:	US20050056625	Pub Dt:	03/17/2005
Title:	METHOD AND APPARATUS FOR REPAIR OF REFLECTIVE PHOTOMASKS

Patent #:	7030008	Issue Dt:	04/18/2006	Application #:	10661041	Filing Dt:	09/12/2003
Publication #:	US20050056823	Pub Dt:	03/17/2005
Title:	TECHNIQUES FOR PATTERNING FEATURES IN SEMICONDUCTOR DEVICES

Patent #:	6917662	Issue Dt:	07/12/2005	Application #:	10661050	Filing Dt:	09/11/2003
Publication #:	US20050057285	Pub Dt:	03/17/2005
Title:	PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER

Patent #:	7029951	Issue Dt:	04/18/2006	Application #:	10661299	Filing Dt:	09/12/2003
Publication #:	US20050059238	Pub Dt:	03/17/2005
Title:	COOLING SYSTEM FOR A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

Patent #:	6954879	Issue Dt:	10/11/2005	Application #:	10661894	Filing Dt:	09/12/2003
Title:	METHOD AND APPARATUS FOR COMMUNICATING CONFIGURATION DATA FOR A PERIPHERAL DEVICE OF A MICROCONTROLLER VIA A SCAN PATH

Patent #:	7067437	Issue Dt:	06/27/2006	Application #:	10662022	Filing Dt:	09/12/2003
Publication #:	US20050059258	Pub Dt:	03/17/2005
Title:	STRUCTURES WITH IMPROVED INTERFACIAL STRENGTH OF SICOH DIELECTRICS AND METHOD FOR PREPARING THE SAME

Patent #:	7384868	Issue Dt:	06/10/2008	Application #:	10662900	Filing Dt:	09/15/2003
Publication #:	US20050059242	Pub Dt:	03/17/2005
Title:	REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SIGE CONTAINING SUBSTRATES

Patent #:	7114136	Issue Dt:	09/26/2006	Application #:	10663020	Filing Dt:	09/16/2003
Publication #:	US20050262454	Pub Dt:	11/24/2005
Title:	METHOD FOR VLSI SYSTEM DEBUG AND TIMING ANALYSIS

Patent #:	7205185	Issue Dt:	04/17/2007	Application #:	10663471	Filing Dt:	09/15/2003
Publication #:	US20050059252	Pub Dt:	03/17/2005
Title:	SELF-ALIGNED PLANAR DOUBLE-GATE PROCESS BY SELF-ALIGNED OXIDATION

Patent #:	7313573	Issue Dt:	12/25/2007	Application #:	10663907	Filing Dt:	09/17/2003
Publication #:	US20050060323	Pub Dt:	03/17/2005
Title:	DIAGNOSIS OF EQUIPMENT FAILURES USING AN INTEGRATED APPROACH OF CASE BASED REASONING AND RELIABILITY ANALYSIS

Patent #:	7205165	Issue Dt:	04/17/2007	Application #:	10664665	Filing Dt:	09/18/2003
Title:	METHOD FOR DETERMINING THE RELIABILITY OF DIELECTRIC LAYERS

Patent #:	7176927	Issue Dt:	02/13/2007	Application #:	10665289	Filing Dt:	09/22/2003
Publication #:	US20040054834	Pub Dt:	03/18/2004
Title:	METHOD AND SYSTEM FOR GRAPHICS RENDERING USING HARDWARE-EVENT-TRIGGERED EXECUTION OF CAPTURED GRAPHICS HARDWARE INSTRUCTIONS

Patent #:	6882052	Issue Dt:	04/19/2005	Application #:	10665322	Filing Dt:	09/20/2003
Publication #:	US20040060617	Pub Dt:	04/01/2004
Title:	PLASMA ENHANCED LINER

Patent #:	7063127	Issue Dt:	06/20/2006	Application #:	10665798	Filing Dt:	09/18/2003
Publication #:	US20050061474	Pub Dt:	03/24/2005
Title:	METHOD AND APPARATUS FOR CHIP-COOLING

Patent #:	7428716	Issue Dt:	09/23/2008	Application #:	10666353	Filing Dt:	09/19/2003
Publication #:	US20050065765	Pub Dt:	03/24/2005
Title:	SYSTEM AND METHOD FOR STATISTICAL TIMING ANALYSIS OF DIGITAL CIRCUITS

Patent #:	7175966	Issue Dt:	02/13/2007	Application #:	10666541	Filing Dt:	09/19/2003
Publication #:	US20050064322	Pub Dt:	03/24/2005
Title:	WATER AND AQUEOUS BASE SOLUBLE ANTIREFLECTIVE COATING/HARDMASK MATERIALS

Patent #:	7361991	Issue Dt:	04/22/2008	Application #:	10666564	Filing Dt:	09/19/2003
Publication #:	US20050062165	Pub Dt:	03/24/2005
Title:	Closed air gap interconnect structure

Patent #:	6872641	Issue Dt:	03/29/2005	Application #:	10667603	Filing Dt:	09/23/2003
Publication #:	US20050064686	Pub Dt:	03/24/2005
Title:	STRAINED SILICON ON RELAXED SIGE FILM WITH UNIFORM MISFIT DISLOCATION DENSITY

Patent #:	6985645	Issue Dt:	01/10/2006	Application #:	10669944	Filing Dt:	09/24/2003
Publication #:	US20050063634	Pub Dt:	03/24/2005
Title:	APPARATUS AND METHODS FOR INTEGRALLY PACKAGING OPTOELECTRONIC DEVICES, IC CHIPS AND OPTICAL TRANSMISSION LINES

Patent #:	7523157	Issue Dt:	04/21/2009	Application #:	10670823	Filing Dt:	09/25/2003
Publication #:	US20050091473	Pub Dt:	04/28/2005
Title:	MANAGING A PLURALITY OF PROCESSORS AS DEVICES

Patent #:	7078341	Issue Dt:	07/18/2006	Application #:	10673648	Filing Dt:	09/30/2003
Publication #:	US20050079708	Pub Dt:	04/14/2005
Title:	METHOD OF DEPOSITING METAL LAYERS FROM METAL-CARBONYL PRECURSORS

Patent #:	7355872	Issue Dt:	04/08/2008	Application #:	10673801	Filing Dt:	09/29/2003
Publication #:	US20050071544	Pub Dt:	03/31/2005
Title:	SEGMENTED CONTENT ADDRESSABLE MEMORY ARCHITECTURE FOR IMPROVED CYCLE TIME AND REDUCED POWER CONSUMPTION

Patent #:	6995438	Issue Dt:	02/07/2006	Application #:	10674478	Filing Dt:	10/01/2003
Title:	SEMICONDUCTOR DEVICE WITH FULLY SILICIDED SOURCE/DRAIN AND DAMASCENE METAL GATE

Patent #:	6855989	Issue Dt:	02/15/2005	Application #:	10674520	Filing Dt:	10/01/2003
Title:	DAMASCENE FINFET GATE WITH SELECTIVE METAL INTERDIFFUSION

Patent #:	6821826	Issue Dt:	11/23/2004	Application #:	10674644	Filing Dt:	09/30/2003
Title:	THREE DIMENSIONAL CMOS INTEGRATED CIRCUITS HAVING DEVICE LAYERS BUILT ON DIFFERENT CRYSTAL ORIENTED WAFERS

Patent #:	7352066	Issue Dt:	04/01/2008	Application #:	10675139	Filing Dt:	09/30/2003
Publication #:	US20070085215	Pub Dt:	04/19/2007
Title:	SILICON BASED OPTICAL VIAS

Patent #:	7052958	Issue Dt:	05/30/2006	Application #:	10675625	Filing Dt:	09/30/2003
Title:	FINFET CMOS WITH NVRAM CAPABILITY

Patent #:	6787427	Issue Dt:	09/07/2004	Application #:	10676171	Filing Dt:	10/01/2003
Publication #:	US20040063293	Pub Dt:	04/01/2004
Title:	METHOD TO FABRICATE SIGE HBTS WITH CONTROLLED CURRENT GAIN AND IMPROVED BREAKDOWN VOLTAGE CHARACTERISTICS

Patent #:	7133969	Issue Dt:	11/07/2006	Application #:	10676437	Filing Dt:	10/01/2003
Publication #:	US20050076180	Pub Dt:	04/07/2005
Title:	SYSTEM AND METHOD FOR HANDLING EXCEPTIONAL INSTRUCTIONS IN A TRACE CACHE BASED PROCESSOR

Patent #:	7069155	Issue Dt:	06/27/2006	Application #:	10676455	Filing Dt:	10/01/2003
Title:	REAL TIME ANALYTICAL MONITOR FOR SOFT DEFECTS ON RETICLE DURING RETICLE INSPECTION

Patent #:	7165172	Issue Dt:	01/16/2007	Application #:	10676600	Filing Dt:	10/01/2003
Title:	FACILITATING COLD RESET AND WARM RESET TASKING IN A COMPUTER SYSTEM

Patent #:	7043626	Issue Dt:	05/09/2006	Application #:	10676636	Filing Dt:	10/01/2003
Title:	Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

Patent #:	7056646	Issue Dt:	06/06/2006	Application #:	10676749	Filing Dt:	10/01/2003
Title:	USE OF BASE DEVELOPERS AS IMMERSION LITHOGRAPHY FLUID

Patent #:	6967363	Issue Dt:	11/22/2005	Application #:	10676904	Filing Dt:	10/01/2003
Title:	LATERAL DIODE WITH MULTIPLE SPACERS

Patent #:	6801368	Issue Dt:	10/05/2004	Application #:	10679058	Filing Dt:	10/02/2003
Publication #:	US20040061952	Pub Dt:	04/01/2004
Title:	SYSTEM FOR CONVERTING OPTICAL BEAMS TO COLLIMATED FLAT-TOP BEAMS

Patent #:	7270931	Issue Dt:	09/18/2007	Application #:	10679782	Filing Dt:	10/06/2003
Publication #:	US20050074689	Pub Dt:	04/07/2005
Title:	SILICON-CONTAINING COMPOSITIONS FOR SPIN-ON ARC/HARDMASK MATERIALS

Patent #:	7340660	Issue Dt:	03/04/2008	Application #:	10680679	Filing Dt:	10/07/2003
Publication #:	US20050076279	Pub Dt:	04/07/2005
Title:	METHOD AND SYSTEM FOR USING STATISTICAL SIGNATURES FOR TESTING HIGH-SPEED CIRCUITS

Patent #:	6927454	Issue Dt:	08/09/2005	Application #:	10680820	Filing Dt:	10/07/2003
Publication #:	US20050073014	Pub Dt:	04/07/2005
Title:	SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK

Patent #:	6956296	Issue Dt:	10/18/2005	Application #:	10681513	Filing Dt:	10/08/2003
Publication #:	US20040071805	Pub Dt:	04/15/2004
Title:	TRANSFER MOLDING OF INTEGRATED CIRCUIT PACKAGES

Patent #:	7023712	Issue Dt:	04/04/2006	Application #:	10683278	Filing Dt:	10/14/2003
Publication #:	US20040119439	Pub Dt:	06/24/2004
Title:	COOLING ARRANGEMENT IN FREQUENCY CONVERTER

Patent #:	7268432	Issue Dt:	09/11/2007	Application #:	10683333	Filing Dt:	10/10/2003
Publication #:	US20050079719	Pub Dt:	04/14/2005
Title:	INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY

Patent #:	6924682	Issue Dt:	08/02/2005	Application #:	10683823	Filing Dt:	10/10/2003
Title:	LATCH CIRCUIT WITH METASTABILITY TRAP AND METHOD THEREFOR

Patent #:	7091612	Issue Dt:	08/15/2006	Application #:	10684952	Filing Dt:	10/14/2003
Publication #:	US20050077628	Pub Dt:	04/14/2005
Title:	DUAL DAMASCENE STRUCTURE AND METHOD

Patent #:	6949761	Issue Dt:	09/27/2005	Application #:	10685013	Filing Dt:	10/14/2003
Publication #:	US20050077510	Pub Dt:	04/14/2005
Title:	STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-MOBILITY FIELD-EFFECT TRANSISTOR

Patent #:	6920062	Issue Dt:	07/19/2005	Application #:	10685828	Filing Dt:	10/14/2003
Publication #:	US20050078509	Pub Dt:	04/14/2005
Title:	SYSTEM AND METHOD FOR READING DATA STORED ON A MAGNETIC SHIFT REGISTER

Patent #:	6970379	Issue Dt:	11/29/2005	Application #:	10685835	Filing Dt:	10/14/2003
Publication #:	US20050078511	Pub Dt:	04/14/2005
Title:	SYSTEM AND METHOD FOR STORING DATA IN AN UNPATTERNED, CONTINUOUS MAGNETIC LAYER

Patent #:	6958506	Issue Dt:	10/25/2005	Application #:	10688508	Filing Dt:	10/17/2003
Publication #:	US20040087100	Pub Dt:	05/06/2004
Title:	HIGH-DIELECTRIC CONSTANT INSULATORS FOR FEOL CAPACITORS

Patent #:	7034362	Issue Dt:	04/25/2006	Application #:	10688692	Filing Dt:	10/17/2003
Publication #:	US20050082531	Pub Dt:	04/21/2005
Title:	DOUBLE SILICON-ON-INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) STRUCTURES

Patent #:	7628974	Issue Dt:	12/08/2009	Application #:	10689675	Filing Dt:	10/22/2003
Publication #:	US20050089467	Pub Dt:	04/28/2005
Title:	CONTROL OF CARBON NANOTUBE DIAMETER USING CVD OR PECVD GROWTH

Patent #:	6833625	Issue Dt:	12/21/2004	Application #:	10690434	Filing Dt:	10/21/2003
Title:	SELF-ALIGNED BARRIER FORMED WITH AN ALLOY HAVING AT LEAST TWO DOPANT ELEMENTS FOR MINIMIZED RESISTANCE OF INTERCONNECT

Patent #:	7081676	Issue Dt:	07/25/2006	Application #:	10691299	Filing Dt:	10/22/2003
Publication #:	US20040087160	Pub Dt:	05/06/2004
Title:	Structure for controlling the interface roughness of cobalt disilicide

Patent #:	7329446	Issue Dt:	02/12/2008	Application #:	10691882	Filing Dt:	10/23/2003
Publication #:	US20040086741	Pub Dt:	05/06/2004
Title:	DRILL STACK FORMATION

Patent #:	7244341	Issue Dt:	07/17/2007	Application #:	10693276	Filing Dt:	10/23/2003
Publication #:	US20040206619	Pub Dt:	10/21/2004
Title:	METHOD TO ACHIEVE LOW AND STABLE FERROMAGNETIC COUPLING FIELD

Patent #:	7366342	Issue Dt:	04/29/2008	Application #:	10694299	Filing Dt:	10/27/2003
Publication #:	US20050089211	Pub Dt:	04/28/2005
Title:	SIMULTANEOUS COMPUTATION OF MULTIPLE POINTS ON ONE OR MULTIPLE CUT LINES

Patent #:	7343271	Issue Dt:	03/11/2008	Application #:	10694465	Filing Dt:	10/27/2003
Publication #:	US20050091013	Pub Dt:	04/28/2005
Title:	INCORPORATION OF A PHASE MAP INTO FAST MODEL-BASED OPTICAL PROXIMITY CORRECTION SIMULATION KERNELS TO ACCOUNT FOR NEAR AND MID-RANGE FLARE

Patent #:	7010776	Issue Dt:	03/07/2006	Application #:	10694466	Filing Dt:	10/27/2003
Publication #:	US20050091631	Pub Dt:	04/28/2005
Title:	EXTENDING THE RANGE OF LITHOGRAPHIC SIMULATION INTEGRALS

Patent #:	7287239	Issue Dt:	10/23/2007	Application #:	10694473	Filing Dt:	10/27/2003
Publication #:	US20050091014	Pub Dt:	04/28/2005
Title:	PERFORMANCE IN MODEL-BASED OPC ENGINE UTILIZING EFFICIENT POLYGON PINNING METHOD

Patent #:	7163883	Issue Dt:	01/16/2007	Application #:	10694500	Filing Dt:	10/27/2003
Publication #:	US20040087078	Pub Dt:	05/06/2004
Title:	EDGE SEAL FOR A SEMICONDUCTOR DEVICE

Patent #:	7173303	Issue Dt:	02/06/2007	Application #:	10695335	Filing Dt:	10/28/2003
Publication #:	US20040092060	Pub Dt:	05/13/2004
Title:	FIN FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE

Patent #:	7247924	Issue Dt:	07/24/2007	Application #:	10695336	Filing Dt:	10/28/2003
Publication #:	US20040084754	Pub Dt:	05/06/2004
Title:	METHOD OF CONTROLLING GRAIN SIZE IN A POLYSILICON LAYER AND IN SEMICONDUCTOR DEVICES HAVING POLYSILICON STRUCTURES

Patent #:	8008724	Issue Dt:	08/30/2011	Application #:	10695748	Filing Dt:	10/30/2003
Publication #:	US20050093030	Pub Dt:	05/05/2005
Title:	STRUCTURE AND METHOD TO ENHANCE BOTH NFET AND PFET PERFORMANCE USING DIFFERENT KINDS OF STRESSED LAYERS

Patent #:	6977194	Issue Dt:	12/20/2005	Application #:	10695752	Filing Dt:	10/30/2003
Publication #:	US20050093059	Pub Dt:	05/05/2005
Title:	STRUCTURE AND METHOD TO IMPROVE CHANNEL MOBILITY BY GATE ELECTRODE STRESS MODIFICATION

Patent #:	6927611	Issue Dt:	08/09/2005	Application #:	10696139	Filing Dt:	10/29/2003
Publication #:	US20050093591	Pub Dt:	05/05/2005
Title:	SEMIDIGITAL DELAY-LOCKED LOOP USING AN ANALOG-BASED FINITE STATE MACHINE

Patent #:	7353359	Issue Dt:	04/01/2008	Application #:	10696511	Filing Dt:	10/28/2003
Publication #:	US20050091298	Pub Dt:	04/28/2005
Title:	AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX

100

Patent #:	7329361	Issue Dt:	02/12/2008	Application #:	10696771	Filing Dt:	10/29/2003
Publication #:	US20050095858	Pub Dt:	05/05/2005
Title:	METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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