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02/23/2006
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03/09/2006
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08/09/2007
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03/02/2006
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03/02/2006
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03/02/2006
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03/09/2006
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03/16/2006
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03/16/2006
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04/06/2006
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03/23/2006
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03/30/2006
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04/13/2006
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04/13/2006
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09/27/2005
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05/19/2005
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05/19/2005
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05/27/2004
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05/26/2005
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05/26/2005
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06/10/2004
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05/26/2005
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06/29/2010
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Application #:
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10736424
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Filing Dt:
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12/15/2003
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
Title:
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TESTING OF TRANSIMPEDANCE AMPLIFIERS
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10737626
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Filing Dt:
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12/16/2003
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Publication #:
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Pub Dt:
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06/16/2005
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Title:
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METHOD FOR OPTIMIZING A NUMBER OF KERNELS USED IN A SUM OF COHERENT SOURCES FOR OPTICAL PROXIMITY CORRECTION IN AN OPTICAL MICROLITHOGRAPHY PROCESS
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10738064
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Filing Dt:
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12/17/2003
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Publication #:
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Pub Dt:
|
06/23/2005
| | | | |
Title:
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SILICON CARRIER FOR OPTICAL INTERCONNECT MODULES
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Patent #:
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Issue Dt:
|
09/13/2005
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Application #:
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10738529
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Filing Dt:
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12/17/2003
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Title:
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SEMICONDUCTOR ON INSULATOR MOSFET HAVING STRAINED SILICON CHANNEL
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Patent #:
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Issue Dt:
|
10/24/2006
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Application #:
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10738711
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Filing Dt:
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12/17/2003
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Publication #:
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Pub Dt:
|
06/23/2005
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Title:
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METHOD AND APPARATUS FOR GENERATING STEINER TREES USING SIMULTANEOUS BLOCKAGE AVOIDANCE, DELAY OPTIMIZATION AND DESIGN DENSITY MANAGEMENT
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Patent #:
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Issue Dt:
|
11/14/2006
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Application #:
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10738714
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Filing Dt:
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12/17/2003
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Publication #:
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Pub Dt:
|
06/23/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR PERFORMING DENSITY-BIASED BUFFER INSERTION IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
07/04/2006
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Application #:
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10738716
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Filing Dt:
|
12/17/2003
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Title:
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STRAINED SILICON PMOS HAVING SILICON GERMANIUM SOURCE/DRAIN EXTENSIONS AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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07/01/2008
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Application #:
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10739966
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
|
06/23/2005
| | | | |
Title:
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DATA STORAGE SYSTEMS
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Patent #:
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Issue Dt:
|
01/27/2009
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Application #:
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10740546
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Filing Dt:
|
12/22/2003
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Title:
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METHOD FOR REDUCING FLOATING BODY EFFECTS IN SOI SEMICONDUCTOR DEVICE WITHOUT DEGRADING MOBILITY
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Patent #:
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Issue Dt:
|
10/17/2006
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Application #:
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10741203
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
|
06/23/2005
| | | | |
Title:
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DEEP TRENCH CAPACITOR WITH BURIED PLATE ELECTRODE AND ISOLATION COLLAR
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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10745044
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
|
11/04/2004
| | | | |
Title:
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METHOD OF PROVIDING CONTEXT SPECIFIC RECIPES IN A SEMICONDUCTOR FACILITY BY DEFINING PRODUCT CATEGORIES
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Patent #:
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Issue Dt:
|
09/04/2012
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Application #:
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10745822
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
|
09/30/2004
| | | | |
Title:
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LOCATING A TESTABLE OBJECT IN A FUNCTIONAL TESTING TOOL
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10747680
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
|
07/07/2005
| | | | |
Title:
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METHOD FOR FORMING RECTANGULAR-SHAPED SPACERS FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10747722
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
|
12/16/2004
| | | | |
Title:
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METHOD OF REDUCING WAFER CONTAMINATION BY REMOVING UNDER-METAL LAYERS AT THE WAFER EDGE
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Patent #:
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Issue Dt:
|
12/19/2006
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Application #:
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10747723
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
|
12/02/2004
| | | | |
Title:
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METHOD AND SYSTEM FOR CONTROLLING THE CHEMICAL MECHANICAL POLISHING BY USING A SENSOR SIGNAL OF A PAD CONDITIONER
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10749607
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
|
07/07/2005
| | | | |
Title:
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METHOD AND SYSTEM FOR SELECTIVE COMPILATION OF INSTRUMENTATION ENTITIES INTO A SIMULATION MODEL OF A DIGITAL DESIGN
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10750697
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Filing Dt:
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01/02/2004
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Publication #:
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Pub Dt:
|
07/22/2004
| | | | |
Title:
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ENHANCED T-GATE STRUCTURE FOR MODULATION DOPED FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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12/04/2012
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Application #:
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10751714
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Filing Dt:
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01/05/2004
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Publication #:
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Pub Dt:
|
07/07/2005
| | | | |
Title:
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AMPLIFIERS USING GATED DIODES
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Patent #:
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Issue Dt:
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01/20/2009
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Application #:
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10751831
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Filing Dt:
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01/05/2004
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Publication #:
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Pub Dt:
|
12/02/2004
| | | | |
Title:
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STI STRESS MODIFICATION BY NITROGEN PLASMA TREATMENT FOR IMPROVING PERFORMANCE IN SMALL WIDTH DEVICES
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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10751916
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Filing Dt:
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01/07/2004
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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HIGH PERFORMANCE STRAINED SILICON FINFETS DEVICE AND METHOD FOR FORMING SAME
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Patent #:
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Issue Dt:
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04/01/2008
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Application #:
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10753241
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Filing Dt:
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01/08/2004
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Publication #:
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Pub Dt:
|
07/22/2004
| | | | |
Title:
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INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION OR NITRIDIZATION
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10753989
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Filing Dt:
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01/08/2004
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Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
Title:
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POSITIVE PHOTORESIST COMPOSITION WITH A POLYMER INCLUDING A FLUOROSULFONAMIDE GROUP AND PROCESS FOR ITS USE
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10754320
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Filing Dt:
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01/08/2004
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Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
Title:
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DISCRIMINATIVE SOI WITH OXIDE HOLES UNDERNEATH DC SOURCE/DRAIN
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Patent #:
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Issue Dt:
|
03/16/2010
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Application #:
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10754515
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Filing Dt:
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01/12/2004
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Title:
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FINFET DEVICE WITH MULTIPLE FIN STRUCTURES
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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10755344
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Filing Dt:
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01/13/2004
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Title:
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FINFET DEVICE WITH MULTIPLE CHANNELS
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Patent #:
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Issue Dt:
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12/09/2008
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Application #:
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10755602
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Filing Dt:
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01/12/2004
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Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
Title:
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SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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10755692
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Filing Dt:
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01/12/2004
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Title:
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CONTROLLING WRITES TO NON-RENAMED REGISTER SPACE IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10755734
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Filing Dt:
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01/12/2004
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Title:
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CACHE MEMORY SUBSYSTEM INCLUDING A FIXED LATENCY R/W PIPELINE
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Patent #:
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Issue Dt:
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05/01/2007
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Application #:
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10755742
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Filing Dt:
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01/12/2004
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Title:
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METHOD AND PROCESSOR INCLUDING LOGIC FOR STORING TRACES WITHIN A TRACE CACHE
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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10755746
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Filing Dt:
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01/12/2004
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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SILICON BUFFERED SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10755763
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Filing Dt:
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01/12/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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Method of fabricating an integrated circuit channel region
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10755816
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Filing Dt:
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01/12/2004
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Publication #:
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Pub Dt:
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04/21/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR THERMO-OPTIC MODULATION OF OPTICAL SIGNALS
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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10755875
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Filing Dt:
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01/13/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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REAL-TIME CONFIGURABLE MASKING
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10757846
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Filing Dt:
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01/15/2004
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Publication #:
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Pub Dt:
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07/21/2005
| | | | |
Title:
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CONCURRENT REFRESH MODE WITH DISTRIBUTED ROW ADDRESS COUNTERS IN AN EMBEDDED DRAM
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10758724
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Filing Dt:
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01/16/2004
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Publication #:
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Pub Dt:
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07/21/2005
| | | | |
Title:
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LOW K AND ULTRA LOW K SICOH DIELECTRIC FILMS AND METHODS TO FORM THE SAME
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10759170
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Filing Dt:
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01/20/2004
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Publication #:
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Pub Dt:
|
07/29/2004
| | | | |
Title:
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PROTECTION OF LOW-K ILD DURING DAMASCENE PROCESSING WITH THIN LINER
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10761009
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Filing Dt:
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01/20/2004
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Title:
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METHOD FOR FORMING A THIN, HIGH QUALITY BUFFER LAYER IN A FIELD EFFECT TRANSISTOR AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10761374
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Filing Dt:
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01/22/2004
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Title:
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REVERSED T-SHAPED FINFET
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10763308
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Filing Dt:
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01/23/2004
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Publication #:
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Pub Dt:
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09/30/2004
| | | | |
Title:
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CMOS DEVICE INTEGRATION FOR LOW EXTERNAL RESISTANCE
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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10765042
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Filing Dt:
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01/28/2004
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Pub Dt:
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07/28/2005
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Title:
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HIGH PERFORMANCE INTERPOSER FOR A CHIP PACKAGE USING DEFORMABLE BUTTON CONTACTS
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10766249
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Filing Dt:
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01/27/2004
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Publication #:
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Pub Dt:
|
09/30/2004
| | | | |
Title:
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ELECTRONIC STRUCTURES WITH REDUCED CAPACITANCE
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