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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
03/20/2007
Application #:
10711023
Filing Dt:
08/18/2004
Publication #:
Pub Dt:
02/23/2006
Title:
MULTIPLE POWER DENSITY CHIP STRUCTURE
2
Patent #:
Issue Dt:
04/17/2007
Application #:
10711079
Filing Dt:
08/20/2004
Publication #:
Pub Dt:
03/09/2006
Title:
METHOD AND SYSTEM FOR INTELLIGENT AUTOMATED RETICLE MANAGEMENT
3
Patent #:
Issue Dt:
08/07/2007
Application #:
10711145
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
MAINTAINING UNIFORM CMP HARD MASK THICKNESS
4
Patent #:
Issue Dt:
03/25/2008
Application #:
10711182
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
08/09/2007
Title:
STRUCTURE AND METHOD OF MAKING DOUBLE-GATED SELF-ALIGNED FINFET HAVING GATES OF DIFFERENT LENGTHS
5
Patent #:
Issue Dt:
06/17/2008
Application #:
10711200
Filing Dt:
09/01/2004
Publication #:
Pub Dt:
03/02/2006
Title:
MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE
6
Patent #:
Issue Dt:
08/29/2006
Application #:
10711205
Filing Dt:
09/01/2004
Publication #:
Pub Dt:
03/02/2006
Title:
LOW VOLTAGE PROGRAMMABLE EFUSE WITH DIFFERENTIAL SENSING SCHEME
7
Patent #:
Issue Dt:
07/29/2008
Application #:
10711224
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
03/02/2006
Title:
SELF HEATING MONITOR FOR SIGE AND SOI CMOS DEVICES
8
Patent #:
Issue Dt:
10/16/2012
Application #:
10711298
Filing Dt:
09/09/2004
Publication #:
Pub Dt:
03/09/2006
Title:
VIA CONTACT STRUCTURE HAVING DUAL SILICIDE LAYERS
9
Patent #:
Issue Dt:
01/08/2008
Application #:
10711367
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/16/2006
Title:
WIRE BOND PADS
10
Patent #:
Issue Dt:
10/23/2007
Application #:
10711394
Filing Dt:
09/16/2004
Publication #:
Pub Dt:
03/16/2006
Title:
AIR-GAP INSULATED INTERCONNECTIONS
11
Patent #:
Issue Dt:
06/12/2007
Application #:
10711418
Filing Dt:
09/17/2004
Publication #:
Pub Dt:
04/06/2006
Title:
DETERMINATION OF GRAIN SIZES OF ELECTRICALLY CONDUCTIVE LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS
12
Patent #:
Issue Dt:
09/04/2007
Application #:
10711486
Filing Dt:
09/21/2004
Publication #:
Pub Dt:
03/23/2006
Title:
METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BICMOS TECHNOLOGY
13
Patent #:
Issue Dt:
08/05/2008
Application #:
10711713
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
HIGH SPEED MULTI-MODE RECEIVER WITH ADAPTIVE RECEIVER EQUALIZATION AND CONTROLLABLE TRANSMITTER PRE-DISTORTION
14
Patent #:
Issue Dt:
06/19/2007
Application #:
10711764
Filing Dt:
10/04/2004
Publication #:
Pub Dt:
04/06/2006
Title:
LOW-K DIELECTRIC LAYER BASED UPON CARBON NANOSTRUCTURES
15
Patent #:
Issue Dt:
11/25/2008
Application #:
10711845
Filing Dt:
10/08/2004
Publication #:
Pub Dt:
04/13/2006
Title:
FIN-TYPE ANTIFUSE
16
Patent #:
Issue Dt:
08/12/2008
Application #:
10711885
Filing Dt:
10/12/2004
Publication #:
Pub Dt:
04/13/2006
Title:
CONTOUR STRUCTURES TO HIGHLIGHT INSPECTION REGIONS
17
Patent #:
Issue Dt:
07/22/2008
Application #:
10711899
Filing Dt:
10/12/2004
Publication #:
Pub Dt:
04/13/2006
Title:
ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION
18
Patent #:
Issue Dt:
04/22/2008
Application #:
10711959
Filing Dt:
10/15/2004
Publication #:
Pub Dt:
04/20/2006
Title:
INTEGRATED CIRCUIT SELECTIVE SCALING
19
Patent #:
Issue Dt:
09/27/2005
Application #:
10711974
Filing Dt:
10/18/2004
Title:
PLANAR SUBSTRATE DEVICES INTEGRATED WITH FINFETS AND METHOD OF MANUFACTURE
20
Patent #:
Issue Dt:
02/26/2008
Application #:
10711978
Filing Dt:
10/18/2004
Publication #:
Pub Dt:
04/20/2006
Title:
IMPROVING SYSTEMATIC YIELD IN SEMICONDUCTOR MANUFACTURE
21
Patent #:
Issue Dt:
07/15/2008
Application #:
10712925
Filing Dt:
11/13/2003
Publication #:
Pub Dt:
05/19/2005
Title:
BUILT IN SELF TEST CIRCUIT FOR MEASURING TOTAL TIMING UNCERTAINTY IN A DIGITAL DATA PATH
22
Patent #:
Issue Dt:
06/20/2006
Application #:
10713227
Filing Dt:
11/13/2003
Publication #:
Pub Dt:
05/19/2005
Title:
METHOD AND STRUCTURE TO USE AN ETCH RESISTANT LINER ON TRANSISTOR GATE STRUCTURE TO ACHIEVE HIGH DEVICE PERFORMANCE
23
Patent #:
Issue Dt:
11/07/2006
Application #:
10713447
Filing Dt:
11/14/2003
Publication #:
Pub Dt:
05/19/2005
Title:
CMOS WELL STRUCTURE AND METHOD OF FORMING THE SAME
24
Patent #:
Issue Dt:
11/21/2006
Application #:
10715288
Filing Dt:
11/17/2003
Publication #:
Pub Dt:
05/19/2005
Title:
INTERPOSER WITH ELECTRICAL CONTACT BUTTON AND METHOD
25
Patent #:
Issue Dt:
10/13/2009
Application #:
10715376
Filing Dt:
11/19/2003
Publication #:
Pub Dt:
05/19/2005
Title:
SPIN-CURRENT SWITCHED MAGNETIC MEMORY ELEMENT SUITABLE FOR CIRCUIT INTEGRATION AND METHOD OF FABRICATING THE MEMORY ELEMENT
26
Patent #:
Issue Dt:
03/08/2011
Application #:
10715689
Filing Dt:
11/18/2003
Publication #:
Pub Dt:
05/19/2005
Title:
ULTRAVIOLET ENERGY CURABLE TAPE AND METHOD OF MAKING A SEMICONDUCTOR CHIP USING THE TAPE
27
Patent #:
Issue Dt:
09/21/2004
Application #:
10717385
Filing Dt:
11/19/2003
Publication #:
Pub Dt:
05/27/2004
Title:
ENHANCEMENT OF MAGNETIZATION SWITCHING SPEED IN SOFT FERROMAGNETIC FILMS THROUGH CONTROL OF EDGE STRESS ANISOTROPY
28
Patent #:
Issue Dt:
08/15/2006
Application #:
10717737
Filing Dt:
11/20/2003
Publication #:
Pub Dt:
05/26/2005
Title:
DUAL GATE FINFET
29
Patent #:
Issue Dt:
07/31/2007
Application #:
10719113
Filing Dt:
11/20/2003
Publication #:
Pub Dt:
05/26/2005
Title:
METHOD, SYSTEM, AND PROGRAM FOR TRANSMITTING INPUT/OUTPUT REQUESTS FROM A PRIMARY CONTROLLER TO A SECONDARY CONTROLLER
30
Patent #:
Issue Dt:
11/27/2007
Application #:
10719180
Filing Dt:
11/20/2003
Publication #:
Pub Dt:
05/26/2005
Title:
HOST-INITIATED DATA RECONSTRUCTION FOR IMPROVED RAID READ OPERATIONS
31
Patent #:
Issue Dt:
08/14/2007
Application #:
10720166
Filing Dt:
11/25/2003
Publication #:
Pub Dt:
06/10/2004
Title:
DOUBLE GATE SEMICONDUCTOR DEVICE HAVING A METAL GATE
32
Patent #:
Issue Dt:
09/19/2006
Application #:
10720464
Filing Dt:
11/24/2003
Publication #:
Pub Dt:
05/26/2005
Title:
MULTIPLE VOLTAGE INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR
33
Patent #:
Issue Dt:
10/10/2006
Application #:
10720466
Filing Dt:
11/24/2003
Publication #:
Pub Dt:
05/26/2005
Title:
SINGLE SUPPLY LEVEL CONVERTER
34
Patent #:
Issue Dt:
11/13/2007
Application #:
10720974
Filing Dt:
11/24/2003
Publication #:
Pub Dt:
05/26/2005
Title:
METHOD FOR DETERMINING JITTER OF A SIGNAL IN A SERIAL LINK AND HIGH SPEED SERIAL LINK
35
Patent #:
Issue Dt:
05/08/2007
Application #:
10722226
Filing Dt:
11/25/2003
Publication #:
Pub Dt:
05/26/2005
Title:
HIGH PERFORMANCE CHIP CARRIER SUBSTRATE
36
Patent #:
Issue Dt:
03/21/2006
Application #:
10722704
Filing Dt:
11/25/2003
Publication #:
Pub Dt:
05/26/2005
Title:
ROUGHENED BONDING PAD AND BONDING WIRE SURFACES FOR LOW PRESSURE WIRE BONDING
37
Patent #:
Issue Dt:
01/30/2007
Application #:
10723751
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
06/16/2005
Title:
DIAGNOSING FAULTS AND ERRORS FROM A DATA REPOSITORY USING DIRECTED GRAPHS
38
Patent #:
Issue Dt:
07/11/2006
Application #:
10725849
Filing Dt:
12/02/2003
Publication #:
Pub Dt:
06/02/2005
Title:
ULTRA-THIN SI CHANNEL MOSFET USING A SELF-ALIGNED OXYGEN IMPLANT AND DAMASCENE TECHNIQUE
39
Patent #:
Issue Dt:
06/27/2006
Application #:
10726140
Filing Dt:
12/02/2003
Publication #:
Pub Dt:
06/02/2005
Title:
BUILDING METAL PILLARS IN A CHIP FOR STRUCTURE SUPPORT
40
Patent #:
Issue Dt:
11/22/2005
Application #:
10726619
Filing Dt:
12/04/2003
Title:
DAMASCENE GATE SEMICONDUCTOR PROCESSING WITH LOCAL THINNING OF CHANNEL REGION
41
Patent #:
Issue Dt:
11/29/2011
Application #:
10726902
Filing Dt:
12/03/2003
Publication #:
Pub Dt:
06/09/2005
Title:
TRANSITIONING FROM INSTRUCTION CACHE TO TRACE CACHE ON LABEL BOUNDARIES
42
Patent #:
Issue Dt:
05/16/2006
Application #:
10728750
Filing Dt:
12/08/2003
Publication #:
Pub Dt:
06/09/2005
Title:
DYNAMIC THRESHOLD VOLTAGE MOSFET ON SOI
43
Patent #:
Issue Dt:
02/27/2007
Application #:
10728909
Filing Dt:
12/08/2003
Title:
METHODS FOR FORMING SMALL CONTACTS
44
Patent #:
Issue Dt:
10/02/2007
Application #:
10729254
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
06/09/2005
Title:
SILICON CHIP CARRIER WITH CONDUCTIVE THROUGH-VIAS AND METHOD FOR FABRICATING SAME
45
Patent #:
Issue Dt:
10/26/2010
Application #:
10729452
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
06/09/2005
Title:
METHOD FOR PATTERNING A LOW ACTIVATION ENERGY PHOTORESIST
46
Patent #:
Issue Dt:
11/20/2007
Application #:
10729453
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
06/09/2005
Title:
PRECURSORS TO FLUOROALKANOL-CONTAINING OLEFIN MONOMERS AND ASSOCIATED METHODS OF SYNTHESIS AND USE
47
Patent #:
Issue Dt:
12/05/2006
Application #:
10729479
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
06/09/2005
Title:
SEMICONDUCTOR SUBSTRATE AND PROCESSES THEREFOR
48
Patent #:
Issue Dt:
10/23/2007
Application #:
10729751
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
06/09/2005
Title:
DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY
49
Patent #:
Issue Dt:
09/13/2011
Application #:
10730800
Filing Dt:
12/09/2003
Title:
APPARATUS AND METHOD FOR MULTIPLE PASS EXTENDED PRECISION FLOATING POINT MULTIPLICATION
50
Patent #:
Issue Dt:
07/04/2006
Application #:
10730892
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
06/16/2005
Title:
FIELD EFFECT TRANSISTOR WITH ETCHED-BACK GATE DIELECTRIC
51
Patent #:
Issue Dt:
11/04/2008
Application #:
10731520
Filing Dt:
12/09/2003
Publication #:
Pub Dt:
06/09/2005
Title:
APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING VIAS AS RADIATING ELEMENTS FORMED IN A SUBSTRATE
52
Patent #:
Issue Dt:
06/17/2008
Application #:
10732322
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
06/16/2005
Title:
SECTIONAL FIELD EFFECT DEVICES
53
Patent #:
Issue Dt:
05/17/2011
Application #:
10732579
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
06/16/2005
Title:
INTEGRATED CIRCUIT WITH UPSTANDING STYLUS
54
Patent #:
Issue Dt:
04/19/2011
Application #:
10732580
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
06/16/2005
Title:
PHASE CHANGE TIP STORAGE CELL
55
Patent #:
Issue Dt:
09/18/2007
Application #:
10732958
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
06/16/2005
Title:
WRAP-AROUND GATE FIELD EFFECT TRANSISTOR
56
Patent #:
Issue Dt:
04/03/2007
Application #:
10733378
Filing Dt:
12/12/2003
Publication #:
Pub Dt:
06/16/2005
Title:
STRAINED FINFETS AND METHOD OF MANUFACTURE
57
Patent #:
Issue Dt:
05/20/2008
Application #:
10733974
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
06/16/2005
Title:
METHODS AND STRUCTURES FOR PROMOTING STABLE SYNTHESIS OF CARBON NANOTUBES
58
Patent #:
Issue Dt:
05/21/2013
Application #:
10735061
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
06/16/2005
Title:
GATED DIODE MEMORY CELLS
59
Patent #:
Issue Dt:
04/29/2008
Application #:
10735845
Filing Dt:
12/16/2003
Publication #:
Pub Dt:
06/16/2005
Title:
INTERCONNECT STRUCTURES AND METHODS OF MAKING THEREOF
60
Patent #:
Issue Dt:
06/29/2010
Application #:
10736424
Filing Dt:
12/15/2003
Publication #:
Pub Dt:
06/16/2005
Title:
TESTING OF TRANSIMPEDANCE AMPLIFIERS
61
Patent #:
Issue Dt:
10/24/2006
Application #:
10737626
Filing Dt:
12/16/2003
Publication #:
Pub Dt:
06/16/2005
Title:
METHOD FOR OPTIMIZING A NUMBER OF KERNELS USED IN A SUM OF COHERENT SOURCES FOR OPTICAL PROXIMITY CORRECTION IN AN OPTICAL MICROLITHOGRAPHY PROCESS
62
Patent #:
Issue Dt:
06/06/2006
Application #:
10738064
Filing Dt:
12/17/2003
Publication #:
Pub Dt:
06/23/2005
Title:
SILICON CARRIER FOR OPTICAL INTERCONNECT MODULES
63
Patent #:
Issue Dt:
09/13/2005
Application #:
10738529
Filing Dt:
12/17/2003
Title:
SEMICONDUCTOR ON INSULATOR MOSFET HAVING STRAINED SILICON CHANNEL
64
Patent #:
Issue Dt:
10/24/2006
Application #:
10738711
Filing Dt:
12/17/2003
Publication #:
Pub Dt:
06/23/2005
Title:
METHOD AND APPARATUS FOR GENERATING STEINER TREES USING SIMULTANEOUS BLOCKAGE AVOIDANCE, DELAY OPTIMIZATION AND DESIGN DENSITY MANAGEMENT
65
Patent #:
Issue Dt:
11/14/2006
Application #:
10738714
Filing Dt:
12/17/2003
Publication #:
Pub Dt:
06/23/2005
Title:
METHOD AND APPARATUS FOR PERFORMING DENSITY-BIASED BUFFER INSERTION IN AN INTEGRATED CIRCUIT DESIGN
66
Patent #:
Issue Dt:
07/04/2006
Application #:
10738716
Filing Dt:
12/17/2003
Title:
STRAINED SILICON PMOS HAVING SILICON GERMANIUM SOURCE/DRAIN EXTENSIONS AND METHOD FOR ITS FABRICATION
67
Patent #:
Issue Dt:
07/01/2008
Application #:
10739966
Filing Dt:
12/18/2003
Publication #:
Pub Dt:
06/23/2005
Title:
DATA STORAGE SYSTEMS
68
Patent #:
Issue Dt:
01/27/2009
Application #:
10740546
Filing Dt:
12/22/2003
Title:
METHOD FOR REDUCING FLOATING BODY EFFECTS IN SOI SEMICONDUCTOR DEVICE WITHOUT DEGRADING MOBILITY
69
Patent #:
Issue Dt:
10/17/2006
Application #:
10741203
Filing Dt:
12/19/2003
Publication #:
Pub Dt:
06/23/2005
Title:
DEEP TRENCH CAPACITOR WITH BURIED PLATE ELECTRODE AND ISOLATION COLLAR
70
Patent #:
Issue Dt:
06/14/2011
Application #:
10745044
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
11/04/2004
Title:
METHOD OF PROVIDING CONTEXT SPECIFIC RECIPES IN A SEMICONDUCTOR FACILITY BY DEFINING PRODUCT CATEGORIES
71
Patent #:
Issue Dt:
09/04/2012
Application #:
10745822
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
09/30/2004
Title:
LOCATING A TESTABLE OBJECT IN A FUNCTIONAL TESTING TOOL
72
Patent #:
Issue Dt:
04/04/2006
Application #:
10747680
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
07/07/2005
Title:
METHOD FOR FORMING RECTANGULAR-SHAPED SPACERS FOR SEMICONDUCTOR DEVICES
73
Patent #:
Issue Dt:
01/30/2007
Application #:
10747722
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
12/16/2004
Title:
METHOD OF REDUCING WAFER CONTAMINATION BY REMOVING UNDER-METAL LAYERS AT THE WAFER EDGE
74
Patent #:
Issue Dt:
12/19/2006
Application #:
10747723
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD AND SYSTEM FOR CONTROLLING THE CHEMICAL MECHANICAL POLISHING BY USING A SENSOR SIGNAL OF A PAD CONDITIONER
75
Patent #:
Issue Dt:
06/26/2007
Application #:
10749607
Filing Dt:
12/31/2003
Publication #:
Pub Dt:
07/07/2005
Title:
METHOD AND SYSTEM FOR SELECTIVE COMPILATION OF INSTRUMENTATION ENTITIES INTO A SIMULATION MODEL OF A DIGITAL DESIGN
76
Patent #:
Issue Dt:
12/06/2005
Application #:
10750697
Filing Dt:
01/02/2004
Publication #:
Pub Dt:
07/22/2004
Title:
ENHANCED T-GATE STRUCTURE FOR MODULATION DOPED FIELD EFFECT TRANSISTORS
77
Patent #:
Issue Dt:
12/04/2012
Application #:
10751714
Filing Dt:
01/05/2004
Publication #:
Pub Dt:
07/07/2005
Title:
AMPLIFIERS USING GATED DIODES
78
Patent #:
Issue Dt:
01/20/2009
Application #:
10751831
Filing Dt:
01/05/2004
Publication #:
Pub Dt:
12/02/2004
Title:
STI STRESS MODIFICATION BY NITROGEN PLASMA TREATMENT FOR IMPROVING PERFORMANCE IN SMALL WIDTH DEVICES
79
Patent #:
Issue Dt:
04/27/2010
Application #:
10751916
Filing Dt:
01/07/2004
Publication #:
Pub Dt:
07/07/2005
Title:
HIGH PERFORMANCE STRAINED SILICON FINFETS DEVICE AND METHOD FOR FORMING SAME
80
Patent #:
Issue Dt:
04/01/2008
Application #:
10753241
Filing Dt:
01/08/2004
Publication #:
Pub Dt:
07/22/2004
Title:
INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION OR NITRIDIZATION
81
Patent #:
Issue Dt:
06/20/2006
Application #:
10753989
Filing Dt:
01/08/2004
Publication #:
Pub Dt:
07/14/2005
Title:
POSITIVE PHOTORESIST COMPOSITION WITH A POLYMER INCLUDING A FLUOROSULFONAMIDE GROUP AND PROCESS FOR ITS USE
82
Patent #:
Issue Dt:
10/25/2005
Application #:
10754320
Filing Dt:
01/08/2004
Publication #:
Pub Dt:
07/14/2005
Title:
DISCRIMINATIVE SOI WITH OXIDE HOLES UNDERNEATH DC SOURCE/DRAIN
83
Patent #:
Issue Dt:
03/16/2010
Application #:
10754515
Filing Dt:
01/12/2004
Title:
FINFET DEVICE WITH MULTIPLE FIN STRUCTURES
84
Patent #:
Issue Dt:
10/07/2008
Application #:
10755344
Filing Dt:
01/13/2004
Title:
FINFET DEVICE WITH MULTIPLE CHANNELS
85
Patent #:
Issue Dt:
12/09/2008
Application #:
10755602
Filing Dt:
01/12/2004
Publication #:
Pub Dt:
07/14/2005
Title:
SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION
86
Patent #:
Issue Dt:
05/13/2008
Application #:
10755692
Filing Dt:
01/12/2004
Title:
CONTROLLING WRITES TO NON-RENAMED REGISTER SPACE IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR
87
Patent #:
Issue Dt:
07/31/2007
Application #:
10755734
Filing Dt:
01/12/2004
Title:
CACHE MEMORY SUBSYSTEM INCLUDING A FIXED LATENCY R/W PIPELINE
88
Patent #:
Issue Dt:
05/01/2007
Application #:
10755742
Filing Dt:
01/12/2004
Title:
METHOD AND PROCESSOR INCLUDING LOGIC FOR STORING TRACES WITHIN A TRACE CACHE
89
Patent #:
Issue Dt:
07/03/2007
Application #:
10755746
Filing Dt:
01/12/2004
Publication #:
Pub Dt:
05/05/2005
Title:
SILICON BUFFERED SHALLOW TRENCH ISOLATION
90
Patent #:
Issue Dt:
11/21/2006
Application #:
10755763
Filing Dt:
01/12/2004
Publication #:
Pub Dt:
07/14/2005
Title:
Method of fabricating an integrated circuit channel region
91
Patent #:
Issue Dt:
06/27/2006
Application #:
10755816
Filing Dt:
01/12/2004
Publication #:
Pub Dt:
04/21/2005
Title:
METHOD AND APPARATUS FOR THERMO-OPTIC MODULATION OF OPTICAL SIGNALS
92
Patent #:
Issue Dt:
04/22/2008
Application #:
10755875
Filing Dt:
01/13/2004
Publication #:
Pub Dt:
07/14/2005
Title:
REAL-TIME CONFIGURABLE MASKING
93
Patent #:
Issue Dt:
11/22/2005
Application #:
10757846
Filing Dt:
01/15/2004
Publication #:
Pub Dt:
07/21/2005
Title:
CONCURRENT REFRESH MODE WITH DISTRIBUTED ROW ADDRESS COUNTERS IN AN EMBEDDED DRAM
94
Patent #:
Issue Dt:
04/18/2006
Application #:
10758724
Filing Dt:
01/16/2004
Publication #:
Pub Dt:
07/21/2005
Title:
LOW K AND ULTRA LOW K SICOH DIELECTRIC FILMS AND METHODS TO FORM THE SAME
95
Patent #:
Issue Dt:
12/28/2004
Application #:
10759170
Filing Dt:
01/20/2004
Publication #:
Pub Dt:
07/29/2004
Title:
PROTECTION OF LOW-K ILD DURING DAMASCENE PROCESSING WITH THIN LINER
96
Patent #:
Issue Dt:
07/04/2006
Application #:
10761009
Filing Dt:
01/20/2004
Title:
METHOD FOR FORMING A THIN, HIGH QUALITY BUFFER LAYER IN A FIELD EFFECT TRANSISTOR AND RELATED STRUCTURE
97
Patent #:
Issue Dt:
07/31/2007
Application #:
10761374
Filing Dt:
01/22/2004
Title:
REVERSED T-SHAPED FINFET
98
Patent #:
Issue Dt:
03/13/2007
Application #:
10763308
Filing Dt:
01/23/2004
Publication #:
Pub Dt:
09/30/2004
Title:
CMOS DEVICE INTEGRATION FOR LOW EXTERNAL RESISTANCE
99
Patent #:
Issue Dt:
02/07/2006
Application #:
10765042
Filing Dt:
01/28/2004
Publication #:
Pub Dt:
07/28/2005
Title:
HIGH PERFORMANCE INTERPOSER FOR A CHIP PACKAGE USING DEFORMABLE BUTTON CONTACTS
100
Patent #:
Issue Dt:
10/25/2005
Application #:
10766249
Filing Dt:
01/27/2004
Publication #:
Pub Dt:
09/30/2004
Title:
ELECTRONIC STRUCTURES WITH REDUCED CAPACITANCE
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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