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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
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Patent #:	7425353	Issue Dt:	09/16/2008	Application #:	10768347	Filing Dt:	01/29/2004
Publication #:	US20050170212	Pub Dt:	08/04/2005
Title:	ENHANCEMENT OF MAGNETIC MEDIA RECORDING PERFORMANCE USING ION IRRADIATION TO TAILOR EXCHANGE COUPLING

Patent #:	7068138	Issue Dt:	06/27/2006	Application #:	10768773	Filing Dt:	01/29/2004
Publication #:	US20050167780	Pub Dt:	08/04/2005
Title:	HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR

Patent #:	8217450	Issue Dt:	07/10/2012	Application #:	10770011	Filing Dt:	02/03/2004
Title:	DOUBLE-GATE SEMICONDUCTOR DEVICE WITH GATE CONTACTS FORMED ADJACENT SIDEWALLS OF A FIN

Patent #:	6855982	Issue Dt:	02/15/2005	Application #:	10770163	Filing Dt:	02/02/2004
Title:	SELF ALIGNED DOUBLE GATE TRANSISTOR HAVING A STRAINED CHANNEL REGION AND PROCESS THEREFOR

Patent #:	7568134	Issue Dt:	07/28/2009	Application #:	10770170	Filing Dt:	02/02/2004
Title:	METHOD OF EXHAUSTIVELY TESTING AN EMBEDDED ROM USING GENERATED ATPG TEST PATTERNS

Patent #:	7473566	Issue Dt:	01/06/2009	Application #:	10770682	Filing Dt:	02/03/2004
Title:	METHOD AND APPARATUS FOR CONTROLLING A FILM FORMATION PROCESS WITH MULTIPLE OBJECTIVES

Patent #:	7064067	Issue Dt:	06/20/2006	Application #:	10770905	Filing Dt:	02/02/2004
Title:	REDUCTION OF LATERAL SILICIDE GROWTH IN INTEGRATED CIRCUIT TECHNOLOGY

Patent #:	7512787	Issue Dt:	03/31/2009	Application #:	10771019	Filing Dt:	02/03/2004
Title:	RECEIVE IPSEC IN-LINE PROCESSING OF MUTABLE FIELDS FOR AH ALGORITHM

Patent #:	6856031	Issue Dt:	02/15/2005	Application #:	10771824	Filing Dt:	02/03/2004
Title:	SRAM CELL WITH WELL CONTACTS AND P+ DIFFUSION CROSSING TO GROUND OR N+ DIFFUSION CROSSING TO VDD

Patent #:	6991890	Issue Dt:	01/31/2006	Application #:	10773930	Filing Dt:	02/06/2004
Publication #:	US20050175928	Pub Dt:	08/11/2005
Title:	NEGATIVE PHOTORESIST COMPOSITION INVOLVING NON-CROSSLINKING CHEMISTRY

Patent #:	7422828	Issue Dt:	09/09/2008	Application #:	10774099	Filing Dt:	02/06/2004
Title:	MASK CD MEASUREMENT MONITOR OUTSIDE OF THE PELLICLE AREA

Patent #:	7064413	Issue Dt:	06/20/2006	Application #:	10774773	Filing Dt:	02/09/2004
Publication #:	US20040159910	Pub Dt:	08/19/2004
Title:	FIN-TYPE RESISTORS

Patent #:	7244980	Issue Dt:	07/17/2007	Application #:	10774827	Filing Dt:	02/09/2004
Publication #:	US20050176197	Pub Dt:	08/11/2005
Title:	LINE MASK DEFINED ACTIVE AREAS FOR 8F2 DRAM CELLS WITH FOLDED BIT LINES AND DEEP TRENCH PATTERNS

Patent #:	7227230	Issue Dt:	06/05/2007	Application #:	10775440	Filing Dt:	02/10/2004
Publication #:	US20040171201	Pub Dt:	09/02/2004
Title:	LOW K-GATE SPACERS BY FLUORINE IMPLANTATION

Patent #:	7183576	Issue Dt:	02/27/2007	Application #:	10775514	Filing Dt:	02/10/2004
Publication #:	US20040161875	Pub Dt:	08/19/2004
Title:	EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD

Patent #:	7212698	Issue Dt:	05/01/2007	Application #:	10775854	Filing Dt:	02/10/2004
Publication #:	US20050176161	Pub Dt:	08/11/2005
Title:	CIRCUIT BOARD INTEGRATED OPTICAL COUPLING ELEMENTS

Patent #:	7269817	Issue Dt:	09/11/2007	Application #:	10776901	Filing Dt:	02/10/2004
Publication #:	US20050177810	Pub Dt:	08/11/2005
Title:	LITHOGRAPHIC PROCESS WINDOW OPTIMIZATION UNDER COMPLEX CONSTRAINTS ON EDGE PLACEMENT

Patent #:	7829883	Issue Dt:	11/09/2010	Application #:	10777576	Filing Dt:	02/12/2004
Publication #:	US20050179029	Pub Dt:	08/18/2005
Title:	VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS AND ARRAYS

Patent #:	7252858	Issue Dt:	08/07/2007	Application #:	10780341	Filing Dt:	02/17/2004
Publication #:	US20040161372	Pub Dt:	08/19/2004
Title:	SYSTEM AND METHOD FOR ABATING THE SIMULTANEOUS FLOW OF SILANE AND ARSINE

Patent #:	7101741	Issue Dt:	09/05/2006	Application #:	10780393	Filing Dt:	02/17/2004
Publication #:	US20040161898	Pub Dt:	08/19/2004
Title:	DUAL DOUBLE GATE TRANSISTOR AND METHOD FOR FORMING

Patent #:	7088003	Issue Dt:	08/08/2006	Application #:	10780554	Filing Dt:	02/19/2004
Publication #:	US20050184397	Pub Dt:	08/25/2005
Title:	STRUCTURES AND METHODS FOR INTERGRATION OF ULTRALOW-K DIELECTRICS WITH IMPROVED RELIABILITY

Patent #:	7321884	Issue Dt:	01/22/2008	Application #:	10782811	Filing Dt:	02/23/2004
Publication #:	US20050184284	Pub Dt:	08/25/2005
Title:	METHOD AND STRUCTURE TO ISOLATE A QUBIT FROM THE ENVIRONMENT

Patent #:	7138697	Issue Dt:	11/21/2006	Application #:	10785894	Filing Dt:	02/24/2004
Publication #:	US20050184354	Pub Dt:	08/25/2005
Title:	STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE GE-ON-INSULATOR PHOTODETECTOR

Patent #:	7375410	Issue Dt:	05/20/2008	Application #:	10787002	Filing Dt:	02/25/2004
Publication #:	US20050184360	Pub Dt:	08/25/2005
Title:	ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF

Patent #:	7084476	Issue Dt:	08/01/2006	Application #:	10787488	Filing Dt:	02/26/2004
Publication #:	US20050189604	Pub Dt:	09/01/2005
Title:	INTEGRATED CIRCUIT LOGIC WITH SELF COMPENSATING BLOCK DELAYS

Patent #:	7135773	Issue Dt:	11/14/2006	Application #:	10787640	Filing Dt:	02/26/2004
Publication #:	US20050189655	Pub Dt:	09/01/2005
Title:	INTEGRATED CIRCUIT CHIP UTILIZING CARBON NANOTUBE COMPOSITE INTERCONNECTION VIAS

Patent #:	7108797	Issue Dt:	09/19/2006	Application #:	10787738	Filing Dt:	02/25/2004
Publication #:	US20040251232	Pub Dt:	12/16/2004
Title:	METHOD OF FABRICATING A SHIFTABLE MAGNETIC SHIFT REGISTER

Patent #:	7122455	Issue Dt:	10/17/2006	Application #:	10790567	Filing Dt:	03/01/2004
Title:	PATTERNING WITH RIGID ORGANIC UNDER-LAYER

Patent #:	7494872	Issue Dt:	02/24/2009	Application #:	10790852	Filing Dt:	03/02/2004
Publication #:	US20050023611	Pub Dt:	02/03/2005
Title:	FIELD EFFECT TRANSISTOR HAVING A DOPED GATE ELECTRODE WITH REDUCED GATE DEPLETION AND METHOD OF FORMING THE TRANSISTOR

Patent #:	7023059	Issue Dt:	04/04/2006	Application #:	10791094	Filing Dt:	03/01/2004
Title:	TRENCHES TO REDUCE LATERAL SILICIDE GROWTH IN INTEGRATED CIRCUIT TECHNOLOGY

Patent #:	7477713	Issue Dt:	01/13/2009	Application #:	10791175	Filing Dt:	03/02/2004
Publication #:	US20050195863	Pub Dt:	09/08/2005
Title:	METHOD FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN HIGH SPEED SERIAL LINKS

Patent #:	6977718	Issue Dt:	12/20/2005	Application #:	10791263	Filing Dt:	03/02/2004
Title:	LITHOGRAPHY METHOD AND SYSTEM WITH ADJUSTABLE REFLECTOR

Patent #:	7091106	Issue Dt:	08/15/2006	Application #:	10791759	Filing Dt:	03/04/2004
Publication #:	US20050196928	Pub Dt:	09/08/2005
Title:	METHOD OF REDUCING STI DIVOT FORMATION DURING SEMICONDUCTOR DEVICE FABRICATION

Patent #:	7071564	Issue Dt:	07/04/2006	Application #:	10791904	Filing Dt:	03/04/2004
Title:	COMPOSITE TANTALUM CAPPED INLAID COPPER WITH REDUCED ELECTROMIGRATION AND REDUCED STRESS MIGRATION

Patent #:	7948902	Issue Dt:	05/24/2011	Application #:	10791914	Filing Dt:	03/03/2004
Title:	METHOD OF GENERATING PACKETS WITHOUT REPETITION IN VERIFICATION OF A DEVICE

Patent #:	6876037	Issue Dt:	04/05/2005	Application #:	10796731	Filing Dt:	03/09/2004
Publication #:	US20040169227	Pub Dt:	09/02/2004
Title:	DOPING METHODS FOR FULLY-DEPLETED SOI STRUCTURES, AND DEVICE COMPRISING THE RESULTING DOPED REGIONS

Patent #:	6915452	Issue Dt:	07/05/2005	Application #:	10797878	Filing Dt:	03/10/2004
Publication #:	US20040205401	Pub Dt:	10/14/2004
Title:	METHOD, SYSTEM AND PROGRAM PRODUCTS FOR OPERATIONALLY MIGRATING A CLUSTER THROUGH EMULATION

Patent #:	6989308	Issue Dt:	01/24/2006	Application #:	10798907	Filing Dt:	03/11/2004
Publication #:	US20050202607	Pub Dt:	09/15/2005
Title:	METHOD OF FORMING FINFET GATES WITHOUT LONG ETCHES

Patent #:	7435074	Issue Dt:	10/14/2008	Application #:	10799282	Filing Dt:	03/13/2004
Publication #:	US20050202350	Pub Dt:	09/15/2005
Title:	METHOD FOR FABRICATING DUAL DAMASCENE STRUCTURES USING PHOTO-IMPRINT LITHOGRAPHY, METHODS FOR FABRICATING IMPRINT LITHOGRAPHY MOLDS FOR DUAL DAMASCENE STRUCTURES, MATERIALS FOR IMPRINTABLE DIELECTRICS AND EQUIPMENT FOR PHOTO-IMPRINT LITHOGRAPHY USED IN DUAL DAMASCE

Patent #:	7023057	Issue Dt:	04/04/2006	Application #:	10799380	Filing Dt:	03/12/2004
Publication #:	US20050093077	Pub Dt:	05/05/2005
Title:	CMOS ON HYBRID SUBSTRATE WITH DIFFERENT CRYSTAL ORIENTATIONS USING SILICON-TO-SILICON DIRECT WAFER BONDING

Patent #:	7094651	Issue Dt:	08/22/2006	Application #:	10801766	Filing Dt:	03/16/2004
Publication #:	US20050009225	Pub Dt:	01/13/2005
Title:	HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS

Patent #:	7115498	Issue Dt:	10/03/2006	Application #:	10803852	Filing Dt:	03/18/2004
Title:	METHOD OF ULTRA-LOW ENERGY ION IMPLANTATION TO FORM ALLOY LAYERS IN COPPER

Patent #:	7084758	Issue Dt:	08/01/2006	Application #:	10804308	Filing Dt:	03/19/2004
Title:	LOCATION-BASED REMINDERS

Patent #:	7030495	Issue Dt:	04/18/2006	Application #:	10804553	Filing Dt:	03/19/2004
Publication #:	US20050208752	Pub Dt:	09/22/2005
Title:	METHOD FOR FABRICATING A SELF-ALIGNED NANOCOLUMNAR AIRBRIDGE AND STRUCTURE PRODUCED THEREBY

Patent #:	7033888	Issue Dt:	04/25/2006	Application #:	10806117	Filing Dt:	03/23/2004
Publication #:	US20040175910	Pub Dt:	09/09/2004
Title:	ENGINEERED METAL GATE ELECTRODE

Patent #:	7676814	Issue Dt:	03/09/2010	Application #:	10809229	Filing Dt:	03/25/2004
Publication #:	US20050213603	Pub Dt:	09/29/2005
Title:	FOUR LAYER ARCHITECTURE FOR NETWORK DEVICE DRIVERS

Patent #:	6952052	Issue Dt:	10/04/2005	Application #:	10811860	Filing Dt:	03/30/2004
Publication #:	US20050224979	Pub Dt:	10/13/2005
Title:	CU INTERCONNECTS WITH COMPOSITE BARRIER LAYERS FOR WAFER-TO-WAFER UNIFORMITY

Patent #:	7288177	Issue Dt:	10/30/2007	Application #:	10813351	Filing Dt:	03/30/2004
Publication #:	US20050218002	Pub Dt:	10/06/2005
Title:	SELECTIVE SHIELD/MATERIAL FLOW MECHANISM

Patent #:	7231501	Issue Dt:	06/12/2007	Application #:	10813519	Filing Dt:	03/30/2004
Publication #:	US20050240833	Pub Dt:	10/27/2005
Title:	METHOD FOR A VOIDING ALIASED TOKENS DURING ABNORMAL COMMUNICATIONS

Patent #:	8450806	Issue Dt:	05/28/2013	Application #:	10814482	Filing Dt:	03/31/2004
Publication #:	US20050227498	Pub Dt:	10/13/2005
Title:	METHOD FOR FABRICATING STRAINED SILICON-ON-INSULATOR STRUCTURES AND STRAINED SILICON-ON INSULATOR STRUCTURES FORMED THEREBY

Patent #:	7353155	Issue Dt:	04/01/2008	Application #:	10816150	Filing Dt:	04/01/2004
Publication #:	US20050222831	Pub Dt:	10/06/2005
Title:	SYSTEM AND METHOD FOR AUTOMATIC SELECTION OF TRANSMISSION LINE MACROMODELS

Patent #:	7826614	Issue Dt:	11/02/2010	Application #:	10816661	Filing Dt:	04/02/2004
Title:	METHODS AND APPARATUS FOR PASSING INITIALIZATION VECTOR INFORMATION FROM SOFTWARE TO HARDWARE TO PERFORM IPSEC ENCRYPTION OPERATION

Patent #:	7269804	Issue Dt:	09/11/2007	Application #:	10816764	Filing Dt:	04/02/2004
Publication #:	US20050229125	Pub Dt:	10/13/2005
Title:	SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES

Patent #:	7356108	Issue Dt:	04/08/2008	Application #:	10817811	Filing Dt:	04/06/2004
Title:	OFDM RECEIVER HAVING ADAPTIVE CHANNEL ESTIMATOR FOR CORRECTING CHANNEL FADING BASED ON ACCUMULATED PSEUDO POWER VALUES

Patent #:	7494885	Issue Dt:	02/24/2009	Application #:	10818155	Filing Dt:	04/05/2004
Title:	DISPOSABLE SPACER PROCESS FOR FIELD EFFECT TRANSISTOR FABRICATION

Patent #:	7400277	Issue Dt:	07/15/2008	Application #:	10818567	Filing Dt:	04/06/2004
Publication #:	US20050231401	Pub Dt:	10/20/2005
Title:	METHOD AND SYSTEM FOR THE COMPRESSION OF PROBABILITY TABLES

Patent #:	7005302	Issue Dt:	02/28/2006	Application #:	10819441	Filing Dt:	04/07/2004
Publication #:	US20050224879	Pub Dt:	10/13/2005
Title:	SEMICONDUCTOR ON INSULATOR SUBSTRATE AND DEVICES FORMED THEREFROM

Patent #:	7373466	Issue Dt:	05/13/2008	Application #:	10819451	Filing Dt:	04/07/2004
Title:	METHOD AND APPARATUS FOR FILTERING MEMORY WRITE SNOOP ACTIVITY IN A DISTRIBUTED SHARED MEMORY COMPUTER

Patent #:	7355384	Issue Dt:	04/08/2008	Application #:	10821044	Filing Dt:	04/08/2004
Publication #:	US20050228907	Pub Dt:	10/13/2005
Title:	APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MONITORING AND CONTROLLING A MICROCOMPUTER USING A SINGLE EXISTING PIN

Patent #:	7074686	Issue Dt:	07/11/2006	Application #:	10824289	Filing Dt:	04/14/2004
Publication #:	US20040192069	Pub Dt:	09/30/2004
Title:	METHOD OF CREATING HIGH-QUALITY RELAXED SIGE-ON-INSULATOR FOR STRAINED SI CMOS APPLICATIONS

Patent #:	7161344	Issue Dt:	01/09/2007	Application #:	10827230	Filing Dt:	04/20/2004
Publication #:	US20050231187	Pub Dt:	10/20/2005
Title:	METHOD AND STRUCTURE FOR VARIABLE PITCH MICROWAVE PROBE ASSEMBLY

Patent #:	7102232	Issue Dt:	09/05/2006	Application #:	10827693	Filing Dt:	04/19/2004
Publication #:	US20050230831	Pub Dt:	10/20/2005
Title:	STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTIRIC AND DIELECTRIC CAPPING LAYER

Patent #:	6921963	Issue Dt:	07/26/2005	Application #:	10830006	Filing Dt:	04/23/2004
Publication #:	US20040197975	Pub Dt:	10/07/2004
Title:	NARROW FIN FINFET

Patent #:	7084431	Issue Dt:	08/01/2006	Application #:	10832217	Filing Dt:	04/26/2004
Publication #:	US20040227154	Pub Dt:	11/18/2004
Title:	HIGH SPEED COMPOSITE P-CHANNEL SI/SIGE HETEROSTRUCTURE FOR FIELD EFFECT DEVICES

Patent #:	7752355	Issue Dt:	07/06/2010	Application #:	10832658	Filing Dt:	04/27/2004
Publication #:	US20050238038	Pub Dt:	10/27/2005
Title:	ASYNCHRONOUS PACKET BASED DUAL PORT LINK LIST HEADER AND DATA CREDIT MANAGEMENT STRUCTURE

Patent #:	7027130	Issue Dt:	04/11/2006	Application #:	10833651	Filing Dt:	04/28/2004
Publication #:	US20050243299	Pub Dt:	11/03/2005
Title:	DEVICE AND METHOD FOR DETERMINING AN ILLUMINATION INTENSITY PROFILE OF AN ILLUMINATOR FOR A LITHOGRAPHY SYSTEM

Patent #:	7807233	Issue Dt:	10/05/2010	Application #:	10835411	Filing Dt:	04/29/2004
Publication #:	US20050048222	Pub Dt:	03/03/2005
Title:	METHOD OF FORMING A TEOS CAP LAYER AT LOW TEMPERATURE AND REDUCED DEPOSITION RATE

Patent #:	7038231	Issue Dt:	05/02/2006	Application #:	10835814	Filing Dt:	04/30/2004
Publication #:	US20050242338	Pub Dt:	11/03/2005
Title:	NON-PLANARIZED, SELF-ALIGNED, NON-VOLATILE PHASE-CHANGE MEMORY ARRAY AND METHOD OF FORMATION

Patent #:	7231621	Issue Dt:	06/12/2007	Application #:	10837395	Filing Dt:	04/30/2004
Title:	SPEED VERIFICATION OF AN EMBEDDED PROCESSOR IN A PROGRAMMABLE LOGIC DEVICE

Patent #:	7449782	Issue Dt:	11/11/2008	Application #:	10838378	Filing Dt:	05/04/2004
Publication #:	US20050250301	Pub Dt:	11/10/2005
Title:	SELF-ALIGNED METAL TO FORM CONTACTS TO GE CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY

Patent #:	7246269	Issue Dt:	07/17/2007	Application #:	10839072	Filing Dt:	05/05/2004
Title:	EFFICIENT MEMORY CHECK ARCHITECTURE AND METHOD

Patent #:	7151020	Issue Dt:	12/19/2006	Application #:	10839437	Filing Dt:	05/04/2004
Title:	CONVERSION OF TRANSITION METAL TO SILICIDE THROUGH BACK END PROCESSING IN INTEGRATED CIRCUIT TECHNOLOGY

Patent #:	7263600	Issue Dt:	08/28/2007	Application #:	10839474	Filing Dt:	05/05/2004
Publication #:	US20050247774	Pub Dt:	11/10/2005
Title:	SYSTEM AND METHOD FOR VALIDATING A MEMORY FILE THAT LINKS SPECULATIVE RESULTS OF LOAD OPERATIONS TO REGISTER VALUES

Patent #:	7502474	Issue Dt:	03/10/2009	Application #:	10839872	Filing Dt:	05/06/2004
Publication #:	US20050256975	Pub Dt:	11/17/2005
Title:	NETWORK INTERFACE WITH SECURITY ASSOCIATION DATA PREFETCH FOR HIGH SPEED OFFLOADED SECURITY PROCESSING

Patent #:	6980038	Issue Dt:	12/27/2005	Application #:	10840561	Filing Dt:	05/06/2004
Publication #:	US20050248412	Pub Dt:	11/10/2005
Title:	CIRCUIT FOR COMPENSATING CHARGE LEAKAGE IN A LOW PASS FILTER CAPACITOR OF PLL SYSTEMS

Patent #:	7426704	Issue Dt:	09/16/2008	Application #:	10842085	Filing Dt:	05/10/2004
Publication #:	US20050251765	Pub Dt:	11/10/2005
Title:	DESIGN VERIFICATION OF HIGHLY OPTIMIZED SYNCHRONOUS PIPELINES VIA RANDOM SIMULATION DRIVEN BY CRITICAL RESOURCE SCHEDULING

Patent #:	7725905	Issue Dt:	05/25/2010	Application #:	10843255	Filing Dt:	05/10/2004
Title:	MEDIA ACCELERATOR INTERFACE API

Patent #:	7037824	Issue Dt:	05/02/2006	Application #:	10844533	Filing Dt:	05/13/2004
Publication #:	US20040207092	Pub Dt:	10/21/2004
Title:	COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER

Patent #:	7131104	Issue Dt:	10/31/2006	Application #:	10844794	Filing Dt:	05/13/2004
Publication #:	US20050257187	Pub Dt:	11/17/2005
Title:	FAST AND ACCURATE OPTICAL PROXIMITY CORRECTION ENGINE FOR INCORPORATING LONG RANGE FLARE EFFECTS

Patent #:	7504727	Issue Dt:	03/17/2009	Application #:	10845718	Filing Dt:	05/14/2004
Publication #:	US20050258542	Pub Dt:	11/24/2005
Title:	A SEMICONDUCTOR INTERCONNECT STRUCTURE UTILIZING A POROUS DIELECTRIC MATERIAL AS AN ETCH STOP LAYER BETWEEN ADJACENT NON-POROUS DIELECTRIC MATERIALS

Patent #:	7081680	Issue Dt:	07/25/2006	Application #:	10849459	Filing Dt:	05/19/2004
Publication #:	US20040234679	Pub Dt:	11/25/2004
Title:	SELF-ALIGNED CORROSION STOP FOR COPPER C4 AND WIREBOND

Patent #:	7557035	Issue Dt:	07/07/2009	Application #:	10849847	Filing Dt:	05/21/2004
Title:	METHOD OF FORMING SEMICONDUCTOR DEVICES BY MICROWAVE CURING OF LOW-K DIELECTRIC FILMS

Patent #:	7135391	Issue Dt:	11/14/2006	Application #:	10851821	Filing Dt:	05/21/2004
Publication #:	US20050260832	Pub Dt:	11/24/2005
Title:	POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES

Patent #:	7115996	Issue Dt:	10/03/2006	Application #:	10852142	Filing Dt:	05/25/2004
Publication #:	US20040212089	Pub Dt:	10/28/2004
Title:	METHOD TO SELECTIVELY CAP INTERCONNECTS WITH INDIUM OR TIN BRONZES AND/OR OXIDES THEREOF AND THE INTERCONNECT SO CAPPED

Patent #:	7370296	Issue Dt:	05/06/2008	Application #:	10853041	Filing Dt:	05/25/2004
Publication #:	US20050278702	Pub Dt:	12/15/2005
Title:	MODELING LANGUAGE AND METHOD FOR ADDRESS TRANSLATION DESIGN MECHANISMS IN TEST GENERATION

Patent #:	7343534	Issue Dt:	03/11/2008	Application #:	10855047	Filing Dt:	05/27/2004
Publication #:	US20050268187	Pub Dt:	12/01/2005
Title:	METHOD FOR DEFERRED DATA COLLECTION IN A CLOCK RUNNING SYSTEM

Patent #:	7348253	Issue Dt:	03/25/2008	Application #:	10855915	Filing Dt:	05/27/2004
Publication #:	US20040259334	Pub Dt:	12/23/2004
Title:	HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT

Patent #:	6906401	Issue Dt:	06/14/2005	Application #:	10856503	Filing Dt:	05/28/2004
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Title:	METHOD TO FABRICATE HIGH-PERFORMANCE NPN TRANSISTORS IN A BICMOS PROCESS

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Title:	IN-SITU DEFECT MONITOR AND CONTROL SYSTEM FOR IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY

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Title:	METHOD FOR OPTIMIZING LOOP CONTROL OF MICROCODED INSTRUCTIONS

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Title:	OPTICAL PROXIMITY CORRECTION (OPC) TECHNIQUE TO COMPENSATE FOR FLARE

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Title:	METHODS AND FIXTURE FOR COUPLING A LID TO A SUPPORT SUBSTRATE

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Title:	COMPLEMENTARY TWO TRANSISTOR ROM CELL

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Title:	DIFFUSED EXTRINSIC BASE AND METHOD FOR FABRICATION

100

Patent #:	7125785	Issue Dt:	10/24/2006	Application #:	10865920	Filing Dt:	06/14/2004
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Title:	MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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