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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 30 of 146
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1
Patent #:
7240322
Issue Dt:
07/03/2007
Application #:
10907494
Filing Dt:
04/04/2005
Publication #:
US20060225023
Pub Dt:
10/05/2006
Title:
METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
2
Patent #:
7290226
Issue Dt:
10/30/2007
Application #:
10907496
Filing Dt:
04/04/2005
Publication #:
US20060225005
Pub Dt:
10/05/2006
Title:
VIA REDUNDANCY BASED ON SUBNET TIMING INFORMATION, TARGET VIA DISTANT ALONG PATH FROM SOURCE AND/OR TARGET VIA NET/SUBNET CHARACTERISTIC
3
Patent #:
7259625
Issue Dt:
08/21/2007
Application #:
10907537
Filing Dt:
04/05/2005
Publication #:
US20060220737
Pub Dt:
10/05/2006
Title:
HIGH Q MONOLITHIC INDUCTORS FOR USE IN DIFFERENTIAL CIRCUITS
4
Patent #:
7205591
Issue Dt:
04/17/2007
Application #:
10907570
Filing Dt:
04/06/2005
Publication #:
US20060226456
Pub Dt:
10/12/2006
Title:
PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF
5
Patent #:
7451070
Issue Dt:
11/11/2008
Application #:
10907628
Filing Dt:
04/08/2005
Publication #:
US20060229858
Pub Dt:
10/12/2006
Title:
OPTIMAL BUS OPERATION PERFORMANCE IN A LOGIC SIMULATION ENVIRONMENT
6
Patent #:
7485910
Issue Dt:
02/03/2009
Application #:
10907630
Filing Dt:
04/08/2005
Publication #:
US20060226481
Pub Dt:
10/12/2006
Title:
SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/EDRAM INTEGRATION: METHOD AND STRUCTURE
7
Patent #:
7816728
Issue Dt:
10/19/2010
Application #:
10907686
Filing Dt:
04/12/2005
Publication #:
US20060226474
Pub Dt:
10/12/2006
Title:
STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS
8
Patent #:
7091551
Issue Dt:
08/15/2006
Application #:
10907712
Filing Dt:
04/13/2005
Title:
FOUR-BIT FINFET NVRAM MEMORY DEVICE
9
Patent #:
7166913
Issue Dt:
01/23/2007
Application #:
10907873
Filing Dt:
04/19/2005
Publication #:
US20060231945
Pub Dt:
10/19/2006
Title:
HEAT DISSIPATION FOR HEAT GENERATING ELEMENT OF SEMICONDUCTOR DEVICE AND RELATED METHOD
10
Patent #:
7504700
Issue Dt:
03/17/2009
Application #:
10907935
Filing Dt:
04/21/2005
Publication #:
US20060237803
Pub Dt:
10/26/2006
Title:
METHOD OF FORMING AN ULTRA-THIN [[HFSIO]] METAL SILCATE FILM FOR HIGH PERFORMANCE CMOS APPLICATIONS AND SEMICONDUCTOR STRUCTURE FORMED IN SAID METHOD
11
Patent #:
7102181
Issue Dt:
09/05/2006
Application #:
10907971
Filing Dt:
04/22/2005
Title:
STRUCTURE AND METHOD FOR DUAL-GATE FET WITH SOI SUBSTRATE
12
Patent #:
7251756
Issue Dt:
07/31/2007
Application #:
10908033
Filing Dt:
04/26/2005
Publication #:
US20060239088
Pub Dt:
10/26/2006
Title:
METHOD AND APPARATUS FOR INCREASING FUSE PROGRAMMING YIELD THROUGH PREFERRED USE OF DUPLICATE DATA
13
Patent #:
7329951
Issue Dt:
02/12/2008
Application #:
10908083
Filing Dt:
04/27/2005
Publication #:
US20060244139
Pub Dt:
11/02/2006
Title:
SOLDER BUMPS IN FLIP-CHIP TECHNOLOGIES
14
Patent #:
7348210
Issue Dt:
03/25/2008
Application #:
10908084
Filing Dt:
04/27/2005
Publication #:
US20060246703
Pub Dt:
11/02/2006
Title:
POST BUMP PASSIVATION FOR SOFT ERROR PROTECTION
15
Patent #:
7418689
Issue Dt:
08/26/2008
Application #:
10908102
Filing Dt:
04/27/2005
Publication #:
US20060248488
Pub Dt:
11/02/2006
Title:
METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION
16
Patent #:
7355249
Issue Dt:
04/08/2008
Application #:
10908117
Filing Dt:
04/28/2005
Publication #:
US20060244062
Pub Dt:
11/02/2006
Title:
SILICON-ON-INSULATOR BASED RADIATION DETECTION DEVICE AND METHOD
17
Patent #:
7288482
Issue Dt:
10/30/2007
Application #:
10908252
Filing Dt:
05/04/2005
Publication #:
US20060252269
Pub Dt:
11/09/2006
Title:
SILICON NITRIDE ETCHING METHODS
18
Patent #:
7200257
Issue Dt:
04/03/2007
Application #:
10908284
Filing Dt:
05/05/2005
Publication #:
US20060253828
Pub Dt:
11/09/2006
Title:
STRUCTURE AND METHODOLOGY FOR FABRICATION AND INSPECTION OF PHOTOMASKS
19
Patent #:
7389480
Issue Dt:
06/17/2008
Application #:
10908342
Filing Dt:
05/09/2005
Publication #:
US20060253806
Pub Dt:
11/09/2006
Title:
CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS
20
Patent #:
7361993
Issue Dt:
04/22/2008
Application #:
10908346
Filing Dt:
05/09/2005
Publication #:
US20060249848
Pub Dt:
11/09/2006
Title:
TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME
21
Patent #:
7250363
Issue Dt:
07/31/2007
Application #:
10908357
Filing Dt:
05/09/2005
Publication #:
US20060252263
Pub Dt:
11/09/2006
Title:
ALIGNED DUMMY METAL FILL AND HOLE SHAPES
22
Patent #:
7122898
Issue Dt:
10/17/2006
Application #:
10908360
Filing Dt:
05/09/2005
Publication #:
US20060249846
Pub Dt:
11/09/2006
Title:
ELECTRICAL PROGRAMMABLE METAL RESISTOR
23
Patent #:
7262484
Issue Dt:
08/28/2007
Application #:
10908361
Filing Dt:
05/09/2005
Publication #:
US20060249813
Pub Dt:
11/09/2006
Title:
STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS
24
Patent #:
7446350
Issue Dt:
11/04/2008
Application #:
10908394
Filing Dt:
05/10/2005
Publication #:
US20060255330
Pub Dt:
11/16/2006
Title:
EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER
25
Patent #:
7132322
Issue Dt:
11/07/2006
Application #:
10908411
Filing Dt:
05/11/2005
Publication #:
US20060258073
Pub Dt:
11/16/2006
Title:
METHOD FOR FORMING A SIGE OR SIGEC GATE SELECTIVELY IN A COMPLEMENTARY MIS/MOS FET DEVICE
26
Patent #:
7952149
Issue Dt:
05/31/2011
Application #:
10908442
Filing Dt:
05/12/2005
Publication #:
US20060255375
Pub Dt:
11/16/2006
Title:
ANTI-HALO COMPENSATION
27
Patent #:
7355221
Issue Dt:
04/08/2008
Application #:
10908448
Filing Dt:
05/12/2005
Publication #:
US20060255415
Pub Dt:
11/16/2006
Title:
FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION
28
Patent #:
7101763
Issue Dt:
09/05/2006
Application #:
10908556
Filing Dt:
05/17/2005
Title:
LOW CAPACITANCE JUNCTION-ISOLATION FOR BULK FINFET TECHNOLOGY
29
Patent #:
7087966
Issue Dt:
08/08/2006
Application #:
10908583
Filing Dt:
05/18/2005
Title:
DOUBLE-GATE FETS (FIELD EFFECT TRANSISTORS)
30
Patent #:
7308669
Issue Dt:
12/11/2007
Application #:
10908593
Filing Dt:
05/18/2005
Publication #:
US20060265684
Pub Dt:
11/23/2006
Title:
THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT
31
Patent #:
8118535
Issue Dt:
02/21/2012
Application #:
10908594
Filing Dt:
05/18/2005
Publication #:
US20060263197
Pub Dt:
11/23/2006
Title:
POD SWAPPING INTERNAL TO TOOL RUN TIME
32
Patent #:
7829965
Issue Dt:
11/09/2010
Application #:
10908601
Filing Dt:
05/18/2005
Publication #:
US20060261426
Pub Dt:
11/23/2006
Title:
A TOUCHING MICROLENS STRUCTURE FOR A PIXEL SENSOR AND METHOD OF FABRICATION
33
Patent #:
7305334
Issue Dt:
12/04/2007
Application #:
10908724
Filing Dt:
05/24/2005
Publication #:
US20060282246
Pub Dt:
12/14/2006
Title:
METHODOLOGY FOR IMAGE FIDELITY VERIFICATION
34
Patent #:
7319591
Issue Dt:
01/15/2008
Application #:
10908796
Filing Dt:
05/26/2005
Publication #:
US20060268521
Pub Dt:
11/30/2006
Title:
OPTIMIZED THERMALLY CONDUCTIVE PLATE AND ATTACHMENT METHOD FOR ENHANCED THERMAL PERFORMANCE AND RELIABILITY OF FLIP CHIP ORGANIC PACKAGES
35
Patent #:
7287468
Issue Dt:
10/30/2007
Application #:
10908883
Filing Dt:
05/31/2005
Publication #:
US20060269770
Pub Dt:
11/30/2006
Title:
NICKEL ALLOY PLATED STRUCTURE
36
Patent #:
7214603
Issue Dt:
05/08/2007
Application #:
10908931
Filing Dt:
06/01/2005
Publication #:
US20060183314
Pub Dt:
08/17/2006
Title:
METHOD FOR FABRICATING INTERCONNECT STRUCTURES WITH REDUCED PLASMA DAMAGE
37
Patent #:
8040813
Issue Dt:
10/18/2011
Application #:
10908959
Filing Dt:
06/02/2005
Publication #:
US20060274681
Pub Dt:
12/07/2006
Title:
APPARATUS AND METHOD FOR REDUCED LOADING OF SIGNAL TRANSMISSION ELEMENTS
38
Patent #:
7173310
Issue Dt:
02/06/2007
Application #:
10908961
Filing Dt:
06/02/2005
Publication #:
US20060273372
Pub Dt:
12/07/2006
Title:
LATERAL LUBISTOR STRUCTURE AND METHOD
39
Patent #:
7217578
Issue Dt:
05/15/2007
Application #:
10909497
Filing Dt:
08/02/2004
Title:
ADVANCED PROCESS CONTROL OF THERMAL OXIDATION PROCESSES, AND SYSTEMS FOR ACCOMPLISHING SAME
40
Patent #:
7186650
Issue Dt:
03/06/2007
Application #:
10909509
Filing Dt:
08/02/2004
Title:
CONTROL OF BOTTOM DIMENSION OF TAPERED CONTACT VIA VARIATION(S) OF ETCH PROCESS
41
Patent #:
7295161
Issue Dt:
11/13/2007
Application #:
10912959
Filing Dt:
08/06/2004
Publication #:
US20060028378
Pub Dt:
02/09/2006
Title:
APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING WIRE BONDS AS RADIATING ELEMENTS
42
Patent #:
7179692
Issue Dt:
02/20/2007
Application #:
10913409
Filing Dt:
08/09/2004
Publication #:
US20050006666
Pub Dt:
01/13/2005
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE
43
Patent #:
7397876
Issue Dt:
07/08/2008
Application #:
10915790
Filing Dt:
08/11/2004
Publication #:
US20060045224
Pub Dt:
03/02/2006
Title:
METHODS AND ARRANGEMENTS FOR LINK POWER REDUCTION
44
Patent #:
7129548
Issue Dt:
10/31/2006
Application #:
10916201
Filing Dt:
08/11/2004
Publication #:
US20060033165
Pub Dt:
02/16/2006
Title:
MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS
45
Patent #:
7271446
Issue Dt:
09/18/2007
Application #:
10916814
Filing Dt:
08/12/2004
Publication #:
US20050014314
Pub Dt:
01/20/2005
Title:
ULTRA-THIN CHANNEL DEVICE WITH RAISED SOURCE AND DRAIN AND SOLID SOURCE EXTENSION DOPING
46
Patent #:
7312487
Issue Dt:
12/25/2007
Application #:
10919121
Filing Dt:
08/16/2004
Publication #:
US20060033110
Pub Dt:
02/16/2006
Title:
THREE DIMENSIONAL INTEGRATED CIRCUIT
47
Patent #:
7129159
Issue Dt:
10/31/2006
Application #:
10921007
Filing Dt:
08/17/2004
Publication #:
US20060040501
Pub Dt:
02/23/2006
Title:
INTEGRATED DUAL DAMASCENE RIE PROCESS WITH ORGANIC PATTERNING LAYER
48
Patent #:
7268066
Issue Dt:
09/11/2007
Application #:
10922093
Filing Dt:
08/19/2004
Publication #:
US20050020019
Pub Dt:
01/27/2005
Title:
METHOD FOR SEMICONDUCTOR GATE LINE DIMENSION REDUCTION
49
Patent #:
7561541
Issue Dt:
07/14/2009
Application #:
10925112
Filing Dt:
08/24/2004
Publication #:
US20050190709
Pub Dt:
09/01/2005
Title:
DEEP SLEEP MODE FOR WLAN COMMUNICATION SYSTEMS
50
Patent #:
7340473
Issue Dt:
03/04/2008
Application #:
10926587
Filing Dt:
08/26/2004
Publication #:
US20060047680
Pub Dt:
03/02/2006
Title:
METHOD AND SYSTEM FOR BUILDING BINARY DECISION DIAGRAMS EFFICIENTLY IN A STRUCTURAL NETWORK REPRESENTATION OF A DIGITAL CIRCUIT
51
Patent #:
7395196
Issue Dt:
07/01/2008
Application #:
10929935
Filing Dt:
08/30/2004
Publication #:
US20060048082
Pub Dt:
03/02/2006
Title:
TEST-CASES FOR FUNCTIONAL VERIFICATION OF SYSTEM-LEVEL INTERCONNECT
52
Patent #:
6962872
Issue Dt:
11/08/2005
Application #:
10930304
Filing Dt:
08/31/2004
Publication #:
US20050023664
Pub Dt:
02/03/2005
Title:
HIGH DENSITY CHIP CARRIER WITH INTEGRATED PASSIVE DEVICES
53
Patent #:
7227205
Issue Dt:
06/05/2007
Application #:
10930404
Filing Dt:
08/31/2004
Publication #:
US20050285187
Pub Dt:
12/29/2005
Title:
STRAINED-SILICON CMOS DEVICE AND METHOD
54
Patent #:
7799517
Issue Dt:
09/21/2010
Application #:
10930432
Filing Dt:
08/31/2004
Title:
SINGLE/DOUBLE DIPOLE MASK FOR CONTACT HOLES
55
Patent #:
7311809
Issue Dt:
12/25/2007
Application #:
10930823
Filing Dt:
09/01/2004
Publication #:
US20050077173
Pub Dt:
04/14/2005
Title:
PLATING APPARATUS FOR SUBSTRATE
56
Patent #:
7259966
Issue Dt:
08/21/2007
Application #:
10931100
Filing Dt:
08/31/2004
Publication #:
US20060044748
Pub Dt:
03/02/2006
Title:
APPARATUS, SYSTEM, AND METHOD FOR REDUCING ROTATIONAL VIBRATION TRANSMISSION WITHIN A DATA STORAGE SYSTEM
57
Patent #:
7102205
Issue Dt:
09/05/2006
Application #:
10931660
Filing Dt:
09/01/2004
Publication #:
US20060043529
Pub Dt:
03/02/2006
Title:
BIPOLAR TRANSISTOR WITH EXTRINSIC STRESS LAYER
58
Patent #:
7141115
Issue Dt:
11/28/2006
Application #:
10932598
Filing Dt:
09/02/2004
Publication #:
US20060042542
Pub Dt:
03/02/2006
Title:
METHOD OF PRODUCING SILICON-GERMANIUM-ON-INSULATOR MATERIAL USING UNSTRAINED GE-CONTAINING SOURCE LAYERS
59
Patent #:
7098508
Issue Dt:
08/29/2006
Application #:
10932982
Filing Dt:
09/02/2004
Publication #:
US20050045995
Pub Dt:
03/03/2005
Title:
ULTRA-THIN SILICON-ON-INSULATOR AND STRAINED-SILICON-DIRECT-ON-INSULATOR WITH HYBRID CRYSTAL ORIENTATIONS
60
Patent #:
7558687
Issue Dt:
07/07/2009
Application #:
10932999
Filing Dt:
09/02/2004
Title:
METHOD AND APPARATUS FOR DYNAMIC ADJUSTMENT OF A SENSOR SAMPLING RATE
61
Patent #:
7434308
Issue Dt:
10/14/2008
Application #:
10933051
Filing Dt:
09/02/2004
Publication #:
US20060042825
Pub Dt:
03/02/2006
Title:
COOLING OF SUBSTRATE USING INTERPOSER CHANNELS
62
Patent #:
7052921
Issue Dt:
05/30/2006
Application #:
10934192
Filing Dt:
09/03/2004
Title:
SYSTEM AND METHOD USING IN SITU SCATTEROMETRY TO DETECT PHOTORESIST PATTERN INTEGRITY DURING THE PHOTOLITHOGRAPHY PROCESS
63
Patent #:
7544610
Issue Dt:
06/09/2009
Application #:
10935497
Filing Dt:
09/07/2004
Publication #:
US20060051961
Pub Dt:
03/09/2006
Title:
METHOD AND PROCESS FOR FORMING A SELF-ALIGNED SILICIDE CONTACT
64
Patent #:
7239516
Issue Dt:
07/03/2007
Application #:
10939230
Filing Dt:
09/10/2004
Publication #:
US20060056156
Pub Dt:
03/16/2006
Title:
FLEXURE PLATE FOR MAINTAINING CONTACT BETWEEN A COOLING PLATE/HEAT SINK AND A MICROCHIP
65
Patent #:
7235812
Issue Dt:
06/26/2007
Application #:
10939736
Filing Dt:
09/13/2004
Publication #:
US20060054891
Pub Dt:
03/16/2006
Title:
METHOD OF CREATING DEFECT FREE HIGH GE CONTENT (>25%) SIGE-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES
66
Patent #:
7305571
Issue Dt:
12/04/2007
Application #:
10940543
Filing Dt:
09/14/2004
Publication #:
US20060056128
Pub Dt:
03/16/2006
Title:
POWER NETWORK RECONFIGURATION USING MEM SWITCHES
67
Patent #:
6989601
Issue Dt:
01/24/2006
Application #:
10946071
Filing Dt:
09/22/2004
Title:
COPPER DAMASCENE WITH LOW-K CAPPING LAYER AND IMPROVED ELECTROMIGRATION RELIABILITY
68
Patent #:
7096436
Issue Dt:
08/22/2006
Application #:
10946552
Filing Dt:
09/21/2004
Publication #:
US20050039153
Pub Dt:
02/17/2005
Title:
MACRO DESIGN TECHNIQUES TO ACCOMMODATE CHIP LEVEL WIRING AND CIRCUIT PLACEMENT ACROSS THE MACRO
69
Patent #:
7783037
Issue Dt:
08/24/2010
Application #:
10946653
Filing Dt:
09/20/2004
Title:
MULTI-GIGABIT PER SECOND COMPUTING OF THE RIJNDAEL INVERSE CIPHER
70
Patent #:
7427773
Issue Dt:
09/23/2008
Application #:
10948421
Filing Dt:
09/23/2004
Publication #:
US20050104067
Pub Dt:
05/19/2005
Title:
LAYER TRANSFER OF LOW DEFECT SIGE USING AN ETCH-BACK PROCESS
71
Patent #:
7098476
Issue Dt:
08/29/2006
Application #:
10949837
Filing Dt:
09/24/2004
Publication #:
US20050037604
Pub Dt:
02/17/2005
Title:
MULTILAYER INTERCONNECT STRUCTURE CONTAINING AIR GAPS AND METHOD FOR MAKING
72
Patent #:
7358586
Issue Dt:
04/15/2008
Application #:
10951745
Filing Dt:
09/28/2004
Publication #:
US20060071274
Pub Dt:
04/06/2006
Title:
SILICON-ON-INSULATOR WAFER HAVING REENTRANT SHAPE DIELECTRIC TRENCHES
73
Patent #:
7191305
Issue Dt:
03/13/2007
Application #:
10952269
Filing Dt:
09/28/2004
Publication #:
US20050044337
Pub Dt:
02/24/2005
Title:
METHOD AND APPARATUS FOR ADDRESS DECODING OF EMBEDDED DRAM DEVICES
74
Patent #:
7173274
Issue Dt:
02/06/2007
Application #:
10953378
Filing Dt:
09/29/2004
Publication #:
US20050054171
Pub Dt:
03/10/2005
Title:
INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY
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Title:
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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