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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
10/26/2010
Application #:
11772418
Filing Dt:
07/02/2007
Publication #:
Pub Dt:
12/06/2007
Title:
DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY
2
Patent #:
Issue Dt:
03/09/2010
Application #:
11772464
Filing Dt:
07/02/2007
Publication #:
Pub Dt:
01/08/2009
Title:
ANTENNA ARRAY FEED LINE STRUCTURES FOR MILLIMETER WAVE APPLICATIONS
3
Patent #:
Issue Dt:
08/31/2010
Application #:
11772503
Filing Dt:
07/02/2007
Publication #:
Pub Dt:
01/08/2009
Title:
METHOD AND APPARATUS FOR CORRELATING TEST EQUIPMENT HEALTH AND TEST RESULTS
4
Patent #:
Issue Dt:
01/06/2009
Application #:
11772592
Filing Dt:
07/02/2007
Publication #:
Pub Dt:
01/08/2009
Title:
SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL
5
Patent #:
Issue Dt:
03/02/2010
Application #:
11772899
Filing Dt:
07/03/2007
Publication #:
Pub Dt:
11/01/2007
Title:
AIR-GAP INSULATED INTERCONNECTIONS
6
Patent #:
Issue Dt:
07/12/2011
Application #:
11772908
Filing Dt:
07/03/2007
Publication #:
Pub Dt:
01/08/2009
Title:
EFFICIENT UTILIZATION OF A MULTI-SOURCE NETWORK OF CONTROL LOGIC TO ACHIEVE TIMING CLOSURE IN A CLOCKED LOGIC CIRCUIT
7
Patent #:
Issue Dt:
02/03/2009
Application #:
11773607
Filing Dt:
07/05/2007
Publication #:
Pub Dt:
01/08/2009
Title:
BODY-CONTACTED FINFET
8
Patent #:
Issue Dt:
01/24/2012
Application #:
11773631
Filing Dt:
07/05/2007
Publication #:
Pub Dt:
01/31/2008
Title:
METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY
9
Patent #:
Issue Dt:
10/19/2010
Application #:
11774087
Filing Dt:
07/06/2007
Publication #:
Pub Dt:
10/16/2008
Title:
DETECTOR FOR DETECTING ELECTROMAGNETIC WAVES
10
Patent #:
Issue Dt:
07/12/2011
Application #:
11774245
Filing Dt:
07/06/2007
Publication #:
Pub Dt:
11/01/2007
Title:
SYSTEM AND METHOD FOR DYNAMICALLY MANAGING POWER CONSUMPTION OF INTEGRATED CIRCUITRY
11
Patent #:
Issue Dt:
01/12/2010
Application #:
11774663
Filing Dt:
07/09/2007
Publication #:
Pub Dt:
11/01/2007
Title:
DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION
12
Patent #:
Issue Dt:
06/03/2008
Application #:
11774853
Filing Dt:
07/09/2007
Publication #:
Pub Dt:
11/22/2007
Title:
DUAL WIRED INTEGRATED CIRCUIT CHIPS
13
Patent #:
Issue Dt:
11/16/2010
Application #:
11775257
Filing Dt:
07/10/2007
Publication #:
Pub Dt:
01/15/2009
Title:
METHOD FOR FORMING CONDUCTIVE STRUCTURES
14
Patent #:
Issue Dt:
10/19/2010
Application #:
11775451
Filing Dt:
07/10/2007
Publication #:
Pub Dt:
01/15/2009
Title:
METHOD AND APPARATUS FOR LENGTH DECODING VARIABLE LENGTH INSTRUCTIONS
15
Patent #:
Issue Dt:
10/19/2010
Application #:
11775456
Filing Dt:
07/10/2007
Publication #:
Pub Dt:
01/15/2009
Title:
METHOD AND APPARATUS FOR LENGTH DECODING AND IDENTIFYING BOUNDARIES OF VARIABLE LENGTH INSTRUCTIONS
16
Patent #:
Issue Dt:
02/22/2011
Application #:
11775531
Filing Dt:
07/10/2007
Publication #:
Pub Dt:
01/15/2009
Title:
DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD
17
Patent #:
Issue Dt:
04/21/2009
Application #:
11775607
Filing Dt:
07/10/2007
Publication #:
Pub Dt:
11/08/2007
Title:
INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF
18
Patent #:
Issue Dt:
04/17/2012
Application #:
11775619
Filing Dt:
07/10/2007
Publication #:
Pub Dt:
01/17/2008
Title:
STRAINED MOS DEVICE AND METHODS FOR ITS FABRICATION
19
Patent #:
Issue Dt:
06/15/2010
Application #:
11776118
Filing Dt:
07/11/2007
Publication #:
Pub Dt:
01/15/2009
Title:
FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF
20
Patent #:
Issue Dt:
12/29/2009
Application #:
11776155
Filing Dt:
07/11/2007
Publication #:
Pub Dt:
06/05/2008
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
21
Patent #:
Issue Dt:
01/13/2009
Application #:
11776710
Filing Dt:
07/12/2007
Publication #:
Pub Dt:
01/15/2009
Title:
PROCESS FOR FINFET SPACER FORMATION
22
Patent #:
Issue Dt:
12/21/2010
Application #:
11776738
Filing Dt:
07/12/2007
Publication #:
Pub Dt:
11/08/2007
Title:
STRUCTURE AND METHOD FOR LATCHUP SUPPRESSION
23
Patent #:
Issue Dt:
09/13/2011
Application #:
11776810
Filing Dt:
07/12/2007
Publication #:
Pub Dt:
01/15/2009
Title:
DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA
24
Patent #:
Issue Dt:
02/22/2011
Application #:
11776986
Filing Dt:
07/12/2007
Publication #:
Pub Dt:
01/15/2009
Title:
MECHANISM FOR USING PERFORMANCE COUNTERS TO IDENTIFY REASONS AND DELAY TIMES FOR INSTRUCTIONS THAT ARE STALLED DURING RETIREMENT
25
Patent #:
Issue Dt:
06/16/2009
Application #:
11777329
Filing Dt:
07/13/2007
Publication #:
Pub Dt:
01/15/2009
Title:
APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PRODUCED BY AN INTEGRATED CIRCUIT
26
Patent #:
Issue Dt:
02/08/2011
Application #:
11777837
Filing Dt:
07/13/2007
Publication #:
Pub Dt:
01/15/2009
Title:
THERMALLY PUMPED LIQUID/GAS HEAT EXCHANGER FOR COOLING HEAT-GENERATING DEVICES
27
Patent #:
Issue Dt:
03/22/2011
Application #:
11778045
Filing Dt:
07/15/2007
Publication #:
Pub Dt:
01/15/2009
Title:
METHODS FOR FORMING SELF-ALIGNED DUAL STRESS LINERS FOR CMOS SEMICONDUCTOR DEVICES
28
Patent #:
Issue Dt:
03/29/2011
Application #:
11778185
Filing Dt:
07/16/2007
Publication #:
Pub Dt:
01/22/2009
Title:
ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
29
Patent #:
Issue Dt:
06/08/2010
Application #:
11778209
Filing Dt:
07/16/2007
Publication #:
Pub Dt:
01/22/2009
Title:
GRAPHENE-BASED TRANSISTOR
30
Patent #:
Issue Dt:
04/06/2010
Application #:
11778217
Filing Dt:
07/16/2007
Publication #:
Pub Dt:
01/22/2009
Title:
FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE
31
Patent #:
Issue Dt:
04/29/2014
Application #:
11778238
Filing Dt:
07/16/2007
Publication #:
Pub Dt:
01/17/2008
Title:
METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC
32
Patent #:
Issue Dt:
07/14/2009
Application #:
11778641
Filing Dt:
07/16/2007
Publication #:
Pub Dt:
01/17/2008
Title:
AUTONOMIC PARITY EXCHANGE
33
Patent #:
Issue Dt:
05/18/2010
Application #:
11778852
Filing Dt:
07/17/2007
Publication #:
Pub Dt:
01/22/2009
Title:
INVERSE SELF-ALIGNED SPACER LITHOGRAPHY
34
Patent #:
Issue Dt:
10/12/2010
Application #:
11778876
Filing Dt:
07/17/2007
Publication #:
Pub Dt:
01/22/2009
Title:
INTEGRATED WAFER PROCESSING SYSTEM FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS
35
Patent #:
Issue Dt:
02/18/2014
Application #:
11778930
Filing Dt:
07/17/2007
Publication #:
Pub Dt:
07/31/2008
Title:
METHOD FOR FORMING SILICON/GERMANIUM CONTAINING DRAIN/SOURCE REGIONS IN TRANSISTORS WITH REDUCED SILICON/GERMANIUM LOSS
36
Patent #:
Issue Dt:
11/08/2011
Application #:
11779432
Filing Dt:
07/18/2007
Publication #:
Pub Dt:
01/22/2009
Title:
STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS
37
Patent #:
Issue Dt:
04/19/2011
Application #:
11780283
Filing Dt:
07/19/2007
Publication #:
Pub Dt:
01/22/2009
Title:
SPECULATIVE MEMORY PREFETCH
38
Patent #:
Issue Dt:
03/15/2011
Application #:
11780519
Filing Dt:
07/20/2007
Publication #:
Pub Dt:
01/22/2009
Title:
THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME
39
Patent #:
Issue Dt:
09/13/2011
Application #:
11780530
Filing Dt:
07/20/2007
Publication #:
Pub Dt:
01/22/2009
Title:
METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
40
Patent #:
Issue Dt:
10/19/2010
Application #:
11780712
Filing Dt:
07/20/2007
Publication #:
Pub Dt:
01/31/2008
Title:
ARCHITECTURAL LEVEL THROUGHPUT BASED POWER MODELING METHODOLOGY AND APPARATUS FOR PERVASIVELY CLOCK-GATED PROCESSOR CORES
41
Patent #:
Issue Dt:
10/11/2011
Application #:
11781363
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
01/29/2009
Title:
MODELING HOMOGENEOUS PARALLELISM
42
Patent #:
Issue Dt:
07/15/2008
Application #:
11781370
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
11/15/2007
Title:
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
43
Patent #:
Issue Dt:
05/02/2017
Application #:
11781664
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
01/29/2009
Title:
INTEGRATED CIRCUIT EMPLOYING VARIABLE THICKNESS FILM
44
Patent #:
Issue Dt:
10/11/2011
Application #:
11781833
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
12/13/2007
Title:
METHODS OF CREATING A DICTIONARY FOR DATA COMPRESSION
45
Patent #:
Issue Dt:
01/12/2010
Application #:
11781854
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
01/29/2009
Title:
COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE
46
Patent #:
Issue Dt:
07/06/2010
Application #:
11782071
Filing Dt:
07/24/2007
Publication #:
Pub Dt:
01/29/2009
Title:
HALF-SELECT COMPLIANT MEMORY CELL PRECHARGE CIRCUIT
47
Patent #:
Issue Dt:
12/28/2010
Application #:
11782079
Filing Dt:
07/24/2007
Publication #:
Pub Dt:
01/29/2009
Title:
PARTIALLY GATED FINFET WITH GATE DIELECTRIC ON ONLY ONE SIDEWALL
48
Patent #:
Issue Dt:
04/27/2010
Application #:
11782734
Filing Dt:
07/25/2007
Publication #:
Pub Dt:
07/03/2008
Title:
TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS WITH INCREASED ROBUSTNESS WITH RESPECT TO BARRIER DEFECTS IN VIAS
49
Patent #:
Issue Dt:
01/20/2009
Application #:
11782808
Filing Dt:
07/25/2007
Publication #:
Pub Dt:
01/29/2009
Title:
METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO)
50
Patent #:
Issue Dt:
10/19/2010
Application #:
11788215
Filing Dt:
04/18/2007
Publication #:
Pub Dt:
10/23/2008
Title:
TOKEN BASED POWER CONTROL MECHANISM
51
Patent #:
Issue Dt:
03/15/2011
Application #:
11788969
Filing Dt:
04/23/2007
Publication #:
Pub Dt:
10/23/2008
Title:
METHOD OF CONTROLLED LOW-K VIA ETCH FOR CU INTERCONNECTIONS
52
Patent #:
Issue Dt:
07/28/2015
Application #:
11789157
Filing Dt:
04/23/2007
Publication #:
Pub Dt:
10/23/2008
Title:
Method for semiconductor wafer fabrication utilizing a cleaning substrate
53
Patent #:
Issue Dt:
02/12/2013
Application #:
11796073
Filing Dt:
04/26/2007
Publication #:
Pub Dt:
10/30/2008
Title:
MEMORY DEVICE WITH IMPROVED PERFORMANCE
54
Patent #:
Issue Dt:
06/17/2008
Application #:
11799261
Filing Dt:
04/10/2007
Publication #:
Pub Dt:
09/20/2007
Title:
INTEGRATION OF STRAINED GE INTO ADVANCED CMOS TECHNOLOGY
55
Patent #:
Issue Dt:
11/26/2013
Application #:
11811418
Filing Dt:
06/07/2007
Publication #:
Pub Dt:
12/11/2008
Title:
METHOD FOR DEPOSITING A CONDUCTIVE CAPPING LAYER ON METAL LINES
56
Patent #:
Issue Dt:
01/04/2011
Application #:
11819748
Filing Dt:
06/28/2007
Publication #:
Pub Dt:
09/04/2008
Title:
SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION
57
Patent #:
Issue Dt:
03/25/2008
Application #:
11820713
Filing Dt:
06/19/2007
Publication #:
Pub Dt:
10/25/2007
Title:
METHOD OF FORMING SILICON-ON-INSULATOR WAFER HAVING REENTRANT SHAPE DIELECTRIC TRENCHES
58
Patent #:
Issue Dt:
03/25/2014
Application #:
11823056
Filing Dt:
06/26/2007
Publication #:
Pub Dt:
01/01/2009
Title:
Method for preventing void formation in a solder joint
59
Patent #:
Issue Dt:
02/01/2011
Application #:
11828382
Filing Dt:
07/26/2007
Publication #:
Pub Dt:
01/29/2009
Title:
METHOD AND APPARATUS FOR HANDLING EXCESS DATA DURING MEMORY ACCESS
60
Patent #:
Issue Dt:
12/21/2010
Application #:
11828657
Filing Dt:
07/26/2007
Publication #:
Pub Dt:
01/29/2009
Title:
OVERHEAD TRANSPORT SERVICE VEHICLE AND METHOD
61
Patent #:
Issue Dt:
07/20/2010
Application #:
11828705
Filing Dt:
07/26/2007
Publication #:
Pub Dt:
01/29/2009
Title:
METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS
62
Patent #:
Issue Dt:
04/19/2011
Application #:
11829187
Filing Dt:
07/27/2007
Publication #:
Pub Dt:
01/24/2008
Title:
ENABLING MEMORY REDUNDANCY DURING TESTING
63
Patent #:
Issue Dt:
05/08/2012
Application #:
11830090
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
02/05/2009
Title:
SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS
64
Patent #:
Issue Dt:
10/20/2009
Application #:
11830116
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
02/05/2009
Title:
SHRINK TEST MODE TO IDENTIFY NTH ORDER SPEED PATHS
65
Patent #:
Issue Dt:
02/24/2009
Application #:
11830200
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
01/24/2008
Title:
APPARATUS AND METHODS FOR INTEGRALLY PACKAGING OPTOELECTRONIC DEVICES, IC CHIPS AND OPTICAL TRANSMISSION LINES
66
Patent #:
Issue Dt:
04/19/2011
Application #:
11830213
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
12/25/2008
Title:
ELECTROLYTIC DEVICE BASED ON A SOLUTION-PROCESSED ELECTROLYTE
67
Patent #:
Issue Dt:
12/02/2008
Application #:
11830221
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
02/07/2008
Title:
CIRCUITS AND METHODS FOR IMPLEMENTING TRANSFORMER-COUPLED AMPLIFIERS AT MILLIMETER WAVE FREQUENCIES
68
Patent #:
Issue Dt:
02/19/2013
Application #:
11830239
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
01/17/2013
Title:
APPARATUS AND METHODS FOR PACKAGING ANTENNAS WITH INTEGRATED CIRCUIT CHIPS FOR MILLIMETER WAVE APPLICATIONS
69
Patent #:
Issue Dt:
02/07/2012
Application #:
11830316
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
02/05/2009
Title:
FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
70
Patent #:
Issue Dt:
11/17/2009
Application #:
11830328
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
02/05/2009
Title:
FINFET FLASH MEMORY DEVICE WITH AN EXTENDED FLOATING BACK GATE
71
Patent #:
Issue Dt:
07/06/2010
Application #:
11830349
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
02/05/2009
Title:
C4NP SERVO CONTROLLED SOLDER FILL HEAD
72
Patent #:
Issue Dt:
09/09/2008
Application #:
11830464
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
11/15/2007
Title:
STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS
73
Patent #:
Issue Dt:
09/16/2008
Application #:
11830489
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
11/22/2007
Title:
STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES
74
Patent #:
Issue Dt:
05/26/2009
Application #:
11830872
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
11/22/2007
Title:
DOUBLE GATE ISOLATION
75
Patent #:
Issue Dt:
06/14/2011
Application #:
11831005
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
76
Patent #:
Issue Dt:
04/12/2011
Application #:
11831099
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
LAYER PATTERNING USING DOUBLE EXPOSURE PROCESSES IN A SINGLE PHOTORESIST LAYER
77
Patent #:
Issue Dt:
10/04/2011
Application #:
11831119
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
PLACING VIRTUAL MACHINE MONITOR (VMM) CODE IN GUEST CONTEXT TO SPEED MEMORY MAPPED INPUT/OUTPUT VIRTUALIZATION
78
Patent #:
Issue Dt:
02/07/2012
Application #:
11831137
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
01/24/2008
Title:
METHOD FOR PERFORMING CHEMICAL SHRINK PROCESS OVER BARC (BOTTOM ANTI-REFLECTIVE COATING)
79
Patent #:
Issue Dt:
08/09/2011
Application #:
11831138
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
MICROELECTRONIC STRUCTURE INCLUDING DUAL DAMASCENE STRUCTURE AND HIGH CONTRAST ALIGNMENT MARK
80
Patent #:
Issue Dt:
07/28/2009
Application #:
11831149
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME
81
Patent #:
Issue Dt:
04/20/2010
Application #:
11831208
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
ORIENTATION-INDEPENDENT MULTI-LAYER BEOL CAPACITOR
82
Patent #:
Issue Dt:
03/22/2011
Application #:
11832220
Filing Dt:
08/01/2007
Publication #:
Pub Dt:
12/20/2007
Title:
DRAM ACCESS COMMAND QUEUING
83
Patent #:
Issue Dt:
03/29/2011
Application #:
11832453
Filing Dt:
08/01/2007
Publication #:
Pub Dt:
01/24/2008
Title:
ENHANCING A POWER DISTRIBUTION SYSTEM IN A CERAMIC INTEGRATED CIRCUIT PACKAGE
84
Patent #:
Issue Dt:
03/08/2011
Application #:
11833112
Filing Dt:
08/02/2007
Publication #:
Pub Dt:
02/05/2009
Title:
SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS
85
Patent #:
Issue Dt:
06/01/2010
Application #:
11833143
Filing Dt:
08/02/2007
Publication #:
Pub Dt:
02/05/2009
Title:
PHASE CHANGE MEMORY WITH DUAL WORD LINES AND SOURCE LINES AND METHOD OF OPERATING SAME
86
Patent #:
Issue Dt:
09/25/2012
Application #:
11833274
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
03/06/2008
Title:
DATA STORAGE SYSTEMS
87
Patent #:
Issue Dt:
06/18/2013
Application #:
11833283
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
11/22/2007
Title:
POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY
88
Patent #:
Issue Dt:
06/28/2011
Application #:
11833321
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/05/2009
Title:
PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL
89
Patent #:
Issue Dt:
02/09/2010
Application #:
11833354
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/05/2009
Title:
PROGRAMMABLE VIA DEVICES WITH AIR GAP ISOLATION
90
Patent #:
Issue Dt:
04/26/2011
Application #:
11833538
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/05/2009
Title:
MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT
91
Patent #:
Issue Dt:
05/10/2011
Application #:
11834110
Filing Dt:
08/06/2007
Publication #:
Pub Dt:
02/12/2009
Title:
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
92
Patent #:
Issue Dt:
07/06/2010
Application #:
11834552
Filing Dt:
08/06/2007
Publication #:
Pub Dt:
02/12/2009
Title:
HEAT SINK WITH THERMALLY COMPLIANT BEAMS
93
Patent #:
Issue Dt:
05/27/2014
Application #:
11834641
Filing Dt:
08/06/2007
Publication #:
Pub Dt:
02/12/2009
Title:
FET DEVICE WITH STABILIZED THRESHOLD MODIFYING MATERIAL
94
Patent #:
Issue Dt:
12/21/2010
Application #:
11834752
Filing Dt:
08/07/2007
Publication #:
Pub Dt:
02/12/2009
Title:
BIDIRECTIONAL AND EXPANDABLE HEAT FLOW MEASUREMENT TOOL FOR UNITS OF AIR COOLED ELECTRICAL EQUIPMENT
95
Patent #:
Issue Dt:
10/19/2010
Application #:
11834956
Filing Dt:
08/07/2007
Publication #:
Pub Dt:
02/12/2009
Title:
ON-CHIP DECOUPLING CAPACITOR STRUCTURES
96
Patent #:
Issue Dt:
06/28/2011
Application #:
11834961
Filing Dt:
08/07/2007
Publication #:
Pub Dt:
02/12/2009
Title:
ON-CHIP DECOUPLING CAPACITOR STRUCTURES
97
Patent #:
Issue Dt:
08/09/2011
Application #:
11834971
Filing Dt:
08/07/2007
Publication #:
Pub Dt:
02/12/2009
Title:
APPARATUS AND METHOD OF ELECTROLYTIC REMOVAL OF METALS FROM A WAFER SURFACE
98
Patent #:
Issue Dt:
11/09/2010
Application #:
11834979
Filing Dt:
08/07/2007
Publication #:
Pub Dt:
02/12/2009
Title:
MULTIPLE EXPOSURE TECHNIQUE USING OPC TO CORRECT DISTORTION
99
Patent #:
Issue Dt:
12/22/2009
Application #:
11835167
Filing Dt:
08/07/2007
Publication #:
Pub Dt:
01/24/2008
Title:
VERTICAL NANOTUBE FIELD EFFECT TRANSISTOR
100
Patent #:
Issue Dt:
09/21/2010
Application #:
11835182
Filing Dt:
08/07/2007
Publication #:
Pub Dt:
02/28/2008
Title:
METHODS FOR MANUFACTURING A FINFET USING A CONVENTIONAL WAFER AND APPARATUS MANUFACTURED THEREFROM
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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