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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 46 of 146
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1
Patent #:
7880243
Issue Dt:
02/01/2011
Application #:
11835310
Filing Dt:
08/07/2007
Publication #:
US20090039434
Pub Dt:
02/12/2009
Title:
SIMPLE LOW POWER CIRCUIT STRUCTURE WITH METAL GATE AND HIGH-K DIELECTRIC
2
Patent #:
8512849
Issue Dt:
08/20/2013
Application #:
11836253
Filing Dt:
08/09/2007
Publication #:
US20090041989
Pub Dt:
02/12/2009
Title:
CORRUGATED INTERFACES FOR MULTILAYERED INTERCONNECTS
3
Patent #:
7740472
Issue Dt:
06/22/2010
Application #:
11836259
Filing Dt:
08/09/2007
Publication #:
US20080000536
Pub Dt:
01/03/2008
Title:
METHOD AND DEVICE FOR FLOWING A LIQUID ON A SURFACE
4
Patent #:
7958484
Issue Dt:
06/07/2011
Application #:
11836842
Filing Dt:
08/10/2007
Publication #:
US20070276896
Pub Dt:
11/29/2007
Title:
AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX
5
Patent #:
7652332
Issue Dt:
01/26/2010
Application #:
11837057
Filing Dt:
08/10/2007
Publication #:
US20090039426
Pub Dt:
02/12/2009
Title:
EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN
6
Patent #:
8055976
Issue Dt:
11/08/2011
Application #:
11837785
Filing Dt:
08/13/2007
Publication #:
US20090049365
Pub Dt:
02/19/2009
Title:
SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM
7
Patent #:
7558136
Issue Dt:
07/07/2009
Application #:
11838341
Filing Dt:
08/14/2007
Publication #:
US20070291562
Pub Dt:
12/20/2007
Title:
INTERNALLY ASYMMETRIC METHODS AND CIRCUITS FOR EVALUATING STATIC MEMORY CELL DYNAMIC STABILITY
8
Patent #:
7893549
Issue Dt:
02/22/2011
Application #:
11838507
Filing Dt:
08/14/2007
Publication #:
US20090045530
Pub Dt:
02/19/2009
Title:
MICROELECTRONIC LITHOGRAPHIC ALIGNMENT USING HIGH CONTRAST ALIGNMENT MARK
9
Patent #:
7755921
Issue Dt:
07/13/2010
Application #:
11838663
Filing Dt:
08/14/2007
Publication #:
US20090046493
Pub Dt:
02/19/2009
Title:
METHOD AND APPARATUS FOR FABRICATING SUB-LITHOGRAPHY DATA TRACKS FOR USE IN MAGNETIC SHIFT REGISTER MEMORY DEVICES
10
Patent #:
7388274
Issue Dt:
06/17/2008
Application #:
11838931
Filing Dt:
08/15/2007
Publication #:
US20070272961
Pub Dt:
11/29/2007
Title:
CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS
11
Patent #:
7566921
Issue Dt:
07/28/2009
Application #:
11838941
Filing Dt:
08/15/2007
Publication #:
US20070272946
Pub Dt:
11/29/2007
Title:
SILICON GERMANIUM EMITTER
12
Patent #:
8030167
Issue Dt:
10/04/2011
Application #:
11839106
Filing Dt:
08/15/2007
Publication #:
US20070275534
Pub Dt:
11/29/2007
Title:
VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES
13
Patent #:
8012848
Issue Dt:
09/06/2011
Application #:
11839585
Filing Dt:
08/16/2007
Publication #:
US20090045468
Pub Dt:
02/19/2009
Title:
TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION
14
Patent #:
7602217
Issue Dt:
10/13/2009
Application #:
11839611
Filing Dt:
08/16/2007
Publication #:
US20090045843
Pub Dt:
02/19/2009
Title:
LEVEL SHIFTER CIRCUIT WITH PRE-CHARGE/PRE-DISCHARGE
15
Patent #:
7835814
Issue Dt:
11/16/2010
Application #:
11839749
Filing Dt:
08/16/2007
Publication #:
US20090049345
Pub Dt:
02/19/2009
Title:
TOOL FOR REPORTING THE STATUS AND DRILL-DOWN OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT
16
Patent #:
7915162
Issue Dt:
03/29/2011
Application #:
11839767
Filing Dt:
08/16/2007
Publication #:
US20080096384
Pub Dt:
04/24/2008
Title:
METHOD OF FORMING DAMASCENE FILAMENT WIRES
17
Patent #:
7935637
Issue Dt:
05/03/2011
Application #:
11839934
Filing Dt:
08/16/2007
Publication #:
US20090047784
Pub Dt:
02/19/2009
Title:
RESIST STRIPPING METHODS USING BACKFILLING MATERIAL LAYER
18
Patent #:
7396747
Issue Dt:
07/08/2008
Application #:
11840029
Filing Dt:
08/16/2007
Publication #:
US20070278517
Pub Dt:
12/06/2007
Title:
HETERO-INTEGRATED STRAINED SILICON N- AND P- MOSFETS
19
Patent #:
7491623
Issue Dt:
02/17/2009
Application #:
11841018
Filing Dt:
08/20/2007
Publication #:
US20080057673
Pub Dt:
03/06/2008
Title:
METHOD OF MAKING A SEMICONDUCTOR STRUCTURE
20
Patent #:
7514361
Issue Dt:
04/07/2009
Application #:
11841114
Filing Dt:
08/20/2007
Publication #:
US20090053890
Pub Dt:
02/26/2009
Title:
SELECTIVE THIN METAL CAP PROCESS
21
Patent #:
7981749
Issue Dt:
07/19/2011
Application #:
11841161
Filing Dt:
08/20/2007
Publication #:
US20090050984
Pub Dt:
02/26/2009
Title:
MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME
22
Patent #:
7913103
Issue Dt:
03/22/2011
Application #:
11841179
Filing Dt:
08/31/2007
Publication #:
US20090063888
Pub Dt:
03/05/2009
Title:
METHOD AND APPARATUS FOR CLOCK CYCLE STEALING
23
Patent #:
8055822
Issue Dt:
11/08/2011
Application #:
11842206
Filing Dt:
08/21/2007
Publication #:
US20090055826
Pub Dt:
02/26/2009
Title:
MULTICORE PROCESSOR HAVING STORAGE FOR CORE-SPECIFIC OPERATIONAL DATA
24
Patent #:
7741658
Issue Dt:
06/22/2010
Application #:
11842437
Filing Dt:
08/21/2007
Publication #:
US20090050942
Pub Dt:
02/26/2009
Title:
SELF-ALIGNED SUPER STRESSED PFET
25
Patent #:
7957826
Issue Dt:
06/07/2011
Application #:
11842515
Filing Dt:
08/21/2007
Publication #:
US20090053627
Pub Dt:
02/26/2009
Title:
METHODS FOR NORMALIZING ERROR IN PHOTOLITHOGRAPHIC PROCESSES
26
Patent #:
7360188
Issue Dt:
04/15/2008
Application #:
11842533
Filing Dt:
08/21/2007
Publication #:
US20070288872
Pub Dt:
12/13/2007
Title:
METHOD AND APPARATUS FOR CHARACTERISTIC IMPEDANCE DISCONTINUITY REDUCTION IN HIGH-SPEED FLEXIBLE CIRCUIT APPLICATIONS
27
Patent #:
7763515
Issue Dt:
07/27/2010
Application #:
11843358
Filing Dt:
08/22/2007
Publication #:
US20080179628
Pub Dt:
07/31/2008
Title:
TRANSISTOR WITH EMBEDDED SILICON/GERMANIUM MATERIAL ON A STRAINED SEMICONDUCTOR ON INSULATOR SUBSTRATE
28
Patent #:
8006032
Issue Dt:
08/23/2011
Application #:
11843434
Filing Dt:
08/22/2007
Publication #:
US20090055572
Pub Dt:
02/26/2009
Title:
OPTIMAL SOLUTION TO CONTROL DATA CHANNELS
29
Patent #:
8095172
Issue Dt:
01/10/2012
Application #:
11843784
Filing Dt:
08/23/2007
Title:
CONNECTIVITY MANAGER TO MANAGE CONNECTIVITY SERVICES
30
Patent #:
7793167
Issue Dt:
09/07/2010
Application #:
11843791
Filing Dt:
08/23/2007
Publication #:
US20090055688
Pub Dt:
02/26/2009
Title:
DETECTION AND CORRECTION OF DROPPED WRITE ERRORS IN A DATA STORAGE SYSTEM
31
Patent #:
7960808
Issue Dt:
06/14/2011
Application #:
11844109
Filing Dt:
08/23/2007
Publication #:
US20070290233
Pub Dt:
12/20/2007
Title:
REPROGRAMMABLE FUSE STRUCTURE AND METHOD
32
Patent #:
8589832
Issue Dt:
11/19/2013
Application #:
11844397
Filing Dt:
08/24/2007
Publication #:
US20090052153
Pub Dt:
02/26/2009
Title:
ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE AND METHOD OF SHIELDING
33
Patent #:
7964081
Issue Dt:
06/21/2011
Application #:
11844587
Filing Dt:
08/24/2007
Publication #:
US20090050486
Pub Dt:
02/26/2009
Title:
ENHANCED MAGNETIC PLATING METHOD
34
Patent #:
7378542
Issue Dt:
05/27/2008
Application #:
11844831
Filing Dt:
08/24/2007
Publication #:
US20080033198
Pub Dt:
02/07/2008
Title:
PRECURSORS TO FLUOROALKANOL-CONTAINING OLEFIN MONOMERS, AND ASSOCIATED METHODS OF SYNTHESIS AND USE
35
Patent #:
7515489
Issue Dt:
04/07/2009
Application #:
11845386
Filing Dt:
08/27/2007
Publication #:
US20090059705
Pub Dt:
03/05/2009
Title:
SRAM HAVING ACTIVE WRITE ASSIST FOR IMPROVED OPERATIONAL MARGINS
36
Patent #:
8032851
Issue Dt:
10/04/2011
Application #:
11845852
Filing Dt:
08/28/2007
Publication #:
US20080184186
Pub Dt:
07/31/2008
Title:
A DESIGN STRUCTURE FOR AN INTEGRATED CIRCUIT DESIGN FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT
37
Patent #:
7446395
Issue Dt:
11/04/2008
Application #:
11845888
Filing Dt:
08/28/2007
Publication #:
US20070292696
Pub Dt:
12/20/2007
Title:
DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER
38
Patent #:
7633103
Issue Dt:
12/15/2009
Application #:
11846318
Filing Dt:
08/28/2007
Publication #:
US20090057729
Pub Dt:
03/05/2009
Title:
SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME
39
Patent #:
7763531
Issue Dt:
07/27/2010
Application #:
11846544
Filing Dt:
08/29/2007
Publication #:
US20070292996
Pub Dt:
12/20/2007
Title:
METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING
40
Patent #:
7831935
Issue Dt:
11/09/2010
Application #:
11846578
Filing Dt:
08/29/2007
Publication #:
US20080024197
Pub Dt:
01/31/2008
Title:
METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE
41
Patent #:
7382055
Issue Dt:
06/03/2008
Application #:
11846595
Filing Dt:
08/29/2007
Publication #:
US20070290272
Pub Dt:
12/20/2007
Title:
INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
42
Patent #:
7925614
Issue Dt:
04/12/2011
Application #:
11847203
Filing Dt:
08/29/2007
Publication #:
US20070295954
Pub Dt:
12/27/2007
Title:
METHOD AND STRUCTURE TO ISOLATE A QUBIT FROM THE ENVIRONMENT
43
Patent #:
7851885
Issue Dt:
12/14/2010
Application #:
11847379
Filing Dt:
08/30/2007
Publication #:
US20100237460
Pub Dt:
09/23/2010
Title:
METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES
44
Patent #:
7465649
Issue Dt:
12/16/2008
Application #:
11847384
Filing Dt:
08/30/2007
Publication #:
US20070293031
Pub Dt:
12/20/2007
Title:
A METHOD OF FORMING A SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK
45
Patent #:
7853443
Issue Dt:
12/14/2010
Application #:
11847391
Filing Dt:
08/30/2007
Publication #:
US20080004854
Pub Dt:
01/03/2008
Title:
TRANSIENT SIMULATION USING ADAPTIVE PIECEWISE CONSTANT MODEL
46
Patent #:
7429877
Issue Dt:
09/30/2008
Application #:
11848470
Filing Dt:
08/31/2007
Publication #:
US20080186054
Pub Dt:
08/07/2008
Title:
DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH
47
Patent #:
8039888
Issue Dt:
10/18/2011
Application #:
11848597
Filing Dt:
08/31/2007
Publication #:
US20080272398
Pub Dt:
11/06/2008
Title:
CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING
48
Patent #:
7885365
Issue Dt:
02/08/2011
Application #:
11848599
Filing Dt:
08/31/2007
Publication #:
US20090060091
Pub Dt:
03/05/2009
Title:
LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE
49
Patent #:
7592685
Issue Dt:
09/22/2009
Application #:
11849048
Filing Dt:
08/31/2007
Publication #:
US20080038915
Pub Dt:
02/14/2008
Title:
DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
50
Patent #:
7827514
Issue Dt:
11/02/2010
Application #:
11849346
Filing Dt:
09/03/2007
Publication #:
US20070300191
Pub Dt:
12/27/2007
Title:
EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES
51
Patent #:
7843069
Issue Dt:
11/30/2010
Application #:
11849409
Filing Dt:
09/04/2007
Publication #:
US20090057908
Pub Dt:
03/05/2009
Title:
WIRE BOND PADS
52
Patent #:
7984329
Issue Dt:
07/19/2011
Application #:
11849452
Filing Dt:
09/04/2007
Publication #:
US20090063896
Pub Dt:
03/05/2009
Title:
SYSTEM AND METHOD FOR PROVIDING DRAM DEVICE-LEVEL REPAIR VIA ADDRESS REMAPPINGS EXTERNAL TO THE DEVICE
53
Patent #:
7710137
Issue Dt:
05/04/2010
Application #:
11849702
Filing Dt:
09/04/2007
Publication #:
US20090058444
Pub Dt:
03/05/2009
Title:
METHOD AND APPARATUS FOR RELATIVE TESTING OF INTEGRATED CIRCUIT DEVICES
54
Patent #:
7784012
Issue Dt:
08/24/2010
Application #:
11849908
Filing Dt:
09/04/2007
Publication #:
US20080010626
Pub Dt:
01/10/2008
Title:
SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR USE IN CIRCUIT DESIGNS
55
Patent #:
7816219
Issue Dt:
10/19/2010
Application #:
11850076
Filing Dt:
09/05/2007
Publication #:
US20070298572
Pub Dt:
12/27/2007
Title:
FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE AND/OR STAIRCASE SILICIDE
56
Patent #:
7825000
Issue Dt:
11/02/2010
Application #:
11850427
Filing Dt:
09/05/2007
Publication #:
US20090059656
Pub Dt:
03/05/2009
Title:
METHOD FOR INTEGRATION OF MAGNETIC RANDOM ACCESS MEMORIES WITH IMPROVED LITHOGRAPHIC ALIGNMENT TO MAGNETIC TUNNEL JUNCTIONS
57
Patent #:
7825469
Issue Dt:
11/02/2010
Application #:
11850488
Filing Dt:
09/05/2007
Publication #:
US20090057804
Pub Dt:
03/05/2009
Title:
THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS
58
Patent #:
7795677
Issue Dt:
09/14/2010
Application #:
11850608
Filing Dt:
09/05/2007
Publication #:
US20090057762
Pub Dt:
03/05/2009
Title:
NANOWIRE FIELD-EFFECT TRANSISTORS
59
Patent #:
7534675
Issue Dt:
05/19/2009
Application #:
11850644
Filing Dt:
09/05/2007
Publication #:
US20090061568
Pub Dt:
03/05/2009
Title:
TECHNIQUES FOR FABRICATING NANOWIRE FIELD-EFFECT TRANSISTORS
60
Patent #:
7633079
Issue Dt:
12/15/2009
Application #:
11850742
Filing Dt:
09/06/2007
Publication #:
US20090065761
Pub Dt:
03/12/2009
Title:
PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL
61
Patent #:
7464217
Issue Dt:
12/09/2008
Application #:
11850840
Filing Dt:
09/06/2007
Publication #:
US20080055956
Pub Dt:
03/06/2008
Title:
DESIGN STRUCTURE FOR CONTENT ADDRESSABLE MEMORY
62
Patent #:
7884018
Issue Dt:
02/08/2011
Application #:
11850916
Filing Dt:
09/06/2007
Publication #:
US20080315429
Pub Dt:
12/25/2008
Title:
METHOD FOR IMPROVING THE SELECTIVITY OF A CVD PROCESS
63
Patent #:
7928571
Issue Dt:
04/19/2011
Application #:
11850968
Filing Dt:
09/06/2007
Publication #:
US20070296044
Pub Dt:
12/27/2007
Title:
DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS
64
Patent #:
7892940
Issue Dt:
02/22/2011
Application #:
11851123
Filing Dt:
09/06/2007
Publication #:
US20080038923
Pub Dt:
02/14/2008
Title:
DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
65
Patent #:
7904658
Issue Dt:
03/08/2011
Application #:
11851128
Filing Dt:
09/06/2007
Publication #:
US20080040547
Pub Dt:
02/14/2008
Title:
STRUCTURE FOR POWER-EFFICIENT CACHE MEMORY
66
Patent #:
7839206
Issue Dt:
11/23/2010
Application #:
11851138
Filing Dt:
09/06/2007
Publication #:
US20080169867
Pub Dt:
07/17/2008
Title:
DESIGN STRUCTURE FOR LOW VOLTAGE APPLICATIONS IN AN INTEGRATED CIRCUIT
67
Patent #:
7569489
Issue Dt:
08/04/2009
Application #:
11851464
Filing Dt:
09/07/2007
Publication #:
US20070298552
Pub Dt:
12/27/2007
Title:
HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING
68
Patent #:
8053810
Issue Dt:
11/08/2011
Application #:
11851858
Filing Dt:
09/07/2007
Publication #:
US20090067463
Pub Dt:
03/12/2009
Title:
STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME
69
Patent #:
7713789
Issue Dt:
05/11/2010
Application #:
11852317
Filing Dt:
09/09/2007
Publication #:
US20080017978
Pub Dt:
01/24/2008
Title:
SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY
70
Patent #:
7939823
Issue Dt:
05/10/2011
Application #:
11852353
Filing Dt:
09/10/2007
Publication #:
US20090065955
Pub Dt:
03/12/2009
Title:
METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING
71
Patent #:
7989229
Issue Dt:
08/02/2011
Application #:
11852493
Filing Dt:
09/10/2007
Publication #:
US20090068770
Pub Dt:
03/12/2009
Title:
TACTILE SURFACE INSPECTION DURING DEVICE FABRICATION OR ASSEMBLY
72
Patent #:
7919379
Issue Dt:
04/05/2011
Application #:
11852906
Filing Dt:
09/10/2007
Publication #:
US20090065817
Pub Dt:
03/12/2009
Title:
DIELECTRIC SPACER REMOVAL
73
Patent #:
7388261
Issue Dt:
06/17/2008
Application #:
11853040
Filing Dt:
09/11/2007
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Title:
DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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