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03/13/2012
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12169668
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07/09/2008
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10/30/2008
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08/24/2010
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12169674
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07/09/2008
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10/30/2008
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01/17/2012
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12169991
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07/09/2008
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11/27/2008
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07/31/2012
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12170462
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07/10/2008
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01/14/2010
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06/12/2012
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12170634
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07/10/2008
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11/20/2008
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ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST
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08/30/2011
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12170988
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07/10/2008
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01/14/2010
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GRID-BASED FRAGMENTATION FOR OPTICAL PROXIMITY CORRECTION IN PHOTOLITHOGRAPHY MASK APPLICATIONS
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03/22/2011
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12171602
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07/11/2008
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11/06/2008
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ELECTRICALLY OPTIMIZED AND STRUCTURALLY PROTECTED VIA STRUCTURE FOR HIGH SPEED SIGNALS
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12/27/2011
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12172233
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07/12/2008
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01/14/2010
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05/17/2011
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12172300
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07/14/2008
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10/30/2008
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01/28/2014
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07/14/2008
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01/14/2010
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WAFER SCALE MEMBRANE FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION
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07/05/2011
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12172557
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07/14/2008
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11/06/2008
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01/31/2012
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07/14/2008
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01/14/2010
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TRANSMISSION ELECTRON MICROSCOPY SAMPLE ETCHING FIXTURE
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12/28/2010
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12173070
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07/15/2008
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12/04/2008
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A METHOD OF CREATING A LOAD BALANCED SPATIAL PARTITIONING OF A STRUCTURED, DIFFUSING SYSTEM OF PARTICLES
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07/10/2012
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12173093
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07/15/2008
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11/06/2008
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PROCESSOR DEDICATED CODE HANDLING IN A MULTI-PROCESSOR ENVIRONMENT
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04/14/2009
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12173280
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07/15/2008
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03/02/2010
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12173346
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07/15/2008
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11/06/2008
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CONDUCTIVE BONDING MATERIAL FILL TECHNIQUES
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08/31/2010
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12173407
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07/15/2008
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01/21/2010
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INTEGRATED CIRCUITS COMPRISING RESISTORS HAVING DIFFERENT SHEET RESISTANCES AND METHODS OF FABRICATING THE SAME
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04/20/2010
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12173642
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07/15/2008
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11/20/2008
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METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES
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03/01/2011
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12173651
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07/15/2008
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01/21/2010
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SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING
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03/25/2014
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12173803
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07/15/2008
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11/27/2008
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PREVENTION AND CONTROL OF INTERMETALLIC ALLOY INCLUSIONS
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01/31/2012
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12173899
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07/16/2008
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01/22/2009
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METHODS FOR FORMING DIELECTRIC INTERCONNECT STRUCTURES
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01/11/2011
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12174074
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07/16/2008
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11/06/2008
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STRUCTURE AND METHOD FOR ENHANCING RESISTANCE TO FRACTURE OF BONDING PADS
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08/30/2011
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12174264
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07/16/2008
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01/21/2010
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PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY
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08/30/2011
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12174289
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07/16/2008
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01/21/2010
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PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY
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09/27/2011
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12174407
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07/16/2008
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01/21/2010
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CONSTRUCTING A COMPREHENSIVE SUMMARY OF AN EVENT SEQUENCE
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09/07/2010
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12174497
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07/16/2008
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01/21/2010
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METHODS FOR REMOVING A METAL-COMPRISING MATERIAL FROM A SEMICONDUCTOR SUBSTRATE
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12/27/2011
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12174572
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07/16/2008
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06/25/2009
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DESIGN STRUCTURE FOR GLITCHLESS CLOCK MULTIPLEXER OPTIMIZED FOR SYNCHRONOUS AND ASYNCHRONOUS CLOCKS
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11/16/2010
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12174683
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07/17/2008
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11/06/2008
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METHOD AND STRUCTURE TO REDUCE CONTACT RESISTANCE ON THIN SILICON-ON-INSULATOR DEVICE
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02/15/2011
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12174707
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07/17/2008
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11/06/2008
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COMPUTER PROGRAM PRODUCT FOR DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY
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10/05/2010
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12174770
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07/17/2008
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11/06/2008
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SYSTEM AND PROCESS FOR SUPPLY MANAGEMENT FOR THE ASSEMBLY OF EXPENSIVE PRODUCTS
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06/07/2011
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12174994
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07/17/2008
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01/21/2010
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CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME
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09/11/2012
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12175012
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07/17/2008
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01/21/2010
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METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM
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12/25/2012
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12175018
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07/17/2008
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01/21/2010
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MONITORING A PROCESS SECTOR IN A PRODUCTION FACILITY
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06/14/2011
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12175097
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07/17/2008
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12/04/2008
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SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION
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04/06/2010
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12175214
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07/17/2008
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01/21/2010
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METHOD AND APPARATUS FOR DATA DECOMPRESSION IN THE PRESENCE OF MEMORY HIERARCHIES
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10/12/2010
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12175528
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07/18/2008
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12/04/2008
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DUAL WORK-FUNCTION SINGLE GATE STACK
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03/29/2011
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12175534
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07/18/2008
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07/16/2009
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DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA
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01/25/2011
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12175576
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07/18/2008
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01/15/2009
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REMOVAL OF RELATIVELY UNIMPORTANT SHAPES FROM A SET OF SHAPES
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04/05/2011
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12176375
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07/19/2008
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12/04/2008
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MANAGING A PLURALITY OF PROCESSORS AS DEVICES
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04/12/2011
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12176530
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07/21/2008
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10/01/2009
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OPTIMIZATION METHOD FOR FRACTIONAL-N PHASED-LOCK-LOOP (PLL) SYSTEM
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12/27/2011
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12176536
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07/21/2008
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10/01/2009
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DESIGN STRUCTURE FOR FRACTIONAL-N PHASED-LOCK-LOOP (PLL) SYSTEM
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03/22/2011
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12176543
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07/21/2008
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01/21/2010
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REGULATING ELECTRICAL FUSE PROGRAMMING CURRENT
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05/10/2011
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12176835
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07/21/2008
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01/21/2010
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TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD
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08/16/2011
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12176975
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07/21/2008
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11/06/2008
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APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING VIAS AS RADIATING ELEMENTS FORMED IN A SUBSTRATE
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07/03/2012
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12177020
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07/21/2008
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01/21/2010
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STRUCTURE AND APPARATUS FOR COOLING INTEGRATED CIRCUITS USING COPPER MICROCHANNELS
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04/19/2011
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12177194
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07/22/2008
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01/28/2010
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SEGMENTATION OF A DIE STACK FOR 3D PACKAGING THERMAL MANAGEMENT
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06/14/2011
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12177231
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07/22/2008
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12/04/2008
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DATA-DEPENDENT JITTER PRE-EMPHASIS FOR HIGH-SPEED SERIAL LINK TRANSMITTERS
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08/21/2012
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12177252
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07/22/2008
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11/13/2008
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RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION
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07/23/2013
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12177300
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07/22/2008
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03/19/2009
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RESOURCE ADAPTIVE SPECTRUM ESTIMATION OF STREAMING DATA
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08/23/2011
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12177309
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07/22/2008
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06/18/2009
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PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT
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06/14/2011
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12177379
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07/22/2008
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04/02/2009
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SYSTEMS AND METHODS FOR CORRELATION OF BURST EVENTS AMONG DATA STREAMS
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04/26/2011
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12177533
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07/22/2008
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01/28/2010
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FULLY SELF-ALIGNED PORE-TYPE MEMORY CELL HAVING DIODE ACCESS DEVICE
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02/28/2012
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12177690
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07/22/2008
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01/28/2010
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MULTIPLE EXPOSURE AND SINGLE ETCH INTEGRATION METHOD
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11/16/2010
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12178303
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07/23/2008
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Pub Dt:
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01/28/2010
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SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING OXYGEN DIFFUSION BARRIER LAYER BETWEEN BURIED OXIDE LAYER AND HIGH K DIELECTRIC LAYER
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06/08/2010
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12178921
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07/24/2008
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03/19/2009
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PROGRAMMABLE VIA STRUCTURE FOR THREE DIMENSIONAL INTEGRATION TECHNOLOGY
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03/15/2011
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12179116
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07/24/2008
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08/06/2009
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METHOD FOR SELECTIVELY FORMING STRAIN IN A TRANSISTOR BY A STRESS MEMORIZATION TECHNIQUE WITHOUT ADDING ADDITIONAL LITHOGRAPHY STEPS
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09/20/2011
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12179846
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07/25/2008
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Pub Dt:
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03/19/2009
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Title:
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A FILM HAVING ALTERNATING MONOLAYERS OF A METAL-METAL BONDED COMPLEX MONOLAYER AND AN ORGANIC MONOLAYER BY LAYER-BY-LAYER GROWTH
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12180010
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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11/13/2008
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Title:
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ELECTRONIC STRUCTURES UTILIZING ETCH RESISTANT BORON AND PHOSPHORUS MATERIALS AND METHODS TO FORM SAME
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12180586
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Filing Dt:
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07/28/2008
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Publication #:
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Pub Dt:
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11/13/2008
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Title:
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INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12180927
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Filing Dt:
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07/28/2008
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Publication #:
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Pub Dt:
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12/04/2008
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Title:
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BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH K GATE DIELECTRICS
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Patent #:
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Issue Dt:
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12/07/2010
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Application #:
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12180989
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Filing Dt:
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07/28/2008
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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METHOD AND APPARATUS FOR NANO PROBING A SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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12181007
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Filing Dt:
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07/28/2008
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Publication #:
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Pub Dt:
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11/05/2009
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Title:
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CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES
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Patent #:
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Issue Dt:
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03/01/2011
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Application #:
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12181335
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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METHOD OF MANUFACTURING A DUAL CONTACT TRENCH CAPACITOR.
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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12181341
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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DESIGN STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEREOF
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Patent #:
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Issue Dt:
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06/12/2012
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Application #:
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12181343
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEREOF
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12181374
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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VIA STRUCTURE TO IMPROVE ROUTING OF WIRES WITHIN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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12181506
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Filing Dt:
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07/29/2008
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Title:
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LOW POWER TO ANALOG TO DIGITAL CONVERTER WITH SMALL INPUT CAPACITANCE
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Patent #:
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Issue Dt:
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12/21/2010
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Application #:
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12181843
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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11/27/2008
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Title:
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FACILITATING SIMULATION OF A MODEL WITHIN A DISTRIBUTED ENVIRONMENT
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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12181852
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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METHOD AND APPARATUS FOR FORMING PLANAR ALLOY DEPOSITS ON A SUBSTRATE
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Patent #:
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Issue Dt:
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12/14/2010
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Application #:
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12182158
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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11/20/2008
| | | | |
Title:
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FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS
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Patent #:
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Issue Dt:
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08/21/2012
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Application #:
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12182211
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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03/05/2009
| | | | |
Title:
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VERIFYING A PROCESSOR DESIGN USING A PROCESSOR SIMULATION MODEL
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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12182212
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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11/20/2008
| | | | |
Title:
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SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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12182282
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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11/20/2008
| | | | |
Title:
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REDUCING CONTAMINATION IN IMMERSION LITHOGRAPHY
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12182411
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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PERSISTENT CURRENT SWITCH
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12182585
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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BACK-END-OF-LINE WIRING STRUCTURES WITH INTEGRATED PASSIVE ELEMENTS AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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12182672
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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SYSTEMS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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12183099
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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ADAPTIVE NOISE SUPPRESSION USING A NOISE LOOK-UP TABLE
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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12183166
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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12/18/2008
| | | | |
Title:
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RIBONUCLEIC ACID INTERFERENCE MOLECULES OF ARABIDOPSIS THALIANA
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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12183169
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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11/20/2008
| | | | |
Title:
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FIN-TYPE ANTIFUSE
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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12183204
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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12/18/2008
| | | | |
Title:
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RIBONUCLEIC ACID INTERFERENCE MOLECULES OF ORYZA SATIVA
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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12183313
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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VIA DENSITY CHANGE TO IMPROVE WAFER SURFACE PLANARITY
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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12183462
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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06/15/2010
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Application #:
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12183533
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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12/04/2008
| | | | |
Title:
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DYNAMIC MEMORY ALLOCATION BETWEEN INBOUND AND OUTBOUND BUFFERS IN A PROTOCOL HANDLER
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12183549
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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12/18/2008
| | | | |
Title:
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METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12183578
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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12/18/2008
| | | | |
Title:
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VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GRID CONSTRAINTS
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Patent #:
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Issue Dt:
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09/27/2011
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Application #:
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12183898
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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SYSTEM AND METHOD FOR IMPROVED PLACEMENT IN CUSTOM VLSI CIRCUIT DESIGN WITH SCHEMATIC-DRIVEN PLACEMENT
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Patent #:
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Issue Dt:
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09/27/2011
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Application #:
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12183958
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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SYSTEM AND METHOD FOR AUTOMATED PLACEMENT IN CUSTOM VLSI CIRCUIT DESIGN WITH SCHEMATIC-DRIVEN PLACEMENT
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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12184148
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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BIAS CIRCUIT FOR A MOS DEVICE
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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12184421
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Filing Dt:
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08/01/2008
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Publication #:
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Pub Dt:
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11/27/2008
| | | | |
Title:
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SYSTEM AND METHOD FOR PROBLEM DETERMINATION USING DEPENDENCY GRAPHS AND RUN-TIME BEHAVIOR MODELS
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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12185095
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Filing Dt:
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08/03/2008
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Publication #:
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Pub Dt:
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01/29/2009
| | | | |
Title:
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HIGH-RATE RLL ENCODING
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Patent #:
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Issue Dt:
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09/29/2009
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Application #:
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12185172
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Filing Dt:
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08/04/2008
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Publication #:
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Pub Dt:
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12/18/2008
| | | | |
Title:
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ON-CHIP AC SELF-TEST CONTROLLER
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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12185259
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Filing Dt:
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08/04/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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METAL ADHESION BY INDUCED SURFACE ROUGHNESS
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Patent #:
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Issue Dt:
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04/28/2015
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Application #:
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12185339
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Filing Dt:
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08/04/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
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Patent #:
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Issue Dt:
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05/01/2012
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Application #:
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12185759
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Filing Dt:
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08/04/2008
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Publication #:
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Pub Dt:
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11/27/2008
| | | | |
Title:
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DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12186061
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Filing Dt:
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08/05/2008
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
Title:
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IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD
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Patent #:
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Issue Dt:
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10/29/2013
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Application #:
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12186075
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Filing Dt:
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08/05/2008
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Publication #:
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Pub Dt:
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11/20/2008
| | | | |
Title:
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CMOS GATE STRUCTURES FABRICATED BY SELECTIVE OXIDATION
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12186588
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Filing Dt:
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08/06/2008
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
Title:
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ROBUST JITTER-FREE REMOTE CLOCK OFFSET MEASURING METHOD
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Patent #:
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Issue Dt:
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03/03/2015
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Application #:
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12186630
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Filing Dt:
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08/06/2008
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Publication #:
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Pub Dt:
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08/06/2009
| | | | |
Title:
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ESD POWER CLAMP WITH STABLE POWER START UP FUNCTION
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12186655
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Filing Dt:
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08/06/2008
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Publication #:
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Pub Dt:
|
03/12/2009
| | | | |
Title:
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DUAL-SIDED CHIP ATTACHED MODULES
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Patent #:
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Issue Dt:
|
05/03/2011
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Application #:
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12186750
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Filing Dt:
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08/06/2008
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
Title:
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METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING RADIATION HARDENED INSULATORS
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