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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
03/13/2012
Application #:
12169668
Filing Dt:
07/09/2008
Publication #:
Pub Dt:
10/30/2008
Title:
AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS
2
Patent #:
Issue Dt:
08/24/2010
Application #:
12169674
Filing Dt:
07/09/2008
Publication #:
Pub Dt:
10/30/2008
Title:
EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER
3
Patent #:
Issue Dt:
01/17/2012
Application #:
12169991
Filing Dt:
07/09/2008
Publication #:
Pub Dt:
11/27/2008
Title:
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
4
Patent #:
Issue Dt:
07/31/2012
Application #:
12170462
Filing Dt:
07/10/2008
Publication #:
Pub Dt:
01/14/2010
Title:
SOFT ERROR CORRECTION IN SLEEPING PROCESSORS
5
Patent #:
Issue Dt:
06/12/2012
Application #:
12170634
Filing Dt:
07/10/2008
Publication #:
Pub Dt:
11/20/2008
Title:
ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST
6
Patent #:
Issue Dt:
08/30/2011
Application #:
12170988
Filing Dt:
07/10/2008
Publication #:
Pub Dt:
01/14/2010
Title:
GRID-BASED FRAGMENTATION FOR OPTICAL PROXIMITY CORRECTION IN PHOTOLITHOGRAPHY MASK APPLICATIONS
7
Patent #:
Issue Dt:
03/22/2011
Application #:
12171602
Filing Dt:
07/11/2008
Publication #:
Pub Dt:
11/06/2008
Title:
ELECTRICALLY OPTIMIZED AND STRUCTURALLY PROTECTED VIA STRUCTURE FOR HIGH SPEED SIGNALS
8
Patent #:
Issue Dt:
12/27/2011
Application #:
12172233
Filing Dt:
07/12/2008
Publication #:
Pub Dt:
01/14/2010
Title:
SELF-SEGREGATING MULTILAYER IMAGING STACK WITH BUILT-IN ANTIREFLECTIVE PROPERTIES
9
Patent #:
Issue Dt:
05/17/2011
Application #:
12172300
Filing Dt:
07/14/2008
Publication #:
Pub Dt:
10/30/2008
Title:
APPARATUS, AND COMPUTER PROGRAM FOR IMPLEMENTING VERTICALLY COUPLED NOISE CONTROL THROUGH A MESH PLANE IN AN ELECTRONIC PACKAGE DESIGN
10
Patent #:
Issue Dt:
01/28/2014
Application #:
12172452
Filing Dt:
07/14/2008
Publication #:
Pub Dt:
01/14/2010
Title:
WAFER SCALE MEMBRANE FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION
11
Patent #:
Issue Dt:
07/05/2011
Application #:
12172557
Filing Dt:
07/14/2008
Publication #:
Pub Dt:
11/06/2008
Title:
METHOD AND SYSTEM FOR CREATING AN IN-MEMORY PHYSICAL DICTIONARY FOR DATA COMPRESSION
12
Patent #:
Issue Dt:
01/31/2012
Application #:
12172876
Filing Dt:
07/14/2008
Publication #:
Pub Dt:
01/14/2010
Title:
TRANSMISSION ELECTRON MICROSCOPY SAMPLE ETCHING FIXTURE
13
Patent #:
Issue Dt:
12/28/2010
Application #:
12173070
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
12/04/2008
Title:
A METHOD OF CREATING A LOAD BALANCED SPATIAL PARTITIONING OF A STRUCTURED, DIFFUSING SYSTEM OF PARTICLES
14
Patent #:
Issue Dt:
07/10/2012
Application #:
12173093
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
11/06/2008
Title:
PROCESSOR DEDICATED CODE HANDLING IN A MULTI-PROCESSOR ENVIRONMENT
15
Patent #:
Issue Dt:
04/14/2009
Application #:
12173280
Filing Dt:
07/15/2008
Title:
SILICON ON INSULATOR DEVICES HAVING BODY-TIED-TO-SOURCE AND METHODS OF MAKING
16
Patent #:
Issue Dt:
03/02/2010
Application #:
12173346
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
11/06/2008
Title:
CONDUCTIVE BONDING MATERIAL FILL TECHNIQUES
17
Patent #:
Issue Dt:
08/31/2010
Application #:
12173407
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
01/21/2010
Title:
INTEGRATED CIRCUITS COMPRISING RESISTORS HAVING DIFFERENT SHEET RESISTANCES AND METHODS OF FABRICATING THE SAME
18
Patent #:
Issue Dt:
04/20/2010
Application #:
12173642
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
11/20/2008
Title:
METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES
19
Patent #:
Issue Dt:
03/01/2011
Application #:
12173651
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
01/21/2010
Title:
SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING
20
Patent #:
Issue Dt:
03/25/2014
Application #:
12173803
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
11/27/2008
Title:
PREVENTION AND CONTROL OF INTERMETALLIC ALLOY INCLUSIONS
21
Patent #:
Issue Dt:
01/31/2012
Application #:
12173899
Filing Dt:
07/16/2008
Publication #:
Pub Dt:
01/22/2009
Title:
METHODS FOR FORMING DIELECTRIC INTERCONNECT STRUCTURES
22
Patent #:
Issue Dt:
01/11/2011
Application #:
12174074
Filing Dt:
07/16/2008
Publication #:
Pub Dt:
11/06/2008
Title:
STRUCTURE AND METHOD FOR ENHANCING RESISTANCE TO FRACTURE OF BONDING PADS
23
Patent #:
Issue Dt:
08/30/2011
Application #:
12174264
Filing Dt:
07/16/2008
Publication #:
Pub Dt:
01/21/2010
Title:
PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY
24
Patent #:
Issue Dt:
08/30/2011
Application #:
12174289
Filing Dt:
07/16/2008
Publication #:
Pub Dt:
01/21/2010
Title:
PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY
25
Patent #:
Issue Dt:
09/27/2011
Application #:
12174407
Filing Dt:
07/16/2008
Publication #:
Pub Dt:
01/21/2010
Title:
CONSTRUCTING A COMPREHENSIVE SUMMARY OF AN EVENT SEQUENCE
26
Patent #:
Issue Dt:
09/07/2010
Application #:
12174497
Filing Dt:
07/16/2008
Publication #:
Pub Dt:
01/21/2010
Title:
METHODS FOR REMOVING A METAL-COMPRISING MATERIAL FROM A SEMICONDUCTOR SUBSTRATE
27
Patent #:
Issue Dt:
12/27/2011
Application #:
12174572
Filing Dt:
07/16/2008
Publication #:
Pub Dt:
06/25/2009
Title:
DESIGN STRUCTURE FOR GLITCHLESS CLOCK MULTIPLEXER OPTIMIZED FOR SYNCHRONOUS AND ASYNCHRONOUS CLOCKS
28
Patent #:
Issue Dt:
11/16/2010
Application #:
12174683
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
11/06/2008
Title:
METHOD AND STRUCTURE TO REDUCE CONTACT RESISTANCE ON THIN SILICON-ON-INSULATOR DEVICE
29
Patent #:
Issue Dt:
02/15/2011
Application #:
12174707
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
11/06/2008
Title:
COMPUTER PROGRAM PRODUCT FOR DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY
30
Patent #:
Issue Dt:
10/05/2010
Application #:
12174770
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
11/06/2008
Title:
SYSTEM AND PROCESS FOR SUPPLY MANAGEMENT FOR THE ASSEMBLY OF EXPENSIVE PRODUCTS
31
Patent #:
Issue Dt:
06/07/2011
Application #:
12174994
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
01/21/2010
Title:
CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME
32
Patent #:
Issue Dt:
09/11/2012
Application #:
12175012
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
01/21/2010
Title:
METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM
33
Patent #:
Issue Dt:
12/25/2012
Application #:
12175018
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
01/21/2010
Title:
MONITORING A PROCESS SECTOR IN A PRODUCTION FACILITY
34
Patent #:
Issue Dt:
06/14/2011
Application #:
12175097
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
12/04/2008
Title:
SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION
35
Patent #:
Issue Dt:
04/06/2010
Application #:
12175214
Filing Dt:
07/17/2008
Publication #:
Pub Dt:
01/21/2010
Title:
METHOD AND APPARATUS FOR DATA DECOMPRESSION IN THE PRESENCE OF MEMORY HIERARCHIES
36
Patent #:
Issue Dt:
10/12/2010
Application #:
12175528
Filing Dt:
07/18/2008
Publication #:
Pub Dt:
12/04/2008
Title:
DUAL WORK-FUNCTION SINGLE GATE STACK
37
Patent #:
Issue Dt:
03/29/2011
Application #:
12175534
Filing Dt:
07/18/2008
Publication #:
Pub Dt:
07/16/2009
Title:
DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA
38
Patent #:
Issue Dt:
01/25/2011
Application #:
12175576
Filing Dt:
07/18/2008
Publication #:
Pub Dt:
01/15/2009
Title:
REMOVAL OF RELATIVELY UNIMPORTANT SHAPES FROM A SET OF SHAPES
39
Patent #:
Issue Dt:
04/05/2011
Application #:
12176375
Filing Dt:
07/19/2008
Publication #:
Pub Dt:
12/04/2008
Title:
MANAGING A PLURALITY OF PROCESSORS AS DEVICES
40
Patent #:
Issue Dt:
04/12/2011
Application #:
12176530
Filing Dt:
07/21/2008
Publication #:
Pub Dt:
10/01/2009
Title:
OPTIMIZATION METHOD FOR FRACTIONAL-N PHASED-LOCK-LOOP (PLL) SYSTEM
41
Patent #:
Issue Dt:
12/27/2011
Application #:
12176536
Filing Dt:
07/21/2008
Publication #:
Pub Dt:
10/01/2009
Title:
DESIGN STRUCTURE FOR FRACTIONAL-N PHASED-LOCK-LOOP (PLL) SYSTEM
42
Patent #:
Issue Dt:
03/22/2011
Application #:
12176543
Filing Dt:
07/21/2008
Publication #:
Pub Dt:
01/21/2010
Title:
REGULATING ELECTRICAL FUSE PROGRAMMING CURRENT
43
Patent #:
Issue Dt:
05/10/2011
Application #:
12176835
Filing Dt:
07/21/2008
Publication #:
Pub Dt:
01/21/2010
Title:
TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD
44
Patent #:
Issue Dt:
08/16/2011
Application #:
12176975
Filing Dt:
07/21/2008
Publication #:
Pub Dt:
11/06/2008
Title:
APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING VIAS AS RADIATING ELEMENTS FORMED IN A SUBSTRATE
45
Patent #:
Issue Dt:
07/03/2012
Application #:
12177020
Filing Dt:
07/21/2008
Publication #:
Pub Dt:
01/21/2010
Title:
STRUCTURE AND APPARATUS FOR COOLING INTEGRATED CIRCUITS USING COPPER MICROCHANNELS
46
Patent #:
Issue Dt:
04/19/2011
Application #:
12177194
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
01/28/2010
Title:
SEGMENTATION OF A DIE STACK FOR 3D PACKAGING THERMAL MANAGEMENT
47
Patent #:
Issue Dt:
06/14/2011
Application #:
12177231
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
12/04/2008
Title:
DATA-DEPENDENT JITTER PRE-EMPHASIS FOR HIGH-SPEED SERIAL LINK TRANSMITTERS
48
Patent #:
Issue Dt:
08/21/2012
Application #:
12177252
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
11/13/2008
Title:
RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION
49
Patent #:
Issue Dt:
07/23/2013
Application #:
12177300
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
03/19/2009
Title:
RESOURCE ADAPTIVE SPECTRUM ESTIMATION OF STREAMING DATA
50
Patent #:
Issue Dt:
08/23/2011
Application #:
12177309
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
06/18/2009
Title:
PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT
51
Patent #:
Issue Dt:
06/14/2011
Application #:
12177379
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
04/02/2009
Title:
SYSTEMS AND METHODS FOR CORRELATION OF BURST EVENTS AMONG DATA STREAMS
52
Patent #:
Issue Dt:
04/26/2011
Application #:
12177533
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
01/28/2010
Title:
FULLY SELF-ALIGNED PORE-TYPE MEMORY CELL HAVING DIODE ACCESS DEVICE
53
Patent #:
Issue Dt:
02/28/2012
Application #:
12177690
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
01/28/2010
Title:
MULTIPLE EXPOSURE AND SINGLE ETCH INTEGRATION METHOD
54
Patent #:
Issue Dt:
11/16/2010
Application #:
12178303
Filing Dt:
07/23/2008
Publication #:
Pub Dt:
01/28/2010
Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING OXYGEN DIFFUSION BARRIER LAYER BETWEEN BURIED OXIDE LAYER AND HIGH K DIELECTRIC LAYER
55
Patent #:
Issue Dt:
06/08/2010
Application #:
12178921
Filing Dt:
07/24/2008
Publication #:
Pub Dt:
03/19/2009
Title:
PROGRAMMABLE VIA STRUCTURE FOR THREE DIMENSIONAL INTEGRATION TECHNOLOGY
56
Patent #:
Issue Dt:
03/15/2011
Application #:
12179116
Filing Dt:
07/24/2008
Publication #:
Pub Dt:
08/06/2009
Title:
METHOD FOR SELECTIVELY FORMING STRAIN IN A TRANSISTOR BY A STRESS MEMORIZATION TECHNIQUE WITHOUT ADDING ADDITIONAL LITHOGRAPHY STEPS
57
Patent #:
Issue Dt:
09/20/2011
Application #:
12179846
Filing Dt:
07/25/2008
Publication #:
Pub Dt:
03/19/2009
Title:
A FILM HAVING ALTERNATING MONOLAYERS OF A METAL-METAL BONDED COMPLEX MONOLAYER AND AN ORGANIC MONOLAYER BY LAYER-BY-LAYER GROWTH
58
Patent #:
Issue Dt:
01/04/2011
Application #:
12180010
Filing Dt:
07/25/2008
Publication #:
Pub Dt:
11/13/2008
Title:
ELECTRONIC STRUCTURES UTILIZING ETCH RESISTANT BORON AND PHOSPHORUS MATERIALS AND METHODS TO FORM SAME
59
Patent #:
Issue Dt:
04/05/2011
Application #:
12180586
Filing Dt:
07/28/2008
Publication #:
Pub Dt:
11/13/2008
Title:
INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES
60
Patent #:
Issue Dt:
06/21/2011
Application #:
12180927
Filing Dt:
07/28/2008
Publication #:
Pub Dt:
12/04/2008
Title:
BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH K GATE DIELECTRICS
61
Patent #:
Issue Dt:
12/07/2010
Application #:
12180989
Filing Dt:
07/28/2008
Publication #:
Pub Dt:
01/28/2010
Title:
METHOD AND APPARATUS FOR NANO PROBING A SEMICONDUCTOR CHIP
62
Patent #:
Issue Dt:
01/10/2012
Application #:
12181007
Filing Dt:
07/28/2008
Publication #:
Pub Dt:
11/05/2009
Title:
CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES
63
Patent #:
Issue Dt:
03/01/2011
Application #:
12181335
Filing Dt:
07/29/2008
Publication #:
Pub Dt:
02/04/2010
Title:
METHOD OF MANUFACTURING A DUAL CONTACT TRENCH CAPACITOR.
64
Patent #:
Issue Dt:
02/26/2013
Application #:
12181341
Filing Dt:
07/29/2008
Publication #:
Pub Dt:
02/04/2010
Title:
DESIGN STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEREOF
65
Patent #:
Issue Dt:
06/12/2012
Application #:
12181343
Filing Dt:
07/29/2008
Publication #:
Pub Dt:
02/04/2010
Title:
STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEREOF
66
Patent #:
Issue Dt:
06/14/2011
Application #:
12181374
Filing Dt:
07/29/2008
Publication #:
Pub Dt:
02/04/2010
Title:
VIA STRUCTURE TO IMPROVE ROUTING OF WIRES WITHIN AN INTEGRATED CIRCUIT
67
Patent #:
Issue Dt:
02/17/2009
Application #:
12181506
Filing Dt:
07/29/2008
Title:
LOW POWER TO ANALOG TO DIGITAL CONVERTER WITH SMALL INPUT CAPACITANCE
68
Patent #:
Issue Dt:
12/21/2010
Application #:
12181843
Filing Dt:
07/29/2008
Publication #:
Pub Dt:
11/27/2008
Title:
FACILITATING SIMULATION OF A MODEL WITHIN A DISTRIBUTED ENVIRONMENT
69
Patent #:
Issue Dt:
01/11/2011
Application #:
12181852
Filing Dt:
07/29/2008
Publication #:
Pub Dt:
02/04/2010
Title:
METHOD AND APPARATUS FOR FORMING PLANAR ALLOY DEPOSITS ON A SUBSTRATE
70
Patent #:
Issue Dt:
12/14/2010
Application #:
12182158
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
11/20/2008
Title:
FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS
71
Patent #:
Issue Dt:
08/21/2012
Application #:
12182211
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
03/05/2009
Title:
VERIFYING A PROCESSOR DESIGN USING A PROCESSOR SIMULATION MODEL
72
Patent #:
Issue Dt:
02/04/2014
Application #:
12182212
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
11/20/2008
Title:
SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT
73
Patent #:
Issue Dt:
01/11/2011
Application #:
12182282
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
11/20/2008
Title:
REDUCING CONTAMINATION IN IMMERSION LITHOGRAPHY
74
Patent #:
Issue Dt:
03/20/2012
Application #:
12182411
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
02/04/2010
Title:
PERSISTENT CURRENT SWITCH
75
Patent #:
Issue Dt:
01/03/2012
Application #:
12182585
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
02/04/2010
Title:
BACK-END-OF-LINE WIRING STRUCTURES WITH INTEGRATED PASSIVE ELEMENTS AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
76
Patent #:
Issue Dt:
03/13/2012
Application #:
12182672
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
02/04/2010
Title:
SYSTEMS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK
77
Patent #:
Issue Dt:
12/13/2011
Application #:
12183099
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
02/04/2010
Title:
ADAPTIVE NOISE SUPPRESSION USING A NOISE LOOK-UP TABLE
78
Patent #:
Issue Dt:
12/16/2014
Application #:
12183166
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
12/18/2008
Title:
RIBONUCLEIC ACID INTERFERENCE MOLECULES OF ARABIDOPSIS THALIANA
79
Patent #:
Issue Dt:
04/06/2010
Application #:
12183169
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
11/20/2008
Title:
FIN-TYPE ANTIFUSE
80
Patent #:
Issue Dt:
08/05/2014
Application #:
12183204
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
12/18/2008
Title:
RIBONUCLEIC ACID INTERFERENCE MOLECULES OF ORYZA SATIVA
81
Patent #:
Issue Dt:
05/24/2011
Application #:
12183313
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
02/04/2010
Title:
VIA DENSITY CHANGE TO IMPROVE WAFER SURFACE PLANARITY
82
Patent #:
Issue Dt:
08/27/2013
Application #:
12183462
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
02/04/2010
Title:
DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS
83
Patent #:
Issue Dt:
06/15/2010
Application #:
12183533
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
12/04/2008
Title:
DYNAMIC MEMORY ALLOCATION BETWEEN INBOUND AND OUTBOUND BUFFERS IN A PROTOCOL HANDLER
84
Patent #:
Issue Dt:
06/14/2011
Application #:
12183549
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
12/18/2008
Title:
METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT
85
Patent #:
Issue Dt:
06/14/2011
Application #:
12183578
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
12/18/2008
Title:
VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GRID CONSTRAINTS
86
Patent #:
Issue Dt:
09/27/2011
Application #:
12183898
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
02/04/2010
Title:
SYSTEM AND METHOD FOR IMPROVED PLACEMENT IN CUSTOM VLSI CIRCUIT DESIGN WITH SCHEMATIC-DRIVEN PLACEMENT
87
Patent #:
Issue Dt:
09/27/2011
Application #:
12183958
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
02/04/2010
Title:
SYSTEM AND METHOD FOR AUTOMATED PLACEMENT IN CUSTOM VLSI CIRCUIT DESIGN WITH SCHEMATIC-DRIVEN PLACEMENT
88
Patent #:
Issue Dt:
05/03/2011
Application #:
12184148
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
02/04/2010
Title:
BIAS CIRCUIT FOR A MOS DEVICE
89
Patent #:
Issue Dt:
05/04/2010
Application #:
12184421
Filing Dt:
08/01/2008
Publication #:
Pub Dt:
11/27/2008
Title:
SYSTEM AND METHOD FOR PROBLEM DETERMINATION USING DEPENDENCY GRAPHS AND RUN-TIME BEHAVIOR MODELS
90
Patent #:
Issue Dt:
03/16/2010
Application #:
12185095
Filing Dt:
08/03/2008
Publication #:
Pub Dt:
01/29/2009
Title:
HIGH-RATE RLL ENCODING
91
Patent #:
Issue Dt:
09/29/2009
Application #:
12185172
Filing Dt:
08/04/2008
Publication #:
Pub Dt:
12/18/2008
Title:
ON-CHIP AC SELF-TEST CONTROLLER
92
Patent #:
Issue Dt:
10/18/2011
Application #:
12185259
Filing Dt:
08/04/2008
Publication #:
Pub Dt:
02/04/2010
Title:
METAL ADHESION BY INDUCED SURFACE ROUGHNESS
93
Patent #:
Issue Dt:
04/28/2015
Application #:
12185339
Filing Dt:
08/04/2008
Publication #:
Pub Dt:
02/04/2010
Title:
METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
94
Patent #:
Issue Dt:
05/01/2012
Application #:
12185759
Filing Dt:
08/04/2008
Publication #:
Pub Dt:
11/27/2008
Title:
DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
95
Patent #:
Issue Dt:
10/30/2012
Application #:
12186061
Filing Dt:
08/05/2008
Publication #:
Pub Dt:
02/11/2010
Title:
IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD
96
Patent #:
Issue Dt:
10/29/2013
Application #:
12186075
Filing Dt:
08/05/2008
Publication #:
Pub Dt:
11/20/2008
Title:
CMOS GATE STRUCTURES FABRICATED BY SELECTIVE OXIDATION
97
Patent #:
Issue Dt:
03/20/2012
Application #:
12186588
Filing Dt:
08/06/2008
Publication #:
Pub Dt:
02/11/2010
Title:
ROBUST JITTER-FREE REMOTE CLOCK OFFSET MEASURING METHOD
98
Patent #:
Issue Dt:
03/03/2015
Application #:
12186630
Filing Dt:
08/06/2008
Publication #:
Pub Dt:
08/06/2009
Title:
ESD POWER CLAMP WITH STABLE POWER START UP FUNCTION
99
Patent #:
Issue Dt:
01/04/2011
Application #:
12186655
Filing Dt:
08/06/2008
Publication #:
Pub Dt:
03/12/2009
Title:
DUAL-SIDED CHIP ATTACHED MODULES
100
Patent #:
Issue Dt:
05/03/2011
Application #:
12186750
Filing Dt:
08/06/2008
Publication #:
Pub Dt:
02/11/2010
Title:
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING RADIATION HARDENED INSULATORS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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