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10/21/2010
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Title:
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HIGH-K METAL GATE CMOS
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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12426467
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Filing Dt:
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04/20/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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MOSFET INCLUDING EPITAXIAL HALO REGION
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Patent #:
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Issue Dt:
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05/08/2012
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Application #:
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12426475
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Filing Dt:
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04/20/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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12426561
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Filing Dt:
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04/20/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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VERTICAL INTEGRATED CIRCUIT SWITCHES, DESIGN STRUCTURE AND METHODS OF FABRICATING SAME
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Patent #:
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Issue Dt:
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09/23/2014
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Application #:
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12426607
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Filing Dt:
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04/20/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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SYSTEM, METHOD AND GRAPHICAL USER INTERFACE FOR A SIMULATION BASED CALCULATOR
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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12426827
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Filing Dt:
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04/20/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING PLANARIZED SPACERS
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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12427484
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Filing Dt:
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04/21/2009
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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HIGH DENSITY TERNARY CONTENT ADDRESSABLE MEMORY
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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12427775
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Filing Dt:
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04/22/2009
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12429374
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Filing Dt:
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04/24/2009
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Publication #:
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Pub Dt:
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10/28/2010
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Title:
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SYNCHRONOUS AND ASYNCHRONOUS CONTINUOUS DATA PROTECTION
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Patent #:
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Issue Dt:
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08/02/2011
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Application #:
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12430300
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Filing Dt:
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04/27/2009
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Publication #:
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Pub Dt:
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10/28/2010
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Title:
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IMPLEMENTING VERTICAL AIRGAP STRUCTURES BETWEEN CHIP METAL LAYERS
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Patent #:
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Issue Dt:
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12/11/2012
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Application #:
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12431259
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Filing Dt:
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04/28/2009
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Publication #:
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Pub Dt:
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10/28/2010
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Title:
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UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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12431289
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Filing Dt:
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04/28/2009
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Publication #:
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Pub Dt:
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08/13/2009
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Title:
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VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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12431827
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Filing Dt:
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04/29/2009
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD
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Patent #:
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Issue Dt:
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10/11/2011
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Application #:
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12432082
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Filing Dt:
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04/29/2009
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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SYSTEM AND METHOD IMPLEMENTING SHORT-PULSE PROPAGATION TECHNIQUE ON PRODUCTION-LEVEL BOARDS WITH INCREMENTAL ACCURACY AND PRODUCTIVITY LEVELS
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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12432293
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Filing Dt:
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04/29/2009
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Publication #:
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Pub Dt:
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11/04/2010
| | | | |
Title:
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METHOD OF MANUFACTURING SOLAR CELL WITH DOPING PATTERNS AND CONTACTS
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12432927
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Filing Dt:
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04/30/2009
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
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Patent #:
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Issue Dt:
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12/11/2012
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Application #:
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12433157
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Filing Dt:
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04/30/2009
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS
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Patent #:
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Issue Dt:
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08/28/2012
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Application #:
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12433220
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Filing Dt:
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04/30/2009
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Publication #:
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Pub Dt:
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11/04/2010
| | | | |
Title:
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WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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12433669
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Filing Dt:
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04/30/2009
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES
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Patent #:
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Issue Dt:
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09/27/2011
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Application #:
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12434321
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Filing Dt:
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05/01/2009
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Publication #:
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Pub Dt:
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11/12/2009
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Title:
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LOW PH MIXTURES FOR THE REMOVAL OF HIGH DENSITY IMPLANTED RESIST
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12436189
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Filing Dt:
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05/06/2009
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Publication #:
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Pub Dt:
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08/27/2009
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Title:
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HIGH-Z STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS
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Patent #:
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Issue Dt:
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05/29/2012
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Application #:
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12437242
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Filing Dt:
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05/07/2009
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Publication #:
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Pub Dt:
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11/11/2010
| | | | |
Title:
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STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12437263
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Filing Dt:
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05/07/2009
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Publication #:
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Pub Dt:
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08/27/2009
| | | | |
Title:
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NEGATIVE COEFFICIENT OF THERMAL EXPANSION PARTICLES
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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12437575
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Filing Dt:
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05/08/2009
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Publication #:
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Pub Dt:
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08/27/2009
| | | | |
Title:
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ON-CHIP ADJUSTMENT OF MIMCAP AND VNCAP CAPACITORS
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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12456462
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Filing Dt:
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06/17/2009
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Publication #:
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Pub Dt:
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12/23/2010
| | | | |
Title:
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Method for forming and integrating metal gate transistors having self-aligned contacts and related structure
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Patent #:
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Issue Dt:
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09/27/2011
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Application #:
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12463221
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Filing Dt:
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05/08/2009
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Publication #:
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Pub Dt:
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11/11/2010
| | | | |
Title:
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METHOD OF FABRICATING SEMICONDUCTOR TRANSISTOR DEVICES WITH ASYMMETRIC EXTENSION AND/OR HALO IMPLANTS
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Patent #:
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Issue Dt:
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05/08/2012
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Application #:
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12464025
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Filing Dt:
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05/11/2009
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Publication #:
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Pub Dt:
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11/11/2010
| | | | |
Title:
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METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING
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Patent #:
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Issue Dt:
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05/25/2010
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Application #:
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12464161
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Filing Dt:
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05/12/2009
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND A SI/GE MATERIAL IN THE DRAIN AND SOURCE AREAS OF THE PMOS TRANSISTOR
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Patent #:
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Issue Dt:
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10/11/2011
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Application #:
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12464206
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Filing Dt:
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05/12/2009
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Publication #:
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Pub Dt:
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11/18/2010
| | | | |
Title:
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ISOLATION WITH OFFSET DEEP WELL IMPLANTS
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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12465419
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Filing Dt:
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05/13/2009
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Publication #:
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Pub Dt:
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09/03/2009
| | | | |
Title:
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INTEGRATED THERMOELECTRIC COOLING DEVICES AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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02/08/2011
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Application #:
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12465817
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Filing Dt:
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05/14/2009
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Publication #:
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Pub Dt:
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09/24/2009
| | | | |
Title:
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METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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12465857
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Filing Dt:
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05/14/2009
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Publication #:
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Pub Dt:
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11/18/2010
| | | | |
Title:
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HIGH-VOLTAGE SOI MOS DEVICE STRUCTURE AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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07/05/2011
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Application #:
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12468297
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Filing Dt:
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05/19/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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12468391
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Filing Dt:
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05/19/2009
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Publication #:
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Pub Dt:
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11/25/2010
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Title:
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Directed self-assembly of block copolymers using segmented prepatterns
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12468612
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Filing Dt:
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05/19/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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TUNNELING FIELD EFFECT TRANSISTOR SWITCH DEVICE
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Patent #:
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Issue Dt:
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12/20/2011
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Application #:
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12469304
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Filing Dt:
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05/20/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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ROBUST TOP-DOWN SILICON NANOWIRE STRUCTURE USING A CONFORMAL NITRIDE
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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12469418
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Filing Dt:
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05/20/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12469710
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Filing Dt:
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05/21/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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IMPLANTATION USING A HARDMASK
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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12470001
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Filing Dt:
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05/21/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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12470128
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Filing Dt:
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05/21/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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SINGLE GATE INVERTER NANOWIRE MESH
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Patent #:
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Issue Dt:
|
04/16/2013
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Application #:
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12470159
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Filing Dt:
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05/21/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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NANOWIRE MESH FET WITH MULTIPLE THRESHOLD VOLTAGES
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Patent #:
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Issue Dt:
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05/01/2012
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Application #:
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12470693
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Filing Dt:
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05/22/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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DATA CONSISTENCY IN LONG-RUNNING PROCESSES
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Patent #:
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Issue Dt:
|
02/14/2012
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Application #:
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12470760
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Filing Dt:
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05/22/2009
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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METHOD OF FORMING SUB-LITHOGRAPHIC FEATURES USING DIRECTED SELF-ASSEMBLY OF POLYMERS
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Patent #:
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Issue Dt:
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08/07/2012
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Application #:
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12471656
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Filing Dt:
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05/26/2009
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Publication #:
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Pub Dt:
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12/02/2010
| | | | |
Title:
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FORMING SEMICONDUCTOR CHIP CONNECTIONS
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