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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 76 of 146
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1
Patent #:
8198152
Issue Dt:
06/12/2012
Application #:
12917700
Filing Dt:
11/02/2010
Publication #:
US20110210398
Pub Dt:
09/01/2011
Title:
TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND ADAPTED CHANNEL SEMICONDUCTOR MATERIALS
2
Patent #:
9184095
Issue Dt:
11/10/2015
Application #:
12917763
Filing Dt:
11/02/2010
Publication #:
US20110210380
Pub Dt:
09/01/2011
Title:
CONTACT BARS WITH REDUCED FRINGING CAPACITANCE IN A SEMICONDUCTOR DEVICE
3
Patent #:
8105850
Issue Dt:
01/31/2012
Application #:
12917800
Filing Dt:
11/02/2010
Title:
PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE
4
Patent #:
8329531
Issue Dt:
12/11/2012
Application #:
12917870
Filing Dt:
11/02/2010
Publication #:
US20110210427
Pub Dt:
09/01/2011
Title:
STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES
5
Patent #:
8595328
Issue Dt:
11/26/2013
Application #:
12938411
Filing Dt:
11/03/2010
Publication #:
US20120110394
Pub Dt:
05/03/2012
Title:
SELF-UPDATING NODE CONTROLLER FOR AN ENDPOINT IN A CLOUD COMPUTING ENVIRONMENT
6
Patent #:
8426265
Issue Dt:
04/23/2013
Application #:
12938457
Filing Dt:
11/03/2010
Publication #:
US20120104507
Pub Dt:
05/03/2012
Title:
METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
7
Patent #:
8334088
Issue Dt:
12/18/2012
Application #:
12938459
Filing Dt:
11/03/2010
Publication #:
US20110045407
Pub Dt:
02/24/2011
Title:
FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME
8
Patent #:
8300450
Issue Dt:
10/30/2012
Application #:
12938477
Filing Dt:
11/03/2010
Publication #:
US20120106235
Pub Dt:
05/03/2012
Title:
IMPLEMENTING PHYSICALLY UNCLONABLE FUNCTION (PUF) UTILIZING EDRAM MEMORY CELL CAPACITANCE VARIATION
9
Patent #:
8507348
Issue Dt:
08/13/2013
Application #:
12939282
Filing Dt:
11/04/2010
Publication #:
US20110211394
Pub Dt:
09/01/2011
Title:
FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION
10
Patent #:
8420533
Issue Dt:
04/16/2013
Application #:
12939424
Filing Dt:
11/04/2010
Publication #:
US20110212616
Pub Dt:
09/01/2011
Title:
METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING ROUNDED INTERCONNECTS FORMED BY HARD MASK ROUNDING
11
Patent #:
8637871
Issue Dt:
01/28/2014
Application #:
12939462
Filing Dt:
11/04/2010
Publication #:
US20120112206
Pub Dt:
05/10/2012
Title:
ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE
12
Patent #:
8479578
Issue Dt:
07/09/2013
Application #:
12939471
Filing Dt:
11/04/2010
Publication #:
US20110209548
Pub Dt:
09/01/2011
Title:
ASSESSING METAL STACK INTEGRITY IN SOPHISTICATED SEMICONDUCTOR DEVICES BY MECHANICALLY STRESSING DIE CONTACTS
13
Patent #:
8642407
Issue Dt:
02/04/2014
Application #:
12939506
Filing Dt:
11/04/2010
Publication #:
US20120112246
Pub Dt:
05/10/2012
Title:
DEVICES HAVING REDUCED SUSCEPTIBILITY TO SOFT-ERROR EFFECTS AND METHOD FOR FABRICATION
14
Patent #:
8089105
Issue Dt:
01/03/2012
Application #:
12939520
Filing Dt:
11/04/2010
Publication #:
US20110042779
Pub Dt:
02/24/2011
Title:
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
15
Patent #:
8580684
Issue Dt:
11/12/2013
Application #:
12939523
Filing Dt:
11/04/2010
Publication #:
US20110210447
Pub Dt:
09/01/2011
Title:
CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES COMPRISING A CONTINUOUS TRANSITION TO METAL LINES OF A METALLIZATION LAYER
16
Patent #:
8236655
Issue Dt:
08/07/2012
Application #:
12939538
Filing Dt:
11/04/2010
Publication #:
US20110045644
Pub Dt:
02/24/2011
Title:
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
17
Patent #:
8232156
Issue Dt:
07/31/2012
Application #:
12939668
Filing Dt:
11/04/2010
Publication #:
US20120112244
Pub Dt:
05/10/2012
Title:
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
18
Patent #:
8558695
Issue Dt:
10/15/2013
Application #:
12940095
Filing Dt:
11/05/2010
Publication #:
US20120116580
Pub Dt:
05/10/2012
Title:
Biodegradable Device and Mesh Network for Optimization of Payload Material Delivery
19
Patent #:
8445965
Issue Dt:
05/21/2013
Application #:
12940115
Filing Dt:
11/05/2010
Publication #:
US20120112284
Pub Dt:
05/10/2012
Title:
STRAINED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING STRAINED SEMICONDUCTOR DEVICES
20
Patent #:
8492845
Issue Dt:
07/23/2013
Application #:
12940210
Filing Dt:
11/05/2010
Publication #:
US20120112287
Pub Dt:
05/10/2012
Title:
GATE-TO-GATE RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
21
Patent #:
8332787
Issue Dt:
12/11/2012
Application #:
12940762
Filing Dt:
11/05/2010
Publication #:
US20120117524
Pub Dt:
05/10/2012
Title:
REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT
22
Patent #:
8324058
Issue Dt:
12/04/2012
Application #:
12941042
Filing Dt:
11/06/2010
Publication #:
US20120112279
Pub Dt:
05/10/2012
Title:
CONTACTS FOR FET DEVICES
23
Patent #:
8119522
Issue Dt:
02/21/2012
Application #:
12941184
Filing Dt:
11/08/2010
Title:
METHOD OF FABRICATING DAMASCENE STRUCTURES
24
Patent #:
8609485
Issue Dt:
12/17/2013
Application #:
12941185
Filing Dt:
11/08/2010
Publication #:
US20110241124
Pub Dt:
10/06/2011
Title:
METHODS OF FORMING EFUSE DEVICES
25
Patent #:
8395228
Issue Dt:
03/12/2013
Application #:
12941375
Filing Dt:
11/08/2010
Publication #:
US20120112302
Pub Dt:
05/10/2012
Title:
NOVEL INTEGRATION PROCESS TO IMPROVE FOCUS LEVELING WITHIN A LOT PROCESS VARIATION
26
Patent #:
8564089
Issue Dt:
10/22/2013
Application #:
12941595
Filing Dt:
11/08/2010
Publication #:
US20110241086
Pub Dt:
10/06/2011
Title:
ELECTRONIC FUSE STRUCTURE FORMED USING A METAL GATE ELECTRODE MATERIAL STACK CONFIGURATION
27
Patent #:
8618554
Issue Dt:
12/31/2013
Application #:
12941771
Filing Dt:
11/08/2010
Publication #:
US20120112207
Pub Dt:
05/10/2012
Title:
METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE
28
Patent #:
9679029
Issue Dt:
06/13/2017
Application #:
12942011
Filing Dt:
11/08/2010
Publication #:
US20120116743
Pub Dt:
05/10/2012
Title:
OPTIMIZING STORAGE CLOUD ENVIRONMENTS THROUGH ADAPTIVE STATISTICAL MODELING
29
Patent #:
8420491
Issue Dt:
04/16/2013
Application #:
12942097
Filing Dt:
11/09/2010
Publication #:
US20120112290
Pub Dt:
05/10/2012
Title:
STRUCTURE AND METHOD FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS
30
Patent #:
9034744
Issue Dt:
05/19/2015
Application #:
12942200
Filing Dt:
11/09/2010
Publication #:
US20110244670
Pub Dt:
10/06/2011
Title:
Replacement Gate Approach for High-K Metal Gate Stacks by Avoiding a Polishing Process for Exposing the Placeholder Material
31
Patent #:
8361859
Issue Dt:
01/29/2013
Application #:
12942289
Filing Dt:
11/09/2010
Publication #:
US20120112208
Pub Dt:
05/10/2012
Title:
STRESSED TRANSISTOR WITH IMPROVED METASTABILITY
32
Patent #:
8420479
Issue Dt:
04/16/2013
Application #:
12942378
Filing Dt:
11/09/2010
Publication #:
US20110241166
Pub Dt:
10/06/2011
Title:
SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR FORMED IN THE CONTACT LEVEL
33
Patent #:
8541769
Issue Dt:
09/24/2013
Application #:
12942490
Filing Dt:
11/09/2010
Publication #:
US20120112164
Pub Dt:
05/10/2012
Title:
FORMATION OF A GRAPHENE LAYER ON A LARGE SUBSTRATE
34
Patent #:
8497554
Issue Dt:
07/30/2013
Application #:
12942506
Filing Dt:
11/09/2010
Publication #:
US20110241117
Pub Dt:
10/06/2011
Title:
SEMICONDUCTOR DEVICE COMPRISING METAL GATE STRUCTURES FORMED BY A REPLACEMENT GATE APPROACH AND EFUSES INCLUDING A SILICIDE
35
Patent #:
8542030
Issue Dt:
09/24/2013
Application #:
12942662
Filing Dt:
11/09/2010
Publication #:
US20120112776
Pub Dt:
05/10/2012
Title:
THREE-DIMENSIONAL (3D) STACKED INTEGRATED CIRCUIT TESTING
36
Patent #:
8741725
Issue Dt:
06/03/2014
Application #:
12943084
Filing Dt:
11/10/2010
Publication #:
US20120112280
Pub Dt:
05/10/2012
Title:
BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION
37
Patent #:
8114747
Issue Dt:
02/14/2012
Application #:
12943146
Filing Dt:
11/10/2010
Publication #:
US20110059583
Pub Dt:
03/10/2011
Title:
METHOD FOR CREATING 3-D SINGLE GATE INVERTER
38
Patent #:
8633096
Issue Dt:
01/21/2014
Application #:
12943987
Filing Dt:
11/11/2010
Publication #:
US20120119294
Pub Dt:
05/17/2012
Title:
CREATING ANISOTROPICALLY DIFFUSED JUNCTIONS IN FIELD EFFECT TRANSISTOR DEVICES
39
Patent #:
8637941
Issue Dt:
01/28/2014
Application #:
12943995
Filing Dt:
11/11/2010
Publication #:
US20120119307
Pub Dt:
05/17/2012
Title:
SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
40
Patent #:
8516409
Issue Dt:
08/20/2013
Application #:
12944020
Filing Dt:
11/11/2010
Publication #:
US20120124532
Pub Dt:
05/17/2012
Title:
IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION OVER MULTIPLE DIES IN THROUGH-SILICON-VIA STACKED SEMICONDUCTOR DEVICE
41
Patent #:
8409989
Issue Dt:
04/02/2013
Application #:
12944174
Filing Dt:
11/11/2010
Publication #:
US20120119310
Pub Dt:
05/17/2012
Title:
STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT
42
Patent #:
8239810
Issue Dt:
08/07/2012
Application #:
12944480
Filing Dt:
11/11/2010
Publication #:
US20120124542
Pub Dt:
05/17/2012
Title:
METHOD AND SYSTEM FOR OPTIMIZING A DEVICE WITH CURRENT SOURCE MODELS
43
Patent #:
8250509
Issue Dt:
08/21/2012
Application #:
12944493
Filing Dt:
11/11/2010
Publication #:
US20120124537
Pub Dt:
05/17/2012
Title:
SLACK-BASED TIMING BUDGET APPORTIONMENT
44
Patent #:
8527704
Issue Dt:
09/03/2013
Application #:
12944682
Filing Dt:
11/11/2010
Publication #:
US20120124318
Pub Dt:
05/17/2012
Title:
METHOD AND APPARATUS FOR OPTIMAL CACHE SIZING AND CONFIGURATION FOR LARGE MEMORY SYSTEMS
45
Patent #:
8402403
Issue Dt:
03/19/2013
Application #:
12946325
Filing Dt:
11/15/2010
Publication #:
US20110154110
Pub Dt:
06/23/2011
Title:
VERIFYING A REGISTER-TRANSFER LEVEL DESIGN OF AN EXECUTION UNIT
46
Patent #:
8040140
Issue Dt:
10/18/2011
Application #:
12946386
Filing Dt:
11/15/2010
Publication #:
US20110057666
Pub Dt:
03/10/2011
Title:
METHOD AND APPARATUS FOR IDENTIFYING BROKEN PINS IN A TEST SOCKET
47
Patent #:
8610451
Issue Dt:
12/17/2013
Application #:
12946875
Filing Dt:
11/16/2010
Publication #:
US20120119778
Pub Dt:
05/17/2012
Title:
POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES
48
Patent #:
8395196
Issue Dt:
03/12/2013
Application #:
12946915
Filing Dt:
11/16/2010
Publication #:
US20120119273
Pub Dt:
05/17/2012
Title:
HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
49
Patent #:
8554390
Issue Dt:
10/08/2013
Application #:
12946925
Filing Dt:
11/16/2010
Publication #:
US20120123607
Pub Dt:
05/17/2012
Title:
FREE COOLING SOLUTION FOR A CONTAINERIZED DATA CENTER
50
Patent #:
8202739
Issue Dt:
06/19/2012
Application #:
12947150
Filing Dt:
11/16/2010
Publication #:
US20120122249
Pub Dt:
05/17/2012
Title:
DOPANT MARKER FOR PRECISE RECESS CONTROL
51
Patent #:
8667441
Issue Dt:
03/04/2014
Application #:
12947445
Filing Dt:
11/16/2010
Publication #:
US20120124539
Pub Dt:
05/17/2012
Title:
Clock Optimization with Local Clock Buffer Control Optimization
52
Patent #:
8329551
Issue Dt:
12/11/2012
Application #:
12947460
Filing Dt:
11/16/2010
Publication #:
US20120119259
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR DEVICE SUBSTRATE WITH EMBEDDED STRESS REGION, AND RELATED FABRICATION METHODS
53
Patent #:
8546211
Issue Dt:
10/01/2013
Application #:
12948031
Filing Dt:
11/17/2010
Publication #:
US20120119204
Pub Dt:
05/17/2012
Title:
Replacement Gate Having Work Function at Valence Band Edge
54
Patent #:
8138099
Issue Dt:
03/20/2012
Application #:
12948079
Filing Dt:
11/17/2010
Title:
CHIP PACKAGE SOLDER INTERCONNECT FORMED BY SURFACE TENSION
55
Patent #:
8227333
Issue Dt:
07/24/2012
Application #:
12948092
Filing Dt:
11/17/2010
Publication #:
US20120119362
Pub Dt:
05/17/2012
Title:
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
56
Patent #:
8296707
Issue Dt:
10/23/2012
Application #:
12948165
Filing Dt:
11/17/2010
Publication #:
US20120124541
Pub Dt:
05/17/2012
Title:
IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION
57
Patent #:
8084311
Issue Dt:
12/27/2011
Application #:
12948246
Filing Dt:
11/17/2010
Title:
METHOD OF FORMING REPLACEMENT METAL GATE WITH BORDERLESS CONTACT AND STRUCTURE THEREOF
58
Patent #:
7985668
Issue Dt:
07/26/2011
Application #:
12948463
Filing Dt:
11/17/2010
Title:
METHOD FOR FORMING A METAL SILICIDE HAVING A LOWER POTENTIAL FOR CONTAINING MATERIAL DEFECTS
59
Patent #:
8236662
Issue Dt:
08/07/2012
Application #:
12949108
Filing Dt:
11/18/2010
Publication #:
US20110062548
Pub Dt:
03/17/2011
Title:
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
60
Patent #:
8507346
Issue Dt:
08/13/2013
Application #:
12949148
Filing Dt:
11/18/2010
Publication #:
US20120126294
Pub Dt:
05/24/2012
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A CUT-WAY HOLE TO EXPOSE A PORTION OF A HARDMASK LAYER
61
Patent #:
8466056
Issue Dt:
06/18/2013
Application #:
12949158
Filing Dt:
11/18/2010
Publication #:
US20110117737
Pub Dt:
05/19/2011
Title:
Method of Forming Metal Interconnect Structures in Ultra Low-K Dielectrics
62
Patent #:
8327304
Issue Dt:
12/04/2012
Application #:
12949328
Filing Dt:
11/18/2010
Publication #:
US20120131530
Pub Dt:
05/24/2012
Title:
PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION
63
Patent #:
8569131
Issue Dt:
10/29/2013
Application #:
12949888
Filing Dt:
11/19/2010
Publication #:
US20120126337
Pub Dt:
05/24/2012
Title:
SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
64
Patent #:
8486796
Issue Dt:
07/16/2013
Application #:
12950635
Filing Dt:
11/19/2010
Publication #:
US20120126370
Pub Dt:
05/24/2012
Title:
THIN FILM RESISTORS AND METHODS OF MANUFACTURE
65
Patent #:
8492286
Issue Dt:
07/23/2013
Application #:
12951107
Filing Dt:
11/22/2010
Publication #:
US20120129312
Pub Dt:
05/24/2012
Title:
METHOD OF FORMING E-FUSE IN REPLACEMENT METAL GATE MANUFACTURING PROCESS
66
Patent #:
8389372
Issue Dt:
03/05/2013
Application #:
12951516
Filing Dt:
11/22/2010
Publication #:
US20120126292
Pub Dt:
05/24/2012
Title:
HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
67
Patent #:
8378419
Issue Dt:
02/19/2013
Application #:
12951575
Filing Dt:
11/22/2010
Publication #:
US20120126336
Pub Dt:
05/24/2012
Title:
ISOLATION FET FOR INTEGRATED CIRCUIT
68
Patent #:
8633067
Issue Dt:
01/21/2014
Application #:
12951597
Filing Dt:
11/22/2010
Publication #:
US20120129302
Pub Dt:
05/24/2012
Title:
FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS
69
Patent #:
8486751
Issue Dt:
07/16/2013
Application #:
12952465
Filing Dt:
11/23/2010
Publication #:
US20110120519
Pub Dt:
05/26/2011
Title:
Method of Manufacturing a Photovoltaic Cell
70
Patent #:
8299533
Issue Dt:
10/30/2012
Application #:
12954155
Filing Dt:
11/24/2010
Publication #:
US20120126285
Pub Dt:
05/24/2012
Title:
VERTICAL NPNP STRUCTURE IN A TRIPLE WELL CMOS PROCESS
71
Patent #:
8524614
Issue Dt:
09/03/2013
Application #:
12955203
Filing Dt:
11/29/2010
Publication #:
US20120132913
Pub Dt:
05/31/2012
Title:
III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER
72
Patent #:
8138008
Issue Dt:
03/20/2012
Application #:
12955224
Filing Dt:
11/29/2010
Title:
FORMING AN OXIDE MEMS BEAM
73
Patent #:
8936978
Issue Dt:
01/20/2015
Application #:
12955388
Filing Dt:
11/29/2010
Publication #:
US20120132989
Pub Dt:
05/31/2012
Title:
MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION
74
Patent #:
8133061
Issue Dt:
03/13/2012
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Title:
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Title:
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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