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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
10/02/2012
Application #:
12963246
Filing Dt:
12/08/2010
Publication #:
Pub Dt:
06/14/2012
Title:
CREATING SCAN CHAIN DEFINITION FROM HIGH-LEVEL MODEL USING HIGH-LEVEL MODEL SIMULATION
2
Patent #:
Issue Dt:
04/09/2013
Application #:
12963314
Filing Dt:
12/08/2010
Publication #:
Pub Dt:
06/14/2012
Title:
NARROW-BAND WIDE-RANGE FREQUENCY MODULATION CONTINUOUS WAVE (FMCW) RADAR SYSTEM
3
Patent #:
Issue Dt:
05/28/2013
Application #:
12963364
Filing Dt:
12/08/2010
Publication #:
Pub Dt:
11/03/2011
Title:
SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND SEMICONDUCTOR RESISTORS FORMED ON THE BASIS OF A REPLACEMENT GATE APPROACH
4
Patent #:
Issue Dt:
11/20/2012
Application #:
12963677
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
06/14/2012
Title:
MULTISTAGE, HYBRID SYNTHESIS PROCESSING FACILITATING INTEGRATED CIRCUIT LAYOUT
5
Patent #:
Issue Dt:
04/23/2013
Application #:
12963753
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
11/03/2011
Title:
STRESS MEMORIZATION WITH REDUCED FRINGING CAPACITANCE BASED ON SILICON NITRIDE IN MOS SEMICONDUCTOR DEVICES
6
Patent #:
Issue Dt:
05/22/2012
Application #:
12963908
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
11/03/2011
Title:
REDUCED DEFECTIVITY IN CONTACTS OF A SEMICONDUCTOR DEVICE COMPRISING REPLACEMENT GATE ELECTRODE STRUCTURES BY USING AN INTERMEDIATE CAP LAYER
7
Patent #:
Issue Dt:
08/20/2013
Application #:
12964082
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
06/14/2012
Title:
PSEUDO BUTTED JUNCTION STRUCTURE FOR BACK PLANE CONNECTION
8
Patent #:
Issue Dt:
05/08/2012
Application #:
12964136
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
11/03/2011
Title:
REDUCED STI TOPOGRAPHY IN HIGH-K METAL GATE TRANSISTORS BY USING A MASK AFTER CHANNEL SEMICONDUCTOR ALLOY DEPOSITION
9
Patent #:
Issue Dt:
10/15/2013
Application #:
12964340
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
06/14/2012
Title:
ADDING SCALABILITY AND FAULT TOLERANCE TO GENERIC FINITE STATE MACHINE FRAMEWORKS FOR USE IN AUTOMATED INCIDENT MANAGEMENT OF CLOUD COMPUTING INFRASTRUCTURES
10
Patent #:
Issue Dt:
08/13/2013
Application #:
12964359
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
12/01/2011
Title:
CHIP PACKAGE INCLUDING MULTIPLE SECTIONS FOR REDUCING CHIP PACKAGE INTERACTION
11
Patent #:
Issue Dt:
07/30/2013
Application #:
12964448
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
12/01/2011
Title:
STRESS REDUCTION IN CHIP PACKAGING BY A STRESS COMPENSATION REGION FORMED AROUND THE CHIP
12
Patent #:
Issue Dt:
12/25/2012
Application #:
12964807
Filing Dt:
12/10/2010
Publication #:
Pub Dt:
06/14/2012
Title:
ASYNCHRONOUS DELETION OF A RANGE OF MESSAGES PROCESSED BY A PARALLEL DATABASE REPLICATION APPLY PROCESS
13
Patent #:
Issue Dt:
10/04/2011
Application #:
12964831
Filing Dt:
12/10/2010
Title:
TEMPORARY ETCHABLE LINER FOR FORMING AIR GAP
14
Patent #:
Issue Dt:
01/27/2015
Application #:
12965118
Filing Dt:
12/10/2010
Publication #:
Pub Dt:
12/01/2011
Title:
Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth
15
Patent #:
Issue Dt:
02/03/2015
Application #:
12965212
Filing Dt:
12/10/2010
Publication #:
Pub Dt:
12/01/2011
Title:
Semiconductor Device Comprising a Buried Capacitor Formed in the Contact Level
16
Patent #:
Issue Dt:
03/18/2014
Application #:
12965341
Filing Dt:
12/10/2010
Publication #:
Pub Dt:
01/05/2012
Title:
TEST STRUCTURE FOR CONTROLLING THE INCORPORATION OF SEMICONDUCTOR ALLOYS IN TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES
17
Patent #:
Issue Dt:
12/11/2012
Application #:
12965488
Filing Dt:
12/10/2010
Publication #:
Pub Dt:
01/05/2012
Title:
CONTROL OF CRITICAL DIMENSIONS IN OPTICAL IMAGING PROCESSES FOR SEMICONDUCTOR PRODUCTION BY EXTRACTING IMAGING IMPERFECTIONS ON THE BASIS OF IMAGING TOOL SPECIFIC INTENSITY MEASUREMENTS AND SIMULATIONS
18
Patent #:
Issue Dt:
07/22/2014
Application #:
12966302
Filing Dt:
12/13/2010
Publication #:
Pub Dt:
01/05/2012
Title:
Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction
19
Patent #:
Issue Dt:
12/17/2013
Application #:
12967114
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
06/14/2012
Title:
SELF-PROTECTED ELECTROSTATIC DISCHARGE FIELD EFFECT TRANSISTOR (SPESDFET), AN INTEGRATED CIRCUIT INCORPORATING THE SPESDFET AS AN INPUT/OUTPUT (I/O) PAD DRIVER AND ASSOCIATED METHODS OF FORMING THE SPESDFET AND THE INTEGRATED CIRCUIT
20
Patent #:
Issue Dt:
08/20/2013
Application #:
12967268
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
12/22/2011
Title:
TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
21
Patent #:
Issue Dt:
11/19/2013
Application #:
12967308
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
06/14/2012
Title:
ELECTRICAL FUSE WITH A CURRENT SHUNT
22
Patent #:
Issue Dt:
04/15/2014
Application #:
12967329
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
06/14/2012
Title:
PARTIALLY DEPLETED (PD) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (VT) LOWERING AND METHOD OF FORMING THE STRUCTURE
23
Patent #:
Issue Dt:
06/17/2014
Application #:
12967625
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
06/14/2012
Title:
METHOD OF FABRICATING PHOTOCONDUCTOR-ON-ACTIVE PIXEL DEVICE
24
Patent #:
Issue Dt:
12/16/2014
Application #:
12967771
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
06/14/2012
Title:
DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY
25
Patent #:
Issue Dt:
02/10/2015
Application #:
12968068
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
06/14/2012
Title:
SEMICONDUCTOR DEVICES HAVING THROUGH-CONTACTS AND RELATED FABRICATION METHODS
26
Patent #:
Issue Dt:
02/25/2014
Application #:
12968864
Filing Dt:
12/15/2010
Publication #:
Pub Dt:
06/21/2012
Title:
STRESS TESTING OF SILICON-ON-INSULATOR SUBSTRATES USING APPLIED ELECTROSTATIC DISCHARGE
27
Patent #:
Issue Dt:
05/21/2013
Application #:
12969004
Filing Dt:
12/15/2010
Publication #:
Pub Dt:
06/21/2012
Title:
METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY
28
Patent #:
Issue Dt:
11/19/2013
Application #:
12969969
Filing Dt:
12/16/2010
Publication #:
Pub Dt:
11/03/2011
Title:
PLANARIZATION OF A MATERIAL SYSTEM IN A SEMICONDUCTOR DEVICE BY USING A NON-SELECTIVE IN SITU PREPARED SLURRY
29
Patent #:
Issue Dt:
03/19/2013
Application #:
12970117
Filing Dt:
12/16/2010
Publication #:
Pub Dt:
01/05/2012
Title:
SOPHISTICATED METALLIZATION SYSTEMS IN SEMICONDUCTORS FORMED BY REMOVING DAMAGED DIELECTRIC SURFACE LAYERS AFTER FORMING THE METAL FEATURES
30
Patent #:
Issue Dt:
12/03/2013
Application #:
12970553
Filing Dt:
12/16/2010
Publication #:
Pub Dt:
01/05/2012
Title:
SEMICONDUCTOR DEVICE COMPRISING THROUGH HOLE VIAS HAVING A STRESS RELAXATION MECHANISM
31
Patent #:
Issue Dt:
08/07/2012
Application #:
12972771
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
04/14/2011
Title:
HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME
32
Patent #:
Issue Dt:
03/26/2013
Application #:
12972879
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
06/21/2012
Title:
TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
33
Patent #:
Issue Dt:
03/05/2013
Application #:
12972934
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
06/21/2012
Title:
TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES
34
Patent #:
Issue Dt:
12/25/2012
Application #:
12972980
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
06/21/2012
Title:
TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS
35
Patent #:
Issue Dt:
08/07/2012
Application #:
12973062
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
04/14/2011
Title:
COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION
36
Patent #:
Issue Dt:
03/20/2012
Application #:
12973063
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
08/25/2011
Title:
FORMATION OF CARBON AND SEMICONDUCTOR NANOMATERIALS USING MOLECULAR ASSEMBLIES
37
Patent #:
Issue Dt:
02/17/2015
Application #:
12973147
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
12/29/2011
Title:
PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
38
Patent #:
Issue Dt:
04/01/2014
Application #:
12973285
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
12/29/2011
Title:
PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
39
Patent #:
Issue Dt:
05/22/2012
Application #:
12973373
Filing Dt:
12/20/2010
Title:
METHOD OF FABRICATING A CONDUCTIVE INTERCONNECT ARRANGEMENT FOR A SEMICONDUCTOR DEVICE
40
Patent #:
Issue Dt:
10/23/2012
Application #:
12973377
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
04/14/2011
Title:
BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
41
Patent #:
Issue Dt:
05/13/2014
Application #:
12973430
Filing Dt:
12/20/2010
Publication #:
Pub Dt:
12/29/2011
Title:
PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
42
Patent #:
Issue Dt:
02/11/2014
Application #:
12974037
Filing Dt:
12/21/2010
Publication #:
Pub Dt:
06/21/2012
Title:
Encapsulation of Closely Spaced Gate Electrode Structures
43
Patent #:
Issue Dt:
01/08/2013
Application #:
12974170
Filing Dt:
12/21/2010
Publication #:
Pub Dt:
06/21/2012
Title:
MODEL LIBRARY IMPLEMENTATION AND METHODOLOGY FOR WORST CASE PERFORMANCE MODELING FOR SRAM CELLS
44
Patent #:
Issue Dt:
06/12/2012
Application #:
12974451
Filing Dt:
12/21/2010
Publication #:
Pub Dt:
04/21/2011
Title:
DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP
45
Patent #:
Issue Dt:
08/02/2016
Application #:
12974854
Filing Dt:
12/21/2010
Publication #:
Pub Dt:
12/29/2011
Title:
PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
46
Patent #:
Issue Dt:
02/04/2014
Application #:
12975327
Filing Dt:
12/21/2010
Publication #:
Pub Dt:
06/21/2012
Title:
INTEGRATED CIRCUIT SYSTEM WITH REDUCED POLYSILICON RESIDUE AND METHOD OF MANUFACTURE THEREOF
47
Patent #:
Issue Dt:
05/07/2013
Application #:
12975515
Filing Dt:
12/22/2010
Publication #:
Pub Dt:
06/28/2012
Title:
ENHANCEMENT OF ULTRAVIOLET CURING OF TENSILE STRESS LINER USING REFLECTIVE MATERIALS
48
Patent #:
Issue Dt:
09/24/2013
Application #:
12975701
Filing Dt:
12/22/2010
Publication #:
Pub Dt:
06/28/2012
Title:
INTEGRATED CIRCUIT FABRICATION METHODS UTILIZING EMBEDDED HARDMASK LAYERS FOR HIGH RESOLUTION PATTERNING
49
Patent #:
Issue Dt:
10/22/2013
Application #:
12977134
Filing Dt:
12/23/2010
Publication #:
Pub Dt:
04/21/2011
Title:
ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT
50
Patent #:
Issue Dt:
11/05/2013
Application #:
12982014
Filing Dt:
12/30/2010
Publication #:
Pub Dt:
07/21/2011
Title:
MATERIALS AND METHODS FOR IMMOBILIZATION OF CATALYSTS ON SURFACES AND FOR SELECTIVE ELECTROLESS METALLIZATION
51
Patent #:
Issue Dt:
03/20/2012
Application #:
12983297
Filing Dt:
01/01/2011
Publication #:
Pub Dt:
06/02/2011
Title:
CHEMICAL TRIM OF PHOTORESIST LINES BY MEANS OF A TUNED OVERCOAT
52
Patent #:
Issue Dt:
09/24/2013
Application #:
12983352
Filing Dt:
01/03/2011
Publication #:
Pub Dt:
07/05/2012
Title:
SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS
53
Patent #:
Issue Dt:
06/25/2013
Application #:
12983353
Filing Dt:
01/03/2011
Publication #:
Pub Dt:
07/05/2012
Title:
STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS
54
Patent #:
Issue Dt:
04/16/2013
Application #:
12983377
Filing Dt:
01/03/2011
Publication #:
Pub Dt:
04/28/2011
Title:
METHOD FOR DIRECT HEAT SINK ATTACHMENT
55
Patent #:
Issue Dt:
10/30/2012
Application #:
12983439
Filing Dt:
01/03/2011
Publication #:
Pub Dt:
07/05/2012
Title:
LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES
56
Patent #:
Issue Dt:
09/09/2014
Application #:
12983477
Filing Dt:
01/03/2011
Publication #:
Pub Dt:
05/12/2011
Title:
METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS
57
Patent #:
Issue Dt:
06/17/2014
Application #:
12983489
Filing Dt:
01/03/2011
Publication #:
Pub Dt:
07/05/2012
Title:
JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE
58
Patent #:
Issue Dt:
01/15/2013
Application #:
12983552
Filing Dt:
01/03/2011
Publication #:
Pub Dt:
04/28/2011
Title:
SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS
59
Patent #:
Issue Dt:
10/30/2012
Application #:
12983925
Filing Dt:
01/04/2011
Publication #:
Pub Dt:
07/05/2012
Title:
FIELD EFFECT TRANSISTOR HAVING OHMIC BODY CONTACT(S), AN INTEGRATED CIRCUIT STRUCTURE INCORPORATING STACKED FIELD EFFECT TRANSISTORS WITH SUCH OHMIC BODY CONTACTS AND ASSOCIATED METHODS
60
Patent #:
Issue Dt:
07/31/2012
Application #:
12983995
Filing Dt:
01/04/2011
Publication #:
Pub Dt:
04/28/2011
Title:
CONTENT ADDRESSABLE MEMORY WITH CONCURRENT READ AND SEARCH/COMPARE OPERATIONS AT THE SAME MEMORY CELL
61
Patent #:
Issue Dt:
05/27/2014
Application #:
12984180
Filing Dt:
01/04/2011
Publication #:
Pub Dt:
07/05/2012
Title:
ADVANCED ROUTING OF VEHICLE FLEETS
62
Patent #:
Issue Dt:
09/10/2013
Application #:
12984252
Filing Dt:
01/04/2011
Publication #:
Pub Dt:
08/18/2011
Title:
CACHE DIRECTORY LOOK-UP RE-USE AS CONFLICT CHECK MECHANISM FOR SPECULATIVE MEMORY REQUESTS
63
Patent #:
Issue Dt:
09/16/2014
Application #:
12984308
Filing Dt:
01/04/2011
Publication #:
Pub Dt:
07/14/2011
Title:
EVICT ON WRITE, A MANAGEMENT STRATEGY FOR A PREFETCH UNIT AND/OR FIRST LEVEL CACHE IN A MULTIPROCESSOR SYSTEM WITH SPECULATIVE EXECUTION
64
Patent #:
Issue Dt:
12/10/2013
Application #:
12984359
Filing Dt:
01/04/2011
Publication #:
Pub Dt:
07/05/2012
Title:
FLAT RESPONSE DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS
65
Patent #:
Issue Dt:
01/28/2014
Application #:
12984653
Filing Dt:
01/05/2011
Publication #:
Pub Dt:
05/12/2011
Title:
VERTICAL NANOWIRE FET DEVICES
66
Patent #:
Issue Dt:
03/27/2012
Application #:
12984682
Filing Dt:
01/05/2011
Publication #:
Pub Dt:
04/28/2011
Title:
MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION
67
Patent #:
Issue Dt:
11/08/2011
Application #:
12985060
Filing Dt:
01/05/2011
Publication #:
Pub Dt:
05/05/2011
Title:
ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
68
Patent #:
Issue Dt:
05/26/2015
Application #:
12985443
Filing Dt:
01/06/2011
Publication #:
Pub Dt:
07/12/2012
Title:
VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
69
Patent #:
Issue Dt:
01/29/2013
Application #:
12985456
Filing Dt:
01/06/2011
Publication #:
Pub Dt:
05/05/2011
Title:
SUBSTRATE ANCHOR STRUCTURE AND METHOD
70
Patent #:
Issue Dt:
12/24/2013
Application #:
12985462
Filing Dt:
01/06/2011
Publication #:
Pub Dt:
07/12/2012
Title:
VOLTAGE DRIVER FOR A VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
71
Patent #:
Issue Dt:
07/05/2016
Application #:
12985669
Filing Dt:
01/06/2011
Publication #:
Pub Dt:
07/12/2012
Title:
Structure and Method to Fabricate Resistor on FinFET Processes
72
Patent #:
Issue Dt:
03/20/2012
Application #:
12985726
Filing Dt:
01/06/2011
Publication #:
Pub Dt:
05/05/2011
Title:
A SYSTEM FOR RECONFIGURING CACHE MEMORY HAVING AN ACCESS BIT ASSOCIATED WITH A SECTOR OF A LOWER-LEVEL CACHE MEMORY AND A GRANULARITY BIT ASSOCIATED WITH A SECTOR OF A HIGHER-LEVEL CACHE MEMORY
73
Patent #:
Issue Dt:
12/09/2014
Application #:
12985840
Filing Dt:
01/06/2011
Publication #:
Pub Dt:
07/12/2012
Title:
SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES
74
Patent #:
Issue Dt:
02/11/2014
Application #:
12986266
Filing Dt:
01/07/2011
Publication #:
Pub Dt:
07/12/2012
Title:
CONDUCTIVE METAL AND DIFFUSION BARRIER SEED COMPOSITIONS, AND METHODS OF USE IN SEMICONDUCTOR AND INTERLEVEL DIELECTRIC SUBSTRATES
75
Patent #:
Issue Dt:
11/18/2014
Application #:
12986652
Filing Dt:
01/07/2011
Publication #:
Pub Dt:
07/21/2011
Title:
STORE-OPERATE-COHERENCE-ON-VALUE
76
Patent #:
Issue Dt:
11/08/2011
Application #:
12987089
Filing Dt:
01/08/2011
Publication #:
Pub Dt:
05/05/2011
Title:
FOUR-TERMINAL RECONFIGURABLE DEVICES
77
Patent #:
Issue Dt:
01/15/2013
Application #:
12987106
Filing Dt:
01/08/2011
Publication #:
Pub Dt:
05/05/2011
Title:
APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
78
Patent #:
Issue Dt:
10/01/2013
Application #:
12987202
Filing Dt:
01/10/2011
Publication #:
Pub Dt:
07/12/2012
Title:
ALIGNMENT MARKS TO ENABLE 3D INTEGRATION
79
Patent #:
Issue Dt:
09/17/2013
Application #:
12987221
Filing Dt:
01/10/2011
Publication #:
Pub Dt:
07/12/2012
Title:
SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
80
Patent #:
Issue Dt:
05/13/2014
Application #:
12987353
Filing Dt:
01/10/2011
Publication #:
Pub Dt:
07/12/2012
Title:
METHODS AND APPARATUS FOR DETECTION OF GASEOUS CORROSIVE CONTAMINANTS
81
Patent #:
NONE
Issue Dt:
Application #:
12988814
Filing Dt:
10/21/2010
Publication #:
Pub Dt:
10/11/2012
Title:
NON-WOVEN MEMBRANE BIOREACTOR AND ITS FOULING CONTROL METHOD
82
Patent #:
Issue Dt:
07/14/2015
Application #:
13004007
Filing Dt:
01/10/2011
Publication #:
Pub Dt:
09/08/2011
Title:
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
83
Patent #:
Issue Dt:
04/16/2013
Application #:
13004104
Filing Dt:
01/11/2011
Publication #:
Pub Dt:
07/12/2012
Title:
DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 AND L2 LATCHES
84
Patent #:
Issue Dt:
11/10/2015
Application #:
13004129
Filing Dt:
01/11/2011
Publication #:
Pub Dt:
05/05/2011
Title:
A THREE-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT
85
Patent #:
Issue Dt:
05/08/2012
Application #:
13004201
Filing Dt:
01/11/2011
Title:
PROCESS FOR EPITAXIALLY GROWING EPITAXIAL MATERIAL REGIONS
86
Patent #:
Issue Dt:
03/12/2013
Application #:
13004471
Filing Dt:
01/11/2011
Publication #:
Pub Dt:
05/26/2011
Title:
SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT
87
Patent #:
Issue Dt:
01/08/2013
Application #:
13004883
Filing Dt:
01/12/2011
Publication #:
Pub Dt:
07/12/2012
Title:
FLASH ANALOG TO DIGITAL CONVERTER WITH METHOD AND SYSTEM FOR DYNAMIC CALIBRATION
88
Patent #:
Issue Dt:
05/07/2013
Application #:
13005089
Filing Dt:
01/12/2011
Publication #:
Pub Dt:
07/12/2012
Title:
IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS
89
Patent #:
Issue Dt:
01/01/2013
Application #:
13005201
Filing Dt:
01/12/2011
Publication #:
Pub Dt:
05/12/2011
Title:
DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
90
Patent #:
Issue Dt:
02/19/2013
Application #:
13005246
Filing Dt:
01/12/2011
Publication #:
Pub Dt:
05/12/2011
Title:
METHOD AND APPARATUS FOR OPTICAL MODULATION
91
Patent #:
Issue Dt:
03/11/2014
Application #:
13005560
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
07/19/2012
Title:
SEMICONDUCTOR STRUCTURES WITH THINNED JUNCTIONS AND METHODS OF MANUFACTURE
92
Patent #:
Issue Dt:
03/05/2013
Application #:
13005599
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
07/19/2012
Title:
SYSTEM, METHOD AND PROGRAM STORAGE DEVICE FOR DEVELOPING CONDENSED NETLISTS REPRESENTATIVE OF GROUPS OF ACTIVE DEVICES IN AN INTEGRATED CIRCUIT AND FOR MODELING THE PERFORMANCE OF THE INTEGRATED CIRCUIT BASED ON THE CONDENSED NETLISTS
93
Patent #:
Issue Dt:
05/15/2012
Application #:
13005821
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
06/16/2011
Title:
SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE
94
Patent #:
Issue Dt:
08/02/2016
Application #:
13005883
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
07/19/2012
Title:
INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS
95
Patent #:
Issue Dt:
01/03/2012
Application #:
13005894
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
05/12/2011
Title:
SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS
96
Patent #:
Issue Dt:
10/01/2013
Application #:
13006081
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
07/19/2012
Title:
RADIATION HARDENED TRANSISTORS BASED ON GRAPHENE AND CARBON NANOTUBES
97
Patent #:
Issue Dt:
12/17/2013
Application #:
13006148
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
01/05/2012
Title:
TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET AND SUPERIOR UNIFORMITY
98
Patent #:
Issue Dt:
02/25/2014
Application #:
13006522
Filing Dt:
01/14/2011
Publication #:
Pub Dt:
01/05/2012
Title:
METHOD AND SYSTEM FOR EXCURSION MONITORING IN OPTICAL LITHOGRAPHY PROCESSES IN MICRO DEVICE FABRICATION
99
Patent #:
Issue Dt:
11/12/2013
Application #:
13006656
Filing Dt:
01/14/2011
Publication #:
Pub Dt:
07/19/2012
Title:
REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
100
Patent #:
Issue Dt:
06/04/2013
Application #:
13006664
Filing Dt:
01/14/2011
Publication #:
Pub Dt:
07/19/2012
Title:
METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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