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10/02/2012
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12963246
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12/08/2010
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06/14/2012
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Title:
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CREATING SCAN CHAIN DEFINITION FROM HIGH-LEVEL MODEL USING HIGH-LEVEL MODEL SIMULATION
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04/09/2013
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12963314
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12/08/2010
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06/14/2012
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Title:
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NARROW-BAND WIDE-RANGE FREQUENCY MODULATION CONTINUOUS WAVE (FMCW) RADAR SYSTEM
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05/28/2013
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12963364
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12/08/2010
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Pub Dt:
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11/03/2011
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Title:
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SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND SEMICONDUCTOR RESISTORS FORMED ON THE BASIS OF A REPLACEMENT GATE APPROACH
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11/20/2012
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12963677
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12/09/2010
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06/14/2012
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Title:
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MULTISTAGE, HYBRID SYNTHESIS PROCESSING FACILITATING INTEGRATED CIRCUIT LAYOUT
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04/23/2013
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12963753
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12/09/2010
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11/03/2011
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Title:
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STRESS MEMORIZATION WITH REDUCED FRINGING CAPACITANCE BASED ON SILICON NITRIDE IN MOS SEMICONDUCTOR DEVICES
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05/22/2012
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12963908
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12/09/2010
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Pub Dt:
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11/03/2011
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Title:
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REDUCED DEFECTIVITY IN CONTACTS OF A SEMICONDUCTOR DEVICE COMPRISING REPLACEMENT GATE ELECTRODE STRUCTURES BY USING AN INTERMEDIATE CAP LAYER
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08/20/2013
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12964082
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12/09/2010
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06/14/2012
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Title:
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PSEUDO BUTTED JUNCTION STRUCTURE FOR BACK PLANE CONNECTION
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05/08/2012
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12964136
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12/09/2010
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11/03/2011
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Title:
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REDUCED STI TOPOGRAPHY IN HIGH-K METAL GATE TRANSISTORS BY USING A MASK AFTER CHANNEL SEMICONDUCTOR ALLOY DEPOSITION
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10/15/2013
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12964340
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12/09/2010
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06/14/2012
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Title:
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ADDING SCALABILITY AND FAULT TOLERANCE TO GENERIC FINITE STATE MACHINE FRAMEWORKS FOR USE IN AUTOMATED INCIDENT MANAGEMENT OF CLOUD COMPUTING INFRASTRUCTURES
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08/13/2013
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12964359
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12/09/2010
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Pub Dt:
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12/01/2011
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Title:
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CHIP PACKAGE INCLUDING MULTIPLE SECTIONS FOR REDUCING CHIP PACKAGE INTERACTION
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07/30/2013
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12964448
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12/09/2010
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12/01/2011
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Title:
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STRESS REDUCTION IN CHIP PACKAGING BY A STRESS COMPENSATION REGION FORMED AROUND THE CHIP
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12/25/2012
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12964807
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12/10/2010
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06/14/2012
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Title:
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ASYNCHRONOUS DELETION OF A RANGE OF MESSAGES PROCESSED BY A PARALLEL DATABASE REPLICATION APPLY PROCESS
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10/04/2011
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12964831
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12/10/2010
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Title:
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TEMPORARY ETCHABLE LINER FOR FORMING AIR GAP
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01/27/2015
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12965118
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12/10/2010
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Pub Dt:
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12/01/2011
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Title:
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Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth
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02/03/2015
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12965212
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12/10/2010
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12/01/2011
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Title:
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Semiconductor Device Comprising a Buried Capacitor Formed in the Contact Level
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03/18/2014
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12965341
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12/10/2010
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Pub Dt:
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01/05/2012
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Title:
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TEST STRUCTURE FOR CONTROLLING THE INCORPORATION OF SEMICONDUCTOR ALLOYS IN TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES
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12/11/2012
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12965488
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12/10/2010
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Pub Dt:
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01/05/2012
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Title:
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CONTROL OF CRITICAL DIMENSIONS IN OPTICAL IMAGING PROCESSES FOR SEMICONDUCTOR PRODUCTION BY EXTRACTING IMAGING IMPERFECTIONS ON THE BASIS OF IMAGING TOOL SPECIFIC INTENSITY MEASUREMENTS AND SIMULATIONS
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07/22/2014
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12966302
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12/13/2010
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01/05/2012
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Title:
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Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction
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12/17/2013
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12967114
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12/14/2010
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Pub Dt:
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06/14/2012
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Title:
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SELF-PROTECTED ELECTROSTATIC DISCHARGE FIELD EFFECT TRANSISTOR (SPESDFET), AN INTEGRATED CIRCUIT INCORPORATING THE SPESDFET AS AN INPUT/OUTPUT (I/O) PAD DRIVER AND ASSOCIATED METHODS OF FORMING THE SPESDFET AND THE INTEGRATED CIRCUIT
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08/20/2013
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12967268
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12/14/2010
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Pub Dt:
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12/22/2011
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Title:
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TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
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11/19/2013
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12967308
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12/14/2010
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Pub Dt:
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06/14/2012
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Title:
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ELECTRICAL FUSE WITH A CURRENT SHUNT
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04/15/2014
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12967329
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12/14/2010
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Pub Dt:
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06/14/2012
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Title:
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PARTIALLY DEPLETED (PD) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (VT) LOWERING AND METHOD OF FORMING THE STRUCTURE
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06/17/2014
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12967625
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12/14/2010
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06/14/2012
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Title:
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METHOD OF FABRICATING PHOTOCONDUCTOR-ON-ACTIVE PIXEL DEVICE
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12/16/2014
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12967771
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12/14/2010
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06/14/2012
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Title:
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DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY
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02/10/2015
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12968068
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12/14/2010
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06/14/2012
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Title:
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SEMICONDUCTOR DEVICES HAVING THROUGH-CONTACTS AND RELATED FABRICATION METHODS
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02/25/2014
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12968864
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12/15/2010
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06/21/2012
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STRESS TESTING OF SILICON-ON-INSULATOR SUBSTRATES USING APPLIED ELECTROSTATIC DISCHARGE
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05/21/2013
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12969004
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12/15/2010
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06/21/2012
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METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY
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11/19/2013
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12969969
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12/16/2010
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11/03/2011
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PLANARIZATION OF A MATERIAL SYSTEM IN A SEMICONDUCTOR DEVICE BY USING A NON-SELECTIVE IN SITU PREPARED SLURRY
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03/19/2013
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12970117
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12/16/2010
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01/05/2012
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Title:
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SOPHISTICATED METALLIZATION SYSTEMS IN SEMICONDUCTORS FORMED BY REMOVING DAMAGED DIELECTRIC SURFACE LAYERS AFTER FORMING THE METAL FEATURES
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12/03/2013
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12970553
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12/16/2010
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01/05/2012
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SEMICONDUCTOR DEVICE COMPRISING THROUGH HOLE VIAS HAVING A STRESS RELAXATION MECHANISM
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08/07/2012
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12972771
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12/20/2010
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04/14/2011
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HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME
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03/26/2013
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12972879
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12/20/2010
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06/21/2012
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
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03/05/2013
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12972934
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12/20/2010
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06/21/2012
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES
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12/25/2012
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12972980
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12/20/2010
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Pub Dt:
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06/21/2012
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS
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08/07/2012
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12973062
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12/20/2010
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04/14/2011
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COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION
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03/20/2012
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12973063
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12/20/2010
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08/25/2011
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FORMATION OF CARBON AND SEMICONDUCTOR NANOMATERIALS USING MOLECULAR ASSEMBLIES
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02/17/2015
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12973147
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12/20/2010
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Pub Dt:
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12/29/2011
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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04/01/2014
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12973285
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12/20/2010
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Pub Dt:
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12/29/2011
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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05/22/2012
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12973373
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12/20/2010
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Title:
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METHOD OF FABRICATING A CONDUCTIVE INTERCONNECT ARRANGEMENT FOR A SEMICONDUCTOR DEVICE
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10/23/2012
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12973377
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12/20/2010
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04/14/2011
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Title:
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BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
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05/13/2014
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12973430
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12/20/2010
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Pub Dt:
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12/29/2011
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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02/11/2014
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12974037
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12/21/2010
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06/21/2012
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Title:
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Encapsulation of Closely Spaced Gate Electrode Structures
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01/08/2013
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12974170
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12/21/2010
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Pub Dt:
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06/21/2012
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Title:
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MODEL LIBRARY IMPLEMENTATION AND METHODOLOGY FOR WORST CASE PERFORMANCE MODELING FOR SRAM CELLS
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06/12/2012
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12974451
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12/21/2010
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Pub Dt:
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04/21/2011
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Title:
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DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP
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Issue Dt:
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08/02/2016
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12974854
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12/21/2010
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Pub Dt:
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12/29/2011
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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02/04/2014
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12975327
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12/21/2010
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Pub Dt:
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06/21/2012
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Title:
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INTEGRATED CIRCUIT SYSTEM WITH REDUCED POLYSILICON RESIDUE AND METHOD OF MANUFACTURE THEREOF
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05/07/2013
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12975515
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12/22/2010
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Pub Dt:
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06/28/2012
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Title:
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ENHANCEMENT OF ULTRAVIOLET CURING OF TENSILE STRESS LINER USING REFLECTIVE MATERIALS
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Issue Dt:
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09/24/2013
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12975701
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12/22/2010
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Pub Dt:
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06/28/2012
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Title:
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INTEGRATED CIRCUIT FABRICATION METHODS UTILIZING EMBEDDED HARDMASK LAYERS FOR HIGH RESOLUTION PATTERNING
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10/22/2013
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12977134
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12/23/2010
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Pub Dt:
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04/21/2011
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ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT
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11/05/2013
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12982014
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12/30/2010
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Pub Dt:
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07/21/2011
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Title:
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MATERIALS AND METHODS FOR IMMOBILIZATION OF CATALYSTS ON SURFACES AND FOR SELECTIVE ELECTROLESS METALLIZATION
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03/20/2012
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12983297
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01/01/2011
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Pub Dt:
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06/02/2011
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Title:
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CHEMICAL TRIM OF PHOTORESIST LINES BY MEANS OF A TUNED OVERCOAT
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09/24/2013
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12983352
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01/03/2011
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07/05/2012
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SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS
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06/25/2013
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12983353
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01/03/2011
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07/05/2012
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STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS
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04/16/2013
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12983377
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01/03/2011
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04/28/2011
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METHOD FOR DIRECT HEAT SINK ATTACHMENT
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10/30/2012
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12983439
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01/03/2011
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Pub Dt:
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07/05/2012
| | | | |
Title:
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LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES
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Patent #:
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Issue Dt:
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09/09/2014
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Application #:
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12983477
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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05/12/2011
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Title:
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METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS
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Patent #:
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Issue Dt:
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06/17/2014
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Application #:
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12983489
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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01/15/2013
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Application #:
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12983552
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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04/28/2011
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Title:
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SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12983925
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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FIELD EFFECT TRANSISTOR HAVING OHMIC BODY CONTACT(S), AN INTEGRATED CIRCUIT STRUCTURE INCORPORATING STACKED FIELD EFFECT TRANSISTORS WITH SUCH OHMIC BODY CONTACTS AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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07/31/2012
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Application #:
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12983995
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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04/28/2011
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Title:
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CONTENT ADDRESSABLE MEMORY WITH CONCURRENT READ AND SEARCH/COMPARE OPERATIONS AT THE SAME MEMORY CELL
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Patent #:
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Issue Dt:
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05/27/2014
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Application #:
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12984180
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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ADVANCED ROUTING OF VEHICLE FLEETS
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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12984252
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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08/18/2011
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Title:
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CACHE DIRECTORY LOOK-UP RE-USE AS CONFLICT CHECK MECHANISM FOR SPECULATIVE MEMORY REQUESTS
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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12984308
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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07/14/2011
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Title:
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EVICT ON WRITE, A MANAGEMENT STRATEGY FOR A PREFETCH UNIT AND/OR FIRST LEVEL CACHE IN A MULTIPROCESSOR SYSTEM WITH SPECULATIVE EXECUTION
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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12984359
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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FLAT RESPONSE DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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12984653
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Filing Dt:
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01/05/2011
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Publication #:
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Pub Dt:
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05/12/2011
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Title:
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VERTICAL NANOWIRE FET DEVICES
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Patent #:
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Issue Dt:
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03/27/2012
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Application #:
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12984682
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Filing Dt:
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01/05/2011
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Publication #:
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Pub Dt:
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04/28/2011
| | | | |
Title:
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MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION
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Patent #:
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Issue Dt:
|
11/08/2011
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Application #:
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12985060
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Filing Dt:
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01/05/2011
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
Title:
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ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
|
05/26/2015
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Application #:
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12985443
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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12985456
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
Title:
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SUBSTRATE ANCHOR STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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12/24/2013
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Application #:
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12985462
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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VOLTAGE DRIVER FOR A VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
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Patent #:
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Issue Dt:
|
07/05/2016
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Application #:
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12985669
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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Structure and Method to Fabricate Resistor on FinFET Processes
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Patent #:
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Issue Dt:
|
03/20/2012
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Application #:
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12985726
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
Title:
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A SYSTEM FOR RECONFIGURING CACHE MEMORY HAVING AN ACCESS BIT ASSOCIATED WITH A SECTOR OF A LOWER-LEVEL CACHE MEMORY AND A GRANULARITY BIT ASSOCIATED WITH A SECTOR OF A HIGHER-LEVEL CACHE MEMORY
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Patent #:
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Issue Dt:
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12/09/2014
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Application #:
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12985840
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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02/11/2014
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Application #:
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12986266
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Filing Dt:
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01/07/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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CONDUCTIVE METAL AND DIFFUSION BARRIER SEED COMPOSITIONS, AND METHODS OF USE IN SEMICONDUCTOR AND INTERLEVEL DIELECTRIC SUBSTRATES
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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12986652
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Filing Dt:
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01/07/2011
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Publication #:
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Pub Dt:
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07/21/2011
| | | | |
Title:
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STORE-OPERATE-COHERENCE-ON-VALUE
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12987089
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Filing Dt:
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01/08/2011
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
Title:
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FOUR-TERMINAL RECONFIGURABLE DEVICES
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Patent #:
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Issue Dt:
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01/15/2013
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Application #:
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12987106
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Filing Dt:
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01/08/2011
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
Title:
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APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
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Patent #:
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Issue Dt:
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10/01/2013
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Application #:
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12987202
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Filing Dt:
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01/10/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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ALIGNMENT MARKS TO ENABLE 3D INTEGRATION
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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12987221
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Filing Dt:
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01/10/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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12987353
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Filing Dt:
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01/10/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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METHODS AND APPARATUS FOR DETECTION OF GASEOUS CORROSIVE CONTAMINANTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12988814
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Filing Dt:
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10/21/2010
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Publication #:
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Pub Dt:
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10/11/2012
| | | | |
Title:
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NON-WOVEN MEMBRANE BIOREACTOR AND ITS FOULING CONTROL METHOD
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13004007
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Filing Dt:
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01/10/2011
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Publication #:
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Pub Dt:
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09/08/2011
| | | | |
Title:
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MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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13004104
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Filing Dt:
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01/11/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 AND L2 LATCHES
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Patent #:
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Issue Dt:
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11/10/2015
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Application #:
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13004129
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Filing Dt:
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01/11/2011
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Publication #:
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Pub Dt:
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05/05/2011
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Title:
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A THREE-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT
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Patent #:
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Issue Dt:
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05/08/2012
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Application #:
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13004201
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Filing Dt:
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01/11/2011
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Title:
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PROCESS FOR EPITAXIALLY GROWING EPITAXIAL MATERIAL REGIONS
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Patent #:
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Issue Dt:
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03/12/2013
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Application #:
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13004471
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Filing Dt:
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01/11/2011
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Publication #:
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Pub Dt:
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05/26/2011
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Title:
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SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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13004883
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Filing Dt:
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01/12/2011
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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FLASH ANALOG TO DIGITAL CONVERTER WITH METHOD AND SYSTEM FOR DYNAMIC CALIBRATION
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Patent #:
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Issue Dt:
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05/07/2013
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Application #:
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13005089
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Filing Dt:
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01/12/2011
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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13005201
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Filing Dt:
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01/12/2011
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Publication #:
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Pub Dt:
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05/12/2011
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Title:
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DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/19/2013
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Application #:
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13005246
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Filing Dt:
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01/12/2011
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Publication #:
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Pub Dt:
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05/12/2011
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Title:
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METHOD AND APPARATUS FOR OPTICAL MODULATION
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Patent #:
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Issue Dt:
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03/11/2014
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Application #:
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13005560
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Filing Dt:
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01/13/2011
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Publication #:
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Pub Dt:
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07/19/2012
| | | | |
Title:
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SEMICONDUCTOR STRUCTURES WITH THINNED JUNCTIONS AND METHODS OF MANUFACTURE
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Patent #:
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Issue Dt:
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03/05/2013
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Application #:
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13005599
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Filing Dt:
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01/13/2011
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Publication #:
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Pub Dt:
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07/19/2012
| | | | |
Title:
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SYSTEM, METHOD AND PROGRAM STORAGE DEVICE FOR DEVELOPING CONDENSED NETLISTS REPRESENTATIVE OF GROUPS OF ACTIVE DEVICES IN AN INTEGRATED CIRCUIT AND FOR MODELING THE PERFORMANCE OF THE INTEGRATED CIRCUIT BASED ON THE CONDENSED NETLISTS
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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13005821
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Filing Dt:
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01/13/2011
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Publication #:
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Pub Dt:
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06/16/2011
| | | | |
Title:
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SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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13005883
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Filing Dt:
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01/13/2011
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Publication #:
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Pub Dt:
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07/19/2012
| | | | |
Title:
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INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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13005894
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Filing Dt:
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01/13/2011
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Publication #:
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Pub Dt:
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05/12/2011
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Title:
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SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS
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Patent #:
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Issue Dt:
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10/01/2013
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Application #:
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13006081
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Filing Dt:
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01/13/2011
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Publication #:
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Pub Dt:
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07/19/2012
| | | | |
Title:
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RADIATION HARDENED TRANSISTORS BASED ON GRAPHENE AND CARBON NANOTUBES
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13006148
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Filing Dt:
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01/13/2011
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Publication #:
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Pub Dt:
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01/05/2012
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Title:
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TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET AND SUPERIOR UNIFORMITY
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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13006522
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Filing Dt:
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01/14/2011
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Publication #:
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Pub Dt:
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01/05/2012
| | | | |
Title:
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METHOD AND SYSTEM FOR EXCURSION MONITORING IN OPTICAL LITHOGRAPHY PROCESSES IN MICRO DEVICE FABRICATION
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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13006656
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Filing Dt:
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01/14/2011
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Publication #:
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Pub Dt:
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07/19/2012
| | | | |
Title:
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REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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13006664
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Filing Dt:
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01/14/2011
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Publication #:
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Pub Dt:
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07/19/2012
| | | | |
Title:
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METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE
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