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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 81 of 146
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1
Patent #:
8354659
Issue Dt:
01/15/2013
Application #:
13150705
Filing Dt:
06/01/2011
Publication #:
US20110227021
Pub Dt:
09/22/2011
Title:
POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL
2
Patent #:
8381150
Issue Dt:
02/19/2013
Application #:
13151295
Filing Dt:
06/02/2011
Publication #:
US20120311515
Pub Dt:
12/06/2012
Title:
METHOD FOR PERFORMING A PARALLEL STATIC TIMING ANALYSIS USING THREAD-SPECIFIC SUB-GRAPHS
3
Patent #:
8381147
Issue Dt:
02/19/2013
Application #:
13151313
Filing Dt:
06/02/2011
Publication #:
US20120311518
Pub Dt:
12/06/2012
Title:
METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION
4
Patent #:
8862417
Issue Dt:
10/14/2014
Application #:
13151337
Filing Dt:
06/02/2011
Publication #:
US20120310574
Pub Dt:
12/06/2012
Title:
SYSTEMS AND METHODS FOR DETERMINING ADJUSTABLE WAFER ACCEPTANCE CRITERIA BASED ON CHIP CHARACTERISTICS
5
Patent #:
8901664
Issue Dt:
12/02/2014
Application #:
13151525
Filing Dt:
06/02/2011
Publication #:
US20110227165
Pub Dt:
09/22/2011
Title:
HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
6
Patent #:
8564917
Issue Dt:
10/22/2013
Application #:
13151898
Filing Dt:
06/02/2011
Publication #:
US20120307405
Pub Dt:
12/06/2012
Title:
INTEGRATED CIRCUIT HAVING ELECTROSTATIC DISCHARGE PROTECTION
7
Patent #:
8507351
Issue Dt:
08/13/2013
Application #:
13152350
Filing Dt:
06/03/2011
Publication #:
US20110230039
Pub Dt:
09/22/2011
Title:
DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
8
Patent #:
8119466
Issue Dt:
02/21/2012
Application #:
13153051
Filing Dt:
06/03/2011
Publication #:
US20110256675
Pub Dt:
10/20/2011
Title:
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
9
Patent #:
8617915
Issue Dt:
12/31/2013
Application #:
13153381
Filing Dt:
06/03/2011
Publication #:
US20120070936
Pub Dt:
03/22/2012
Title:
ANNEALING THIN FILMS
10
Patent #:
8766410
Issue Dt:
07/01/2014
Application #:
13153806
Filing Dt:
06/06/2011
Publication #:
US20110233634
Pub Dt:
09/29/2011
Title:
EMBEDDED DRAM INTEGRATED CIRCUITS WITH EXTREMELY THIN SILICON-ON-INSULATOR PASS TRANSISTORS
11
Patent #:
8697557
Issue Dt:
04/15/2014
Application #:
13154521
Filing Dt:
06/07/2011
Publication #:
US20120313187
Pub Dt:
12/13/2012
Title:
Method of Removing Gate Cap Materials While Protecting Active Area
12
Patent #:
8941182
Issue Dt:
01/27/2015
Application #:
13154548
Filing Dt:
06/07/2011
Publication #:
US20120313176
Pub Dt:
12/13/2012
Title:
BURIED SUBLEVEL METALLIZATIONS FOR IMPROVED TRANSISTOR DENSITY
13
Patent #:
8664103
Issue Dt:
03/04/2014
Application #:
13154578
Filing Dt:
06/07/2011
Publication #:
US20120315749
Pub Dt:
12/13/2012
Title:
Metal Gate Stack Formation for Replacement Gate Technology
14
Patent #:
8835900
Issue Dt:
09/16/2014
Application #:
13154677
Filing Dt:
06/07/2011
Publication #:
US20120313143
Pub Dt:
12/13/2012
Title:
HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT
15
Patent #:
8722511
Issue Dt:
05/13/2014
Application #:
13154754
Filing Dt:
06/07/2011
Publication #:
US20120025318
Pub Dt:
02/02/2012
Title:
REDUCED TOPOGRAPHY IN ISOLATION REGIONS OF A SEMICONDUCTOR DEVICE BY APPLYING A DEPOSITION/ETCH SEQUENCE PRIOR TO FORMING THE INTERLAYER DIELECTRIC
16
Patent #:
8791009
Issue Dt:
07/29/2014
Application #:
13154905
Filing Dt:
06/07/2011
Publication #:
US20120315753
Pub Dt:
12/13/2012
Title:
METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
17
Patent #:
8536032
Issue Dt:
09/17/2013
Application #:
13155878
Filing Dt:
06/08/2011
Publication #:
US20120313168
Pub Dt:
12/13/2012
Title:
FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION
18
Patent #:
8283233
Issue Dt:
10/09/2012
Application #:
13156170
Filing Dt:
06/08/2011
Publication #:
US20110233627
Pub Dt:
09/29/2011
Title:
MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME
19
Patent #:
8460984
Issue Dt:
06/11/2013
Application #:
13156578
Filing Dt:
06/09/2011
Publication #:
US20120313169
Pub Dt:
12/13/2012
Title:
FIN-FET DEVICE AND METHOD AND INTEGRATED CIRCUITS USING SUCH
20
Patent #:
8162200
Issue Dt:
04/24/2012
Application #:
13156736
Filing Dt:
06/09/2011
Publication #:
US20110233262
Pub Dt:
09/29/2011
Title:
MICRO-FLUIDIC INJECTION MOLDED SOLDER (IMS)
21
Patent #:
8963657
Issue Dt:
02/24/2015
Application #:
13156935
Filing Dt:
06/09/2011
Publication #:
US20120313736
Pub Dt:
12/13/2012
Title:
ON-CHIP SLOW-WAVE THROUGH-SILICON VIA COPLANAR WAVEGUIDE STRUCTURES, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
22
Patent #:
8402398
Issue Dt:
03/19/2013
Application #:
13157909
Filing Dt:
06/10/2011
Publication #:
US20120317523
Pub Dt:
12/13/2012
Title:
REDUCING THROUGH PROCESS DELAY VARIATION IN METAL WIRES
23
Patent #:
8774228
Issue Dt:
07/08/2014
Application #:
13157968
Filing Dt:
06/10/2011
Publication #:
US20120314721
Pub Dt:
12/13/2012
Title:
TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY
24
Patent #:
8640062
Issue Dt:
01/28/2014
Application #:
13157980
Filing Dt:
06/10/2011
Publication #:
US20120317529
Pub Dt:
12/13/2012
Title:
Rapid Estimation of Temperature Rise in Wires Due to Joule Heating
25
Patent #:
8405187
Issue Dt:
03/26/2013
Application #:
13158048
Filing Dt:
06/10/2011
Publication #:
US20110241161
Pub Dt:
10/06/2011
Title:
CHIP PACKAGE WITH CHANNEL STIFFENER FRAME
26
Patent #:
8552783
Issue Dt:
10/08/2013
Application #:
13158079
Filing Dt:
06/10/2011
Publication #:
US20120313683
Pub Dt:
12/13/2012
Title:
PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR
27
Patent #:
8664115
Issue Dt:
03/04/2014
Application #:
13158114
Filing Dt:
06/10/2011
Publication #:
US20120315755
Pub Dt:
12/13/2012
Title:
COPPER INTERCONNECT WITH METAL HARDMASK REMOVAL
28
Patent #:
8531001
Issue Dt:
09/10/2013
Application #:
13158419
Filing Dt:
06/12/2011
Publication #:
US20120313216
Pub Dt:
12/13/2012
Title:
COMPLEMENTARY BIPOLAR INVERTER
29
Patent #:
8526220
Issue Dt:
09/03/2013
Application #:
13158420
Filing Dt:
06/12/2011
Publication #:
US20120314485
Pub Dt:
12/13/2012
Title:
COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A LOW-VOLTAGE CMOS PLATFORM
30
Patent #:
8365117
Issue Dt:
01/29/2013
Application #:
13158562
Filing Dt:
06/13/2011
Publication #:
US20120317530
Pub Dt:
12/13/2012
Title:
SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE
31
Patent #:
8227180
Issue Dt:
07/24/2012
Application #:
13158901
Filing Dt:
06/13/2011
Publication #:
US20110256486
Pub Dt:
10/20/2011
Title:
PHOTOLITHOGRAPHY FOCUS IMPROVEMENT BY REDUCTION OF AUTOFOCUS RADIATION TRANSMISSION INTO SUBSTRATE
32
Patent #:
8767531
Issue Dt:
07/01/2014
Application #:
13159580
Filing Dt:
06/14/2011
Publication #:
US20120151247
Pub Dt:
06/14/2012
Title:
DYNAMIC FAULT DETECTION AND REPAIR IN A DATA COMMUNICATIONS MECHANISM
33
Patent #:
8344351
Issue Dt:
01/01/2013
Application #:
13159594
Filing Dt:
06/14/2011
Publication #:
US20110240944
Pub Dt:
10/06/2011
Title:
PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL
34
Patent #:
8841203
Issue Dt:
09/23/2014
Application #:
13159877
Filing Dt:
06/14/2011
Publication #:
US20120322230
Pub Dt:
12/20/2012
Title:
METHOD FOR FORMING TWO DEVICE WAFERS FROM A SINGLE BASE SUBSTRATE UTILIZING A CONTROLLED SPALLING PROCESS
35
Patent #:
8709914
Issue Dt:
04/29/2014
Application #:
13159893
Filing Dt:
06/14/2011
Publication #:
US20120322227
Pub Dt:
12/20/2012
Title:
METHOD FOR CONTROLLED LAYER TRANSFER
36
Patent #:
8927318
Issue Dt:
01/06/2015
Application #:
13160067
Filing Dt:
06/14/2011
Publication #:
US20120318334
Pub Dt:
12/20/2012
Title:
SPALLING METHODS TO FORM MULTI-JUNCTION PHOTOVOLTAIC STRUCTURE
37
Patent #:
8660878
Issue Dt:
02/25/2014
Application #:
13160734
Filing Dt:
06/15/2011
Publication #:
US20120323624
Pub Dt:
12/20/2012
Title:
MODEL-DRIVEN ASSIGNMENT OF WORK TO A SOFTWARE FACTORY
38
Patent #:
8551833
Issue Dt:
10/08/2013
Application #:
13161013
Filing Dt:
06/15/2011
Publication #:
US20120319178
Pub Dt:
12/20/2012
Title:
DOUBLE GATE PLANAR FIELD EFFECT TRANSISTORS
39
Patent #:
8628996
Issue Dt:
01/14/2014
Application #:
13161163
Filing Dt:
06/15/2011
Publication #:
US20120318342
Pub Dt:
12/20/2012
Title:
UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS
40
Patent #:
9040392
Issue Dt:
05/26/2015
Application #:
13161260
Filing Dt:
06/15/2011
Publication #:
US20120322244
Pub Dt:
12/20/2012
Title:
METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE
41
Patent #:
8445316
Issue Dt:
05/21/2013
Application #:
13162712
Filing Dt:
06/17/2011
Publication #:
US20120322200
Pub Dt:
12/20/2012
Title:
NON-LITHOGRAPHIC METHOD OF PATTERNING CONTACTS FOR A PHOTOVOLTAIC DEVICE
42
Patent #:
8772154
Issue Dt:
07/08/2014
Application #:
13163495
Filing Dt:
06/17/2011
Publication #:
US20120319285
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF
43
Patent #:
8595676
Issue Dt:
11/26/2013
Application #:
13163700
Filing Dt:
06/19/2011
Publication #:
US20120324414
Pub Dt:
12/20/2012
Title:
BDD-BASED FUNCTIONAL MODELING
44
Patent #:
8470628
Issue Dt:
06/25/2013
Application #:
13164126
Filing Dt:
06/20/2011
Publication #:
US20120318649
Pub Dt:
12/20/2012
Title:
Methods to Fabricate Silicide Micromechanical Device
45
Patent #:
8421126
Issue Dt:
04/16/2013
Application #:
13164173
Filing Dt:
06/20/2011
Publication #:
US20110241082
Pub Dt:
10/06/2011
Title:
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
46
Patent #:
9034753
Issue Dt:
05/19/2015
Application #:
13164272
Filing Dt:
06/20/2011
Publication #:
US20120322225
Pub Dt:
12/20/2012
Title:
Method of Forming Conductive Contacts on a Semiconductor Device with Embedded Memory and the Resulting Device
47
Patent #:
8492290
Issue Dt:
07/23/2013
Application #:
13164891
Filing Dt:
06/21/2011
Publication #:
US20120329230
Pub Dt:
12/27/2012
Title:
FABRICATION OF SILICON OXIDE AND OXYNITRIDE HAVING SUB-NANOMETER THICKNESS
48
Patent #:
8492279
Issue Dt:
07/23/2013
Application #:
13164899
Filing Dt:
06/21/2011
Publication #:
US20120028472
Pub Dt:
02/02/2012
Title:
METHOD OF CONTROLLING CRITICAL DIMENSIONS OF VIAS IN A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE DURING SILICON-ARC ETCH
49
Patent #:
8420531
Issue Dt:
04/16/2013
Application #:
13164929
Filing Dt:
06/21/2011
Publication #:
US20120326311
Pub Dt:
12/27/2012
Title:
ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES
50
Patent #:
8665575
Issue Dt:
03/04/2014
Application #:
13166842
Filing Dt:
06/23/2011
Publication #:
US20110317324
Pub Dt:
12/29/2011
Title:
SOLAR MODULE WITH OVERHEAT PROTECTION
51
Patent #:
8916919
Issue Dt:
12/23/2014
Application #:
13167076
Filing Dt:
06/23/2011
Publication #:
US20120326270
Pub Dt:
12/27/2012
Title:
INTERDIGITATED VERTICAL NATIVE CAPACITOR
52
Patent #:
8487425
Issue Dt:
07/16/2013
Application #:
13167107
Filing Dt:
06/23/2011
Publication #:
US20120326309
Pub Dt:
12/27/2012
Title:
OPTIMIZED ANNULAR COPPER TSV
53
Patent #:
8735283
Issue Dt:
05/27/2014
Application #:
13167176
Filing Dt:
06/23/2011
Publication #:
US20120329272
Pub Dt:
12/27/2012
Title:
METHOD FOR FORMING SMALL DIMENSION OPENINGS IN THE ORGANIC MASKING LAYER OF TRI-LAYER LITHOGRAPHY
54
Patent #:
8232151
Issue Dt:
07/31/2012
Application #:
13167303
Filing Dt:
06/23/2011
Publication #:
US20110254059
Pub Dt:
10/20/2011
Title:
STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
55
Patent #:
8569143
Issue Dt:
10/29/2013
Application #:
13167558
Filing Dt:
06/23/2011
Publication #:
US20120329239
Pub Dt:
12/27/2012
Title:
METHODS OF FABRICATING A SEMICONDUCTOR IC HAVING A HARDENED SHALLOW TRENCH ISOLATION (STI)
56
Patent #:
8407656
Issue Dt:
03/26/2013
Application #:
13167826
Filing Dt:
06/24/2011
Publication #:
US20120326752
Pub Dt:
12/27/2012
Title:
DESIGN METHOD AND STRUCTURE FOR A TRANSISTOR HAVING A RELATIVELY LARGE THRESHOLD VOLTAGE VARIATION RANGE AND FOR A RANDOM NUMBER GENERATOR INCORPORATING MULTIPLE ESSENTIALLY IDENTICAL TRANSISTORS HAVING SUCH A LARGE THRESHOLD VOLTAGE VARIATION RANGE
57
Patent #:
8586423
Issue Dt:
11/19/2013
Application #:
13168232
Filing Dt:
06/24/2011
Publication #:
US20120326766
Pub Dt:
12/27/2012
Title:
SILICON CONTROLLED RECTIFIER WITH STRESS-ENHANCED ADJUSTABLE TRIGGER VOLTAGE
58
Patent #:
8860191
Issue Dt:
10/14/2014
Application #:
13168512
Filing Dt:
06/24/2011
Publication #:
US20120326798
Pub Dt:
12/27/2012
Title:
ON-CHIP TRANSMISSION LINE STRUCTURES WITH BALANCED PHASE DELAY
59
Patent #:
8324102
Issue Dt:
12/04/2012
Application #:
13169248
Filing Dt:
06/27/2011
Publication #:
US20110256720
Pub Dt:
10/20/2011
Title:
TECHNIQUES FOR IMPEDING REVERSE ENGINEERING
60
Patent #:
8431455
Issue Dt:
04/30/2013
Application #:
13169360
Filing Dt:
06/27/2011
Publication #:
US20120329220
Pub Dt:
12/27/2012
Title:
METHOD OF IMPROVING MEMORY CELL DEVICE BY ION IMPLANTATION
61
Patent #:
8891328
Issue Dt:
11/18/2014
Application #:
13169485
Filing Dt:
06/27/2011
Publication #:
US20120327700
Pub Dt:
12/27/2012
Title:
LOW VOLTAGE METAL GATE ANTIFUSE WITH DEPLETION MODE MOSFET
62
Patent #:
8432002
Issue Dt:
04/30/2013
Application #:
13170565
Filing Dt:
06/28/2011
Publication #:
US20130001706
Pub Dt:
01/03/2013
Title:
METHOD AND STRUCTURE FOR LOW RESISTIVE SOURCE AND DRAIN REGIONS IN A REPLACEMENT METAL GATE PROCESS FLOW
63
Patent #:
8569116
Issue Dt:
10/29/2013
Application #:
13171228
Filing Dt:
06/28/2011
Publication #:
US20130001741
Pub Dt:
01/03/2013
Title:
INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD
64
Patent #:
8631371
Issue Dt:
01/14/2014
Application #:
13171528
Filing Dt:
06/29/2011
Publication #:
US20130007686
Pub Dt:
01/03/2013
Title:
METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR MODELING THE CAPACITANCE ASSOCIATED WITH A DIFFUSION REGION OF A SILICON-ON-INSULATOR DEVICE
65
Patent #:
8359556
Issue Dt:
01/22/2013
Application #:
13171530
Filing Dt:
06/29/2011
Publication #:
US20130007674
Pub Dt:
01/03/2013
Title:
RESOLVING DOUBLE PATTERNING CONFLICTS
66
Patent #:
8940634
Issue Dt:
01/27/2015
Application #:
13171657
Filing Dt:
06/29/2011
Publication #:
US20130001786
Pub Dt:
01/03/2013
Title:
OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE
67
Patent #:
8586482
Issue Dt:
11/19/2013
Application #:
13171868
Filing Dt:
06/29/2011
Publication #:
US20130001750
Pub Dt:
01/03/2013
Title:
FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION
68
Patent #:
8637372
Issue Dt:
01/28/2014
Application #:
13172635
Filing Dt:
06/29/2011
Publication #:
US20130005103
Pub Dt:
01/03/2013
Title:
METHODS FOR FABRICATING A FINFET INTEGRATED CIRCUIT ON A BULK SILICON SUBSTRATE
69
Patent #:
8748296
Issue Dt:
06/10/2014
Application #:
13172793
Filing Dt:
06/29/2011
Publication #:
US20130005116
Pub Dt:
01/03/2013
Title:
EDGE-EXCLUSION SPALLING METHOD FOR IMPROVING SUBSTRATE REUSABILITY
70
Patent #:
8599966
Issue Dt:
12/03/2013
Application #:
13173434
Filing Dt:
06/30/2011
Publication #:
US20130002347
Pub Dt:
01/03/2013
Title:
COUPLING SYSTEM FOR DATA RECEIVERS
71
Patent #:
8431472
Issue Dt:
04/30/2013
Application #:
13174257
Filing Dt:
06/30/2011
Publication #:
US20130005131
Pub Dt:
01/03/2013
Title:
SEMICONDUCTOR DEVICE FABRICATION USING GATE SUBSTITUTION
72
Patent #:
8456006
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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