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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 82 of 146
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Patent #:	8261226	Issue Dt:	09/04/2012	Application #:	13187196	Filing Dt:	07/20/2011
Title:	NETWORK FLOW BASED MODULE BOTTOM SURFACE METAL PIN ASSIGNMENT

Patent #:	8920027	Issue Dt:	12/30/2014	Application #:	13187203	Filing Dt:	07/20/2011
Publication #:	US20120051392	Pub Dt:	03/01/2012
Title:	Assessing Thermal Mechanical Characteristics of Complex Semiconductor Devices by Integrated Heating Systems

Patent #:	8492171	Issue Dt:	07/23/2013	Application #:	13187562	Filing Dt:	07/21/2011
Publication #:	US20130020697	Pub Dt:	01/24/2013
Title:	TECHNIQUES AND STRUCTURES FOR TESTING INTEGRATED CIRCUITS IN FLIP-CHIP ASSEMBLIES

Patent #:	8728924	Issue Dt:	05/20/2014	Application #:	13187795	Filing Dt:	07/21/2011
Publication #:	US20120049286	Pub Dt:	03/01/2012
Title:	GATE ELECTRODES OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE IN COMBINATION WITH A SHRINK SPACER

Patent #:	8513738	Issue Dt:	08/20/2013	Application #:	13188094	Filing Dt:	07/21/2011
Publication #:	US20130020645	Pub Dt:	01/24/2013
Title:	ESD FIELD-EFFECT TRANSISTOR AND INTEGRATED DIFFUSION RESISTOR

Patent #:	8418120	Issue Dt:	04/09/2013	Application #:	13188129	Filing Dt:	07/21/2011
Publication #:	US20130024828	Pub Dt:	01/24/2013
Title:	SOLUTIONS FOR NETLIST REDUCTION FOR MULTI-FINGER DEVICES

Patent #:	8951901	Issue Dt:	02/10/2015	Application #:	13188745	Filing Dt:	07/22/2011
Publication #:	US20120086056	Pub Dt:	04/12/2012
Title:	SUPERIOR INTEGRITY OF A HIGH-K GATE STACK BY FORMING A CONTROLLED UNDERCUT ON THE BASIS OF A WET CHEMISTRY

Patent #:	8299570	Issue Dt:	10/30/2012	Application #:	13189016	Filing Dt:	07/22/2011
Publication #:	US20110272779	Pub Dt:	11/10/2011
Title:	EFUSE CONTAINING SIGE STACK

Patent #:	8614111	Issue Dt:	12/24/2013	Application #:	13189848	Filing Dt:	07/25/2011
Publication #:	US20130026544	Pub Dt:	01/31/2013
Title:	FULLY DEPLETED SILICON ON INSULATOR NEUTRON DETECTOR

Patent #:	8592244	Issue Dt:	11/26/2013	Application #:	13189961	Filing Dt:	07/25/2011
Publication #:	US20130026587	Pub Dt:	01/31/2013
Title:	PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING

Patent #:	9281200	Issue Dt:	03/08/2016	Application #:	13189997	Filing Dt:	07/25/2011
Publication #:	US20120156865	Pub Dt:	06/21/2012
Title:	ENHANCED PATTERNING UNIFORMITY OF GATE ELECTRODES OF A SEMICONDUCTOR DEVICE BY LATE GATE DOPING

Patent #:	8592103	Issue Dt:	11/26/2013	Application #:	13190270	Filing Dt:	07/25/2011
Publication #:	US20130029253	Pub Dt:	01/31/2013
Title:	EXTREME ULTRAVIOLET MASKS HAVING ANNEALED LIGHT-ABSORPTIVE BORDERS AND ASSOCIATED FABRICATION METHODS

Patent #:	8704229	Issue Dt:	04/22/2014	Application #:	13190566	Filing Dt:	07/26/2011
Publication #:	US20130026582	Pub Dt:	01/31/2013
Title:	PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION

Patent #:	8466018	Issue Dt:	06/18/2013	Application #:	13190940	Filing Dt:	07/26/2011
Publication #:	US20130029463	Pub Dt:	01/31/2013
Title:	METHODS OF FORMING A PMOS DEVICE WITH IN SITU DOPED EPITAXIAL SOURCE/DRAIN REGIONS

Patent #:	8497580	Issue Dt:	07/30/2013	Application #:	13191090	Filing Dt:	07/26/2011
Publication #:	US20110285021	Pub Dt:	11/24/2011
Title:	NOBLE METAL CAP FOR INTERCONNECT STRUCTURES

Patent #:	8383490	Issue Dt:	02/26/2013	Application #:	13191540	Filing Dt:	07/27/2011
Publication #:	US20130026570	Pub Dt:	01/31/2013
Title:	BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES

Patent #:	8327312	Issue Dt:	12/04/2012	Application #:	13191750	Filing Dt:	07/27/2011
Publication #:	US20120030643	Pub Dt:	02/02/2012
Title:	ASSESSING PRINTABILITY OF A VERY-LARGE-SCALE INTEGRATION DESIGN

Patent #:	8816929	Issue Dt:	08/26/2014	Application #:	13191917	Filing Dt:	07/27/2011
Publication #:	US20130027271	Pub Dt:	01/31/2013
Title:	ANTENNA ARRAY PACKAGE AND METHOD FOR BUILDING LARGE ARRAYS

Patent #:	8658050	Issue Dt:	02/25/2014	Application #:	13191985	Filing Dt:	07/27/2011
Publication #:	US20130026133	Pub Dt:	01/31/2013
Title:	Method to Transfer Lithographic Patterns Into Inorganic Substrates

Patent #:	8748275	Issue Dt:	06/10/2014	Application #:	13191993	Filing Dt:	07/27/2011
Publication #:	US20120156846	Pub Dt:	06/21/2012
Title:	Semiconductor Devices Comprising a Channel Semiconductor Alloy Formed with Reduced STI Topography

Patent #:	8525339	Issue Dt:	09/03/2013	Application #:	13191999	Filing Dt:	07/27/2011
Publication #:	US20130026635	Pub Dt:	01/31/2013
Title:	HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME

Patent #:	8778795	Issue Dt:	07/15/2014	Application #:	13192164	Filing Dt:	07/27/2011
Publication #:	US20120153480	Pub Dt:	06/21/2012
Title:	METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES COMPRISING A COPPER/SILICON COMPOUND AS A BARRIER MATERIAL

Patent #:	8736385	Issue Dt:	05/27/2014	Application #:	13192324	Filing Dt:	07/27/2011
Publication #:	US20130027139	Pub Dt:	01/31/2013
Title:	RING OSCILLATOR BASED VOLTAGE CONTROL OSCILLATOR HAVING LOW-JITTER AND WIDE BANDWIDTH

Patent #:	8586440	Issue Dt:	11/19/2013	Application #:	13192332	Filing Dt:	07/27/2011
Publication #:	US20130029464	Pub Dt:	01/31/2013
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING NON-OXIDIZING RESIST REMOVAL

Patent #:	8709902	Issue Dt:	04/29/2014	Application #:	13192567	Filing Dt:	07/28/2011
Publication #:	US20120156837	Pub Dt:	06/21/2012
Title:	SACRIFICIAL SPACER APPROACH FOR DIFFERENTIAL SOURCE/DRAIN IMPLANTATION SPACERS IN TRANSISTORS COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE

Patent #:	8664068	Issue Dt:	03/04/2014	Application #:	13192620	Filing Dt:	07/28/2011
Publication #:	US20120153399	Pub Dt:	06/21/2012
Title:	LOW-DIFFUSION DRAIN AND SOURCE REGIONS IN CMOS TRANSISTORS FOR LOW POWER/HIGH PERFORMANCE APPLICATIONS

Patent #:	8347259	Issue Dt:	01/01/2013	Application #:	13193721	Filing Dt:	07/29/2011
Title:	CIRCUIT ENHANCEMENT BY MULTIPLICATE-LAYER-HANDLING CIRCUIT SIMULATION

Patent #:	8691691	Issue Dt:	04/08/2014	Application #:	13194214	Filing Dt:	07/29/2011
Publication #:	US20130026606	Pub Dt:	01/31/2013
Title:	TSV PILLAR AS AN INTERCONNECTING STRUCTURE

Patent #:	8949083	Issue Dt:	02/03/2015	Application #:	13194644	Filing Dt:	07/29/2011
Publication #:	US20130030774	Pub Dt:	01/31/2013
Title:	MODELING GATE TRANSCONDUCTANCE IN A SUB-CIRCUIT TRANSISTOR MODEL

Patent #:	9159711	Issue Dt:	10/13/2015	Application #:	13194695	Filing Dt:	07/29/2011
Publication #:	US20130027127	Pub Dt:	01/31/2013
Title:	INTEGRATED CIRCUIT SYSTEMS INCLUDING VERTICAL INDUCTORS

Patent #:	8877593	Issue Dt:	11/04/2014	Application #:	13194980	Filing Dt:	07/31/2011
Publication #:	US20130026465	Pub Dt:	01/31/2013
Title:	SEMICONDUCTOR DEVICE INCLUDING AN ASYMMETRIC FEATURE, AND METHOD OF MAKING THE SAME

Patent #:	8611164	Issue Dt:	12/17/2013	Application #:	13195114	Filing Dt:	08/01/2011
Publication #:	US20130033948	Pub Dt:	02/07/2013
Title:	DEVICE AND METHOD FOR DETECTING RESISTIVE DEFECT

Patent #:	8872236	Issue Dt:	10/28/2014	Application #:	13195155	Filing Dt:	08/01/2011
Publication #:	US20110278570	Pub Dt:	11/17/2011
Title:	SCALING OF BIPOLAR TRANSISTORS

Patent #:	8207609	Issue Dt:	06/26/2012	Application #:	13195255	Filing Dt:	08/01/2011
Publication #:	US20110284280	Pub Dt:	11/24/2011
Title:	OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME

Patent #:	8404430	Issue Dt:	03/26/2013	Application #:	13195307	Filing Dt:	08/01/2011
Publication #:	US20110287349	Pub Dt:	11/24/2011
Title:	MULTI-CHIP RETICLE PHOTOMASKS

Patent #:	8120132	Issue Dt:	02/21/2012	Application #:	13196334	Filing Dt:	08/02/2011
Publication #:	US20110284073	Pub Dt:	11/24/2011
Title:	HOLEY ELECTRODE GRIDS FOR PHOTOVOLTAIC CELLS WITH SUBWAVELENGTH AND SUPERWAVELENGTH FEATURE SIZES

Patent #:	8373267	Issue Dt:	02/12/2013	Application #:	13196404	Filing Dt:	08/02/2011
Publication #:	US20110284925	Pub Dt:	11/24/2011
Title:	ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE

Patent #:	8536009	Issue Dt:	09/17/2013	Application #:	13197239	Filing Dt:	08/03/2011
Publication #:	US20120153401	Pub Dt:	06/21/2012
Title:	DIFFERENTIAL THRESHOLD VOLTAGE ADJUSTMENT IN PMOS TRANSISTORS BY DIFFERENTIAL FORMATION OF A CHANNEL SEMICONDUCTOR MATERIAL

Patent #:	8673710	Issue Dt:	03/18/2014	Application #:	13197387	Filing Dt:	08/03/2011
Publication #:	US20120156864	Pub Dt:	06/21/2012
Title:	FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY A NITRIDE HARD MASK LAYER AND AN OXIDE MASK

Patent #:	8299558	Issue Dt:	10/30/2012	Application #:	13197414	Filing Dt:	08/03/2011
Publication #:	US20110284961	Pub Dt:	11/24/2011
Title:	SELF-ALIGNED SCHOTTKY DIODE

Patent #:	8841732	Issue Dt:	09/23/2014	Application #:	13197631	Filing Dt:	08/03/2011
Publication #:	US20130032890	Pub Dt:	02/07/2013
Title:	SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES

Patent #:	8987144	Issue Dt:	03/24/2015	Application #:	13198107	Filing Dt:	08/04/2011
Publication #:	US20120161243	Pub Dt:	06/28/2012
Title:	HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY CAP LAYER REMOVAL WITHOUT SACRIFICIAL SPACER

Patent #:	9076817	Issue Dt:	07/07/2015	Application #:	13198152	Filing Dt:	08/04/2011
Publication #:	US20130032859	Pub Dt:	02/07/2013
Title:	EPITAXIAL EXTENSION CMOS TRANSISTOR

Patent #:	8343826	Issue Dt:	01/01/2013	Application #:	13198209	Filing Dt:	08/04/2011
Publication #:	US20120161250	Pub Dt:	06/28/2012
Title:	METHOD FOR FORMING A TRANSISTOR COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES INCLUDING A POLYCRYSTALLINE SEMICONDUCTOR MATERIAL AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS

Patent #:	9048261	Issue Dt:	06/02/2015	Application #:	13198255	Filing Dt:	08/04/2011
Publication #:	US20130032883	Pub Dt:	02/07/2013
Title:	FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING

Patent #:	8467260	Issue Dt:	06/18/2013	Application #:	13198894	Filing Dt:	08/05/2011
Publication #:	US20130033951	Pub Dt:	02/07/2013
Title:	STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A FUSEBAY

Patent #:	9117771	Issue Dt:	08/25/2015	Application #:	13202228	Filing Dt:	08/18/2011
Publication #:	US20110297869	Pub Dt:	12/08/2011
Title:	INSULATION MATERIAL FOR INTEGRATED CIRCUITS AND USE OF SAID INTEGRATED CIRCUITS

Patent #:	8497180	Issue Dt:	07/30/2013	Application #:	13204271	Filing Dt:	08/05/2011
Publication #:	US20130032864	Pub Dt:	02/07/2013
Title:	TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS

Patent #:	8524564	Issue Dt:	09/03/2013	Application #:	13204283	Filing Dt:	08/05/2011
Publication #:	US20130032901	Pub Dt:	02/07/2013
Title:	FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH

Patent #:	8266554	Issue Dt:	09/11/2012	Application #:	13204440	Filing Dt:	08/05/2011
Publication #:	US20120047471	Pub Dt:	02/23/2012
Title:	DYNAMIC PROVISIONAL DECOMPOSITION OF LITHOGRAPHIC PATTERNS HAVING DIFFERENT INTERACTION RANGES

Patent #:	8484543	Issue Dt:	07/09/2013	Application #:	13204929	Filing Dt:	08/08/2011
Publication #:	US20130042166	Pub Dt:	02/14/2013
Title:	FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD

Patent #:	9360858	Issue Dt:	06/07/2016	Application #:	13204955	Filing Dt:	08/08/2011
Publication #:	US20130041494	Pub Dt:	02/14/2013
Title:	ALIGNMENT DATA BASED PROCESS CONTROL SYSTEM

Patent #:	8728908	Issue Dt:	05/20/2014	Application #:	13205050	Filing Dt:	08/08/2011
Publication #:	US20130040450	Pub Dt:	02/14/2013
Title:	Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure

Patent #:	8525232	Issue Dt:	09/03/2013	Application #:	13206586	Filing Dt:	08/10/2011
Publication #:	US20130037865	Pub Dt:	02/14/2013
Title:	SEMICONDUCTOR STRUCTURE HAVING A WETTING LAYER

Patent #:	8853700	Issue Dt:	10/07/2014	Application #:	13207102	Filing Dt:	08/10/2011
Publication #:	US20130037864	Pub Dt:	02/14/2013
Title:	CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES

Patent #:	8212332	Issue Dt:	07/03/2012	Application #:	13207480	Filing Dt:	08/11/2011
Publication #:	US20110291238	Pub Dt:	12/01/2011
Title:	BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES

Patent #:	8310011	Issue Dt:	11/13/2012	Application #:	13208610	Filing Dt:	08/12/2011
Publication #:	US20120003818	Pub Dt:	01/05/2012
Title:	FIELD EFFECT RESISTOR FOR ESD PROTECTION

Patent #:	8563426	Issue Dt:	10/22/2013	Application #:	13208697	Filing Dt:	08/12/2011
Publication #:	US20120161327	Pub Dt:	06/28/2012
Title:	SHRINKAGE OF CONTACT ELEMENTS AND VIAS IN A SEMICONDUCTOR DEVICE BY INCORPORATING ADDITIONAL TAPERING MATERIAL

Patent #:	8536052	Issue Dt:	09/17/2013	Application #:	13208835	Filing Dt:	08/12/2011
Publication #:	US20120161324	Pub Dt:	06/28/2012
Title:	Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions

Patent #:	8877597	Issue Dt:	11/04/2014	Application #:	13208972	Filing Dt:	08/12/2011
Publication #:	US20120161210	Pub Dt:	06/28/2012
Title:	Embedding Metal Silicide Contact Regions Reliably Into Highly Doped Drain and Source Regions by a Stop Implantation

Patent #:	8722498	Issue Dt:	05/13/2014	Application #:	13209057	Filing Dt:	08/12/2011
Publication #:	US20120161238	Pub Dt:	06/28/2012
Title:	SELF-ALIGNED FIN TRANSISTOR FORMED ON A BULK SUBSTRATE BY LATE FIN ETCH

Patent #:	8873271	Issue Dt:	10/28/2014	Application #:	13209405	Filing Dt:	08/14/2011
Publication #:	US20130039110	Pub Dt:	02/14/2013
Title:	3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE

Patent #:	8830725	Issue Dt:	09/09/2014	Application #:	13209569	Filing Dt:	08/15/2011
Publication #:	US20130044532	Pub Dt:	02/21/2013
Title:	LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS

Patent #:	9018023	Issue Dt:	04/28/2015	Application #:	13210514	Filing Dt:	08/16/2011
Publication #:	US20130045546	Pub Dt:	02/21/2013
Title:	DETECTION OF SURFACE DEFECTS BY OPTICAL INLINE METROLOGY DURING Cu-CMP PROCESS

Patent #:	8841209	Issue Dt:	09/23/2014	Application #:	13212489	Filing Dt:	08/18/2011
Publication #:	US20130043060	Pub Dt:	02/21/2013
Title:	METHOD FOR FORMING CORELESS FLIP CHIP BALL GRID ARRAY (FCBGA) SUBSTRATES AND SUCH SUBSTRATES FORMED BY THE METHOD

Patent #:	8828489	Issue Dt:	09/09/2014	Application #:	13213740	Filing Dt:	08/19/2011
Publication #:	US20130045337	Pub Dt:	02/21/2013
Title:	HOMOGENEOUS MODIFICATION OF POROUS FILMS

Patent #:	8637412	Issue Dt:	01/28/2014	Application #:	13214157	Filing Dt:	08/19/2011
Publication #:	US20130043514	Pub Dt:	02/21/2013
Title:	PROCESS TO FORM AN ADHESION LAYER AND MULTIPHASE ULTRA-LOW K DIELECTRIC MATERIAL USING PECVD

Patent #:	8675475	Issue Dt:	03/18/2014	Application #:	13214818	Filing Dt:	08/22/2011
Publication #:	US20130051216	Pub Dt:	02/28/2013
Title:	TECHNIQUES FOR RECOVERY OF WIRELESS SERVICES FOLLOWING POWER FAILURES

Patent #:	8716077	Issue Dt:	05/06/2014	Application #:	13215635	Filing Dt:	08/23/2011
Publication #:	US20130049103	Pub Dt:	02/28/2013
Title:	REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL

Patent #:	8679943	Issue Dt:	03/25/2014	Application #:	13215738	Filing Dt:	08/23/2011
Publication #:	US20130052798	Pub Dt:	02/28/2013
Title:	FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS

Patent #:	8471343	Issue Dt:	06/25/2013	Application #:	13216708	Filing Dt:	08/24/2011
Publication #:	US20130049132	Pub Dt:	02/28/2013
Title:	PARASITIC CAPACITANCE REDUCTION IN MOSFET BY AIRGAP ILD

Patent #:	8476131	Issue Dt:	07/02/2013	Application #:	13216791	Filing Dt:	08/24/2011
Publication #:	US20130049126	Pub Dt:	02/28/2013
Title:	METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN REGIONS, AND A SEMICONDUCTOR DEVICE COMPRISING SAME

Patent #:	8647951	Issue Dt:	02/11/2014	Application #:	13216862	Filing Dt:	08/24/2011
Publication #:	US20130052782	Pub Dt:	02/28/2013
Title:	IMPLANTATION OF HYDROGEN TO IMPROVE GATE INSULATION LAYER-SUBSTRATE INTERFACE

Patent #:	8536034	Issue Dt:	09/17/2013	Application #:	13216921	Filing Dt:	08/24/2011
Publication #:	US20130052783	Pub Dt:	02/28/2013
Title:	METHODS OF FORMING STRESSED SILICON-CARBON AREAS IN AN NMOS TRANSISTOR

Patent #:	8580643	Issue Dt:	11/12/2013	Application #:	13217009	Filing Dt:	08/24/2011
Publication #:	US20130049121	Pub Dt:	02/28/2013
Title:	THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION

Patent #:	8759904	Issue Dt:	06/24/2014	Application #:	13217061	Filing Dt:	08/24/2011
Publication #:	US20130049136	Pub Dt:	02/28/2013
Title:	ELECTRONIC DEVICE HAVING PLURAL FIN-FETS WITH DIFFERENT FIN HEIGHTS AND PLANAR FETS ON THE SAME SUBSTRATE

Patent #:	8525569	Issue Dt:	09/03/2013	Application #:	13217335	Filing Dt:	08/25/2011
Publication #:	US20130049827	Pub Dt:	02/28/2013
Title:	SYNCHRONIZING GLOBAL CLOCKS IN 3D STACKS OF INTEGRATED CIRCUITS BY SHORTING THE CLOCK NETWORK

Patent #:	8576000	Issue Dt:	11/05/2013	Application #:	13217349	Filing Dt:	08/25/2011
Publication #:	US20130049824	Pub Dt:	02/28/2013
Title:	3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING

Patent #:	8381156	Issue Dt:	02/19/2013	Application #:	13217381	Filing Dt:	08/25/2011
Publication #:	US20130055183	Pub Dt:	02/28/2013
Title:	3D INTER-STRATUM CONNECTIVITY ROBUSTNESS

Patent #:	8587357	Issue Dt:	11/19/2013	Application #:	13217406	Filing Dt:	08/25/2011
Publication #:	US20130049828	Pub Dt:	02/28/2013
Title:	AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CLOCK SHIFTING

Patent #:	8516426	Issue Dt:	08/20/2013	Application #:	13217429	Filing Dt:	08/25/2011
Publication #:	US20130055185	Pub Dt:	02/28/2013
Title:	VERTICAL POWER BUDGETING AND SHIFTING FOR THREE-DIMENSIONAL INTEGRATION

Patent #:	8519735	Issue Dt:	08/27/2013	Application #:	13217734	Filing Dt:	08/25/2011
Publication #:	US20130049795	Pub Dt:	02/28/2013
Title:	PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STACK OF INTEGRATED CIRCUITS

Patent #:	8508001	Issue Dt:	08/13/2013	Application #:	13217792	Filing Dt:	08/25/2011
Publication #:	US20130049139	Pub Dt:	02/28/2013
Title:	SEMICONDUCTOR DEVICE WITH WORK FUNCTION ADJUSTING LAYER HAVING VARIED THICKNESS IN A GATE WIDTH DIRECTION AND METHODS OF MAKING SAME

Patent #:	8815736	Issue Dt:	08/26/2014	Application #:	13218089	Filing Dt:	08/25/2011
Publication #:	US20130052819	Pub Dt:	02/28/2013
Title:	Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures

Patent #:	8853810	Issue Dt:	10/07/2014	Application #:	13218262	Filing Dt:	08/25/2011
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Title:	INTEGRATED CIRCUITS THAT INCLUDE DEEP TRENCH CAPACITORS AND METHODS FOR THEIR FABRICATION

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Title:	BOND PAD CONFIGURATIONS FOR CONTROLLING SEMICONDUCTOR CHIP PACKAGE INTERACTIONS

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Title:	METHODS OF FORMING AN ANODE AND A CATHODE OF A SUBSTRATE DIODE BY PERFORMING ANGLED ION IMPLANTATION PROCESSES

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Title:	TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE

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Title:	STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR

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Title:	FORMATION OF METAL NANOSPHERES AND MICROSPHERES

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Title:	REMOVAL OF ALKALINE CRYSTAL DEFECTS IN LITHOGRAPHIC PATTERNING

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Title:	Multiple Patterning Layout Decomposition for Ease of Conflict Removal

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Title:	METHOD AND APPARATUS FOR CHARACTERIZING DISCONTINUITIES IN SEMICONDUCTOR DEVICES

100

Patent #:	8642998	Issue Dt:	02/04/2014	Application #:	13224765	Filing Dt:	09/02/2011
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Title:	ARRAY OF QUANTUM SYSTEMS IN A CAVITY FOR QUANTUM COMPUTING

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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