|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
13224768
|
Filing Dt:
|
09/02/2011
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
MODULAR ARRAY OF FIXED-COUPLING QUANTUM SYSTEMS FOR QUANTUM INFORMATION PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13226557
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
REDUCING PHASE LOCKED LOOP PHASE LOCK TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13226650
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
TRANSIMPEDANCE AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13226681
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
MULTIPATH SOLDERED THERMAL INTERFACE BETWEEN A CHIP AND ITS HEAT SINK
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13226838
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13227028
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
Title:
|
COMPARATOR OFFSET CANCELLATION IN A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13228491
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
EMBEDDING A NANOTUBE INSIDE A NANOPORE FOR DNA TRANSLOCATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13228767
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13228857
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13228983
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
Heat Treatment Process and Photovoltaic Device Based on Said Process
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13229250
|
Filing Dt:
|
09/09/2011
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
MECHANICALLY ROBUST METAL/LOW-k INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13230083
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
TRANSISTOR WITH ASYMMETRIC SILICON GERMANIUM SOURCE REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
13230360
|
Filing Dt:
|
09/12/2011
|
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13230371
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13230442
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
Title:
|
Reconfigurable Multi-level Sensing Scheme for Semiconductor Memories
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13230457
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
Strain-Compensating Fill Patterns for Controlling Semiconductor Chip Package Interactions
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13230798
|
Filing Dt:
|
09/12/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
TUNABLE RADIATION SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13231194
|
Filing Dt:
|
09/13/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13231516
|
Filing Dt:
|
09/13/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
TEST STRUCTURE AND CALIBRATION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13231750
|
Filing Dt:
|
09/13/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13232075
|
Filing Dt:
|
09/14/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
Methods of Forming Semiconductor Devices Having Capacitor and Via Contacts
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13232571
|
Filing Dt:
|
09/14/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13232681
|
Filing Dt:
|
09/14/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
BEOL ANTI-FUSE STRUCTURES FOR GATE LAST SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13232711
|
Filing Dt:
|
09/14/2011
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
Superior Integrity of High-K Metal Gate Stacks by Preserving a Resist Material Above End Caps of Gate Electrode Structures
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13233064
|
Filing Dt:
|
09/15/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13233590
|
Filing Dt:
|
09/15/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
Repair of Damaged Surface Areas of Sensitive Low-K Dielectrics of Microstructure Devices After Plasma Processing by In Situ Treatment
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13233752
|
Filing Dt:
|
09/15/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
METAL INSULATOR METAL (MIM) CAPACITOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13233762
|
Filing Dt:
|
09/15/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
SOI Semiconductor Device Comprising a Substrate Diode and a Film Diode Formed by Using a Common Well Implantation Mask
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13233948
|
Filing Dt:
|
09/15/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT DECOUPLING CAPACITOR ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13234073
|
Filing Dt:
|
09/15/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
ANTIFERROMAGNETIC STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13234276
|
Filing Dt:
|
09/16/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
CHARGED ENTITIES AS LOCOMOTIVE TO CONTROL MOTION OF POLYMERS THROUGH A NANOCHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13234529
|
Filing Dt:
|
09/16/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13235194
|
Filing Dt:
|
09/16/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
METHODS FOR FORMING SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13235211
|
Filing Dt:
|
09/16/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
STRAINED SEMICONDUCTOR DEVICES HAVING ASYMMETRICAL HETEROJUNCTION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
13235653
|
Filing Dt:
|
09/19/2011
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13236109
|
Filing Dt:
|
09/19/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
INCREASING THROUGHPUT OF MULTIPLEXED ELECTRICAL BUS IN PIPE-LINED ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13236119
|
Filing Dt:
|
09/19/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13237011
|
Filing Dt:
|
09/20/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13237265
|
Filing Dt:
|
09/20/2011
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
REDUCING CONTAMINATION IN A PROCESS FLOW OF FORMING A CHANNEL SEMICONDUCTOR ALLOY IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13237319
|
Filing Dt:
|
09/20/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
Field Effect Transistor Device with Raised Active Regions
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13237374
|
Filing Dt:
|
09/20/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
MULTI-SPINDLE CHEMICAL MECHANICAL PLANARIZATION TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13237386
|
Filing Dt:
|
09/20/2011
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
METHOD OF CONCETRATING SOLAR ENERGY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13237688
|
Filing Dt:
|
09/20/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13237732
|
Filing Dt:
|
09/20/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
MOSFET INTEGRATED CIRCUIT WITH UNIFORMLY THIN SILICIDE LAYER AND METHODS FOR ITS MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13238070
|
Filing Dt:
|
09/21/2011
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A HARD MASK LAYER STACK AND APPLYING A PLASMA-BASED MASK PATTERNING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13238180
|
Filing Dt:
|
09/21/2011
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
EMBEDDED SIGMA-SHAPED SEMICONDUCTOR ALLOYS FORMED IN TRANSISTORS BY APPLYING A UNIFORM OXIDE LAYER PRIOR TO CAVITY ETCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13238414
|
Filing Dt:
|
09/21/2011
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) HAVING A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE (VB), A METHOD OF FORMING AN LEDMOSFET, AND A SILICON-CONTROLLED RECTIFIER (SCR) INCORPORATING A COMPLEMENTARY PAIR OF LEDMOSFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13239533
|
Filing Dt:
|
09/22/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13239672
|
Filing Dt:
|
09/22/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
DRIVE CURRENT INCREASE IN FIELD EFFECT TRANSISTORS BY ASYMMETRIC CONCENTRATION PROFILE OF ALLOY SPECIES OF A CHANNEL SEMICONDUCTOR ALLOY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13239865
|
Filing Dt:
|
09/22/2011
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
CHARGING PROTECTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13239872
|
Filing Dt:
|
09/22/2011
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
SEMICONDUCTOR CHIP WITH BACKSIDE CONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13239943
|
Filing Dt:
|
09/22/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
SUPERIOR INTEGRITY OF HIGH-K METAL GATE STACKS BY FORMING STI REGIONS AFTER GATE METALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
13240272
|
Filing Dt:
|
09/22/2011
|
Title:
|
COMMAND PACKET PACKING TO MITIGATE CRC OVERHEAD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13241383
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13241458
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
MANUFACTURING PROCESS PRIORITIZATION BASED ON APPLYING RULES TO TASK-BASED DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13241496
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
FUNCTIONAL SIMULATION REDUNDANCY REDUCTION BY STATE COMPARISON AND PRUNING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13241810
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
MASK FOR FORMING INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13241915
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
Semiconductor Device Comprising Replacement Gate Electrode Structures and Self-Aligned Contact Elements Formed by a Late Contact Fill
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13241995
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
LITHOGRAPHIC CD CORRECTION BY SECOND EXPOSURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13242861
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
JUNCTIONLESS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13243502
|
Filing Dt:
|
09/23/2011
|
Title:
|
METHOD FOR FABRICATING THROUGH SUBSTRATE VIAS IN SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13243605
|
Filing Dt:
|
09/23/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUIT SYSTEMS INCLUDING HIGH RELIABILITY DIE UNDER-FILL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13244426
|
Filing Dt:
|
09/24/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
RETICLE DEFECT CORRECTION BY SECOND EXPOSURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
13244998
|
Filing Dt:
|
09/26/2011
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13246037
|
Filing Dt:
|
09/27/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
13246175
|
Filing Dt:
|
09/27/2011
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13246904
|
Filing Dt:
|
09/28/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13247763
|
Filing Dt:
|
09/28/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE FABRICATION METHODS WITH ENHANCED CONTROL IN RECESSING PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13248792
|
Filing Dt:
|
09/29/2011
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13251660
|
Filing Dt:
|
10/03/2011
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
STRUCTURE AND METHOD TO FORM PASSIVE DEVICES IN ETSOI PROCESS FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13251757
|
Filing Dt:
|
10/03/2011
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
13252152
|
Filing Dt:
|
10/03/2011
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
Title:
|
POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13252366
|
Filing Dt:
|
10/04/2011
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
FUSE FOR THREE DIMENSIONAL SOLID-STATE BATTERY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13252424
|
Filing Dt:
|
10/04/2011
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
Title:
|
NOVEL REWORKABLE UNDERFILLS FOR CERAMIC MCM C4 PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13252868
|
Filing Dt:
|
10/04/2011
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTION HISTOGRAMS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
|
Application #:
|
13253210
|
Filing Dt:
|
10/05/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
Enhancing Transistor Performance by Reducing Exposure to Oxygen Plasma in a Dual Stress Liner Approach
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13253260
|
Filing Dt:
|
10/05/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
Low Phase Variation CMOS Digital Attenuator
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13253375
|
Filing Dt:
|
10/05/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13267198
|
Filing Dt:
|
10/06/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
SIDEWALL IMAGE TRANSFER PROCESS WITH MULTIPLE CRITICAL DIMENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13267739
|
Filing Dt:
|
10/06/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
MOSFET INTEGRATED CIRCUIT HAVING DOPED CONDUCTIVE INTERCONNECTS AND METHODS FOR ITS MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13269552
|
Filing Dt:
|
10/07/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13269830
|
Filing Dt:
|
10/10/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
DETERMINATION OF SERIES RESISTANCE OF AN ARRAY OF CAPACITIVE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13269942
|
Filing Dt:
|
10/10/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
ASYMMETRIC MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13269955
|
Filing Dt:
|
10/10/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
EMBEDED DRAM CELL STRUCTURES WITH HIGH CONDUCTANCE ELECTRODES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2015
|
Application #:
|
13270047
|
Filing Dt:
|
10/10/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13270649
|
Filing Dt:
|
10/11/2011
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
USER-COORDINATED RESOURCE RECOVERY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13271796
|
Filing Dt:
|
10/12/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
MULTI-BIT SPIN-MOMENTUM-TRANSFER MAGNETORESISTENCE RANDOM ACCESS MEMORY WITH SINGLE MAGNETIC-TUNNEL-JUNCTION STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13272340
|
Filing Dt:
|
10/13/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
REDUCING PERFORMANCE VARIATION OF NARROW CHANNEL DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2016
|
Application #:
|
13272395
|
Filing Dt:
|
10/13/2011
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
METHOD, STRUCTURES AND METHOD OF DESIGNING REDUCED DELAMINATION INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13272409
|
Filing Dt:
|
10/13/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
FINFET PARASITIC CAPACITANCE REDUCTION USING AIR GAP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13272485
|
Filing Dt:
|
10/13/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
SEMICONDUCTOR TRENCH INDUCTORS AND TRANSFORMERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13274389
|
Filing Dt:
|
10/17/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
ARRAY AND MOAT ISOLATION STRUCTURES AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2016
|
Application #:
|
13274758
|
Filing Dt:
|
10/17/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
13275441
|
Filing Dt:
|
10/18/2011
|
Publication #:
|
|
Pub Dt:
|
02/09/2012
| | | | |
Title:
|
METHOD FOR HIGH DENSITY DATA STORAGE AND IMAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13275766
|
Filing Dt:
|
10/18/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
METHODS OF FORMING HIGHLY SCALED SEMICONDUCTOR DEVICES USING A DISPOSABLE SPACER TECHNIQUE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13275936
|
Filing Dt:
|
10/18/2011
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
PHOTOVOLTAIC DEVICE USING NANO-SPHERES FOR TEXTURED ELECTRODES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13276383
|
Filing Dt:
|
10/19/2011
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13276395
|
Filing Dt:
|
10/19/2011
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13277259
|
Filing Dt:
|
10/20/2011
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13277265
|
Filing Dt:
|
10/20/2011
|
Publication #:
|
|
Pub Dt:
|
02/09/2012
| | | | |
Title:
|
ON-CHIP MILLIMETER WAVE LANGE COUPLER
|
|