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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
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Patent #:	8399181	Issue Dt:	03/19/2013	Application #:	13346776	Filing Dt:	01/10/2012
Publication #:	US20120110524	Pub Dt:	05/03/2012
Title:	METHODS OF FABRICATING PHOTOMASKS FOR IMPROVING DAMASCENE WIRE UNIFORMITY WITHOUT REDUCING PERFORMANCE

Patent #:	8354309	Issue Dt:	01/15/2013	Application #:	13347014	Filing Dt:	01/10/2012
Publication #:	US20120108017	Pub Dt:	05/03/2012
Title:	THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION

Patent #:	8717136	Issue Dt:	05/06/2014	Application #:	13347571	Filing Dt:	01/10/2012
Publication #:	US20130176095	Pub Dt:	07/11/2013
Title:	INDUCTOR WITH LAMINATED YOKE

Patent #:	8872279	Issue Dt:	10/28/2014	Application #:	13347851	Filing Dt:	01/11/2012
Publication #:	US20120112819	Pub Dt:	05/10/2012
Title:	A TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER

Patent #:	8629008	Issue Dt:	01/14/2014	Application #:	13348018	Filing Dt:	01/11/2012
Publication #:	US20130175622	Pub Dt:	07/11/2013
Title:	ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES

Patent #:	8778772	Issue Dt:	07/15/2014	Application #:	13348101	Filing Dt:	01/11/2012
Publication #:	US20130178045	Pub Dt:	07/11/2013
Title:	METHOD OF FORMING TRANSISTOR WITH INCREASED GATE WIDTH

Patent #:	8946821	Issue Dt:	02/03/2015	Application #:	13348142	Filing Dt:	01/11/2012
Publication #:	US20130175627	Pub Dt:	07/11/2013
Title:	SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION

Patent #:	8557648	Issue Dt:	10/15/2013	Application #:	13348188	Filing Dt:	01/11/2012
Publication #:	US20130175623	Pub Dt:	07/11/2013
Title:	RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS

Patent #:	8859418	Issue Dt:	10/14/2014	Application #:	13348256	Filing Dt:	01/11/2012
Publication #:	US20130178057	Pub Dt:	07/11/2013
Title:	Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique

Patent #:	8557668	Issue Dt:	10/15/2013	Application #:	13348771	Filing Dt:	01/12/2012
Publication #:	US20130181260	Pub Dt:	07/18/2013
Title:	METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER

Patent #:	8656325	Issue Dt:	02/18/2014	Application #:	13348850	Filing Dt:	01/12/2012
Publication #:	US20130185684	Pub Dt:	07/18/2013
Title:	INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM

Patent #:	9620619	Issue Dt:	04/11/2017	Application #:	13348894	Filing Dt:	01/12/2012
Publication #:	US20130181261	Pub Dt:	07/18/2013
Title:	BORDERLESS CONTACT STRUCTURE

Patent #:	8441103	Issue Dt:	05/14/2013	Application #:	13349158	Filing Dt:	01/12/2012
Publication #:	US20120104551	Pub Dt:	05/03/2012
Title:	EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE

Patent #:	9355887	Issue Dt:	05/31/2016	Application #:	13349203	Filing Dt:	01/12/2012
Publication #:	US20120104511	Pub Dt:	05/03/2012
Title:	DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS

Patent #:	8418105	Issue Dt:	04/09/2013	Application #:	13349412	Filing Dt:	01/12/2012
Title:	METHODS FOR PATTERN MATCHING IN A DOUBLE PATTERNING TECHNOLOGY-COMPLIANT PHYSICAL DESIGN FLOW

Patent #:	8445964	Issue Dt:	05/21/2013	Application #:	13349883	Filing Dt:	01/13/2012
Publication #:	US20120112281	Pub Dt:	05/10/2012
Title:	FABRICATION OF SEMICONDUCTORS WITH HIGH-K/METAL GATE ELECTRODES

Patent #:	8941187	Issue Dt:	01/27/2015	Application #:	13349942	Filing Dt:	01/13/2012
Publication #:	US20130181299	Pub Dt:	07/18/2013
Title:	STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON STRAINED ISOLATION MATERIAL

Patent #:	8338225	Issue Dt:	12/25/2012	Application #:	13350817	Filing Dt:	01/16/2012
Publication #:	US20120115302	Pub Dt:	05/10/2012
Title:	METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL

Patent #:	8877606	Issue Dt:	11/04/2014	Application #:	13350889	Filing Dt:	01/16/2012
Publication #:	US20120112309	Pub Dt:	05/10/2012
Title:	LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION

Patent #:	8669170	Issue Dt:	03/11/2014	Application #:	13350891	Filing Dt:	01/16/2012
Publication #:	US20130183817	Pub Dt:	07/18/2013
Title:	METHODS OF REDUCING GATE LEAKAGE

Patent #:	9117877	Issue Dt:	08/25/2015	Application #:	13350908	Filing Dt:	01/16/2012
Publication #:	US20130181263	Pub Dt:	07/18/2013
Title:	METHODS OF FORMING A DIELECTRIC CAP LAYER ON A METAL GATE STRUCTURE

Patent #:	8779865	Issue Dt:	07/15/2014	Application #:	13350981	Filing Dt:	01/16/2012
Publication #:	US20120112842	Pub Dt:	05/10/2012
Title:	ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE

Patent #:	8492841	Issue Dt:	07/23/2013	Application #:	13351012	Filing Dt:	01/16/2012
Publication #:	US20120119296	Pub Dt:	05/17/2012
Title:	TRENCH-GENERATED TRANSISTOR STRUCTURES, DEVICE STRUCTURES, AND DESIGN STRUCTURES

Patent #:	8946853	Issue Dt:	02/03/2015	Application #:	13351041	Filing Dt:	01/16/2012
Publication #:	US20120112310	Pub Dt:	05/10/2012
Title:	DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE

Patent #:	8598633	Issue Dt:	12/03/2013	Application #:	13351101	Filing Dt:	01/16/2012
Publication #:	US20130181289	Pub Dt:	07/18/2013
Title:	SEMICONDUCTOR DEVICE HAVING CONTACT LAYER PROVIDING ELECTRICAL CONNECTIONS

Patent #:	8741718	Issue Dt:	06/03/2014	Application #:	13351294	Filing Dt:	01/17/2012
Publication #:	US20130181292	Pub Dt:	07/18/2013
Title:	LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES

Patent #:	8383507	Issue Dt:	02/26/2013	Application #:	13351370	Filing Dt:	01/17/2012
Publication #:	US20120111825	Pub Dt:	05/10/2012
Title:	METHOD FOR FABRICATING AIR GAP INTERCONNECT STRUCTURES

Patent #:	8455861	Issue Dt:	06/04/2013	Application #:	13351398	Filing Dt:	01/17/2012
Publication #:	US20120112166	Pub Dt:	05/10/2012
Title:	GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP

Patent #:	8450198	Issue Dt:	05/28/2013	Application #:	13351402	Filing Dt:	01/17/2012
Publication #:	US20120115295	Pub Dt:	05/10/2012
Title:	GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP

Patent #:	8880382	Issue Dt:	11/04/2014	Application #:	13352713	Filing Dt:	01/18/2012
Publication #:	US20130185045	Pub Dt:	07/18/2013
Title:	ANALYZING A PATTERNING PROCESS USING A MODEL OF YIELD

Patent #:	8748871	Issue Dt:	06/10/2014	Application #:	13352737	Filing Dt:	01/18/2012
Publication #:	US20120181510	Pub Dt:	07/19/2012
Title:	GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS

Patent #:	8796130	Issue Dt:	08/05/2014	Application #:	13352851	Filing Dt:	01/18/2012
Publication #:	US20130181293	Pub Dt:	07/18/2013
Title:	DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR

Patent #:	8390042	Issue Dt:	03/05/2013	Application #:	13353013	Filing Dt:	01/18/2012
Publication #:	US20120119308	Pub Dt:	05/17/2012
Title:	GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE

Patent #:	8855452	Issue Dt:	10/07/2014	Application #:	13353118	Filing Dt:	01/18/2012
Publication #:	US20130182998	Pub Dt:	07/18/2013
Title:	SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES

Patent #:	8901576	Issue Dt:	12/02/2014	Application #:	13353162	Filing Dt:	01/18/2012
Publication #:	US20130181233	Pub Dt:	07/18/2013
Title:	SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER

Patent #:	8471595	Issue Dt:	06/25/2013	Application #:	13353383	Filing Dt:	01/19/2012
Title:	SELECTABLE DYNAMIC/STATIC LATCH WITH EMBEDDED LOGIC

Patent #:	8772168	Issue Dt:	07/08/2014	Application #:	13353708	Filing Dt:	01/19/2012
Publication #:	US20130187203	Pub Dt:	07/25/2013
Title:	FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE

Patent #:	8843806	Issue Dt:	09/23/2014	Application #:	13353879	Filing Dt:	01/19/2012
Publication #:	US20130191703	Pub Dt:	07/25/2013
Title:	DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS

Patent #:	8782485	Issue Dt:	07/15/2014	Application #:	13353925	Filing Dt:	01/19/2012
Publication #:	US20130191698	Pub Dt:	07/25/2013
Title:	HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM

Patent #:	9147765	Issue Dt:	09/29/2015	Application #:	13354024	Filing Dt:	01/19/2012
Publication #:	US20130187228	Pub Dt:	07/25/2013
Title:	FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE AND METHODS OF MAKING SAME

Patent #:	9190323	Issue Dt:	11/17/2015	Application #:	13354070	Filing Dt:	01/19/2012
Publication #:	US20130187273	Pub Dt:	07/25/2013
Title:	SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME

Patent #:	9034701	Issue Dt:	05/19/2015	Application #:	13354363	Filing Dt:	01/20/2012
Publication #:	US20130187229	Pub Dt:	07/25/2013
Title:	SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME

Patent #:	8293638	Issue Dt:	10/23/2012	Application #:	13354371	Filing Dt:	01/20/2012
Publication #:	US20120115303	Pub Dt:	05/10/2012
Title:	METHOD OF FABRICATING DAMASCENE STRUCTURES

Patent #:	9058455	Issue Dt:	06/16/2015	Application #:	13354705	Filing Dt:	01/20/2012
Publication #:	US20130187246	Pub Dt:	07/25/2013
Title:	BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE

Patent #:	8490045	Issue Dt:	07/16/2013	Application #:	13354715	Filing Dt:	01/20/2012
Publication #:	US20120115256	Pub Dt:	05/10/2012
Title:	METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT

Patent #:	8927407	Issue Dt:	01/06/2015	Application #:	13354739	Filing Dt:	01/20/2012
Publication #:	US20130189833	Pub Dt:	07/25/2013
Title:	METHOD OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE

Patent #:	8504186	Issue Dt:	08/06/2013	Application #:	13354883	Filing Dt:	01/20/2012
Publication #:	US20120130523	Pub Dt:	05/24/2012
Title:	METHOD FOR AUTOMATIC GENERATION OF THROUGHPUT MODELS FOR SEMICONDUCTOR TOOLS

Patent #:	8589843	Issue Dt:	11/19/2013	Application #:	13355065	Filing Dt:	01/20/2012
Publication #:	US20120112341	Pub Dt:	05/10/2012
Title:	METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT

Patent #:	8504971	Issue Dt:	08/06/2013	Application #:	13355099	Filing Dt:	01/20/2012
Publication #:	US20120124538	Pub Dt:	05/17/2012
Title:	METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT

Patent #:	8293609	Issue Dt:	10/23/2012	Application #:	13355221	Filing Dt:	01/20/2012
Publication #:	US20120129311	Pub Dt:	05/24/2012
Title:	METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS

Patent #:	8922022	Issue Dt:	12/30/2014	Application #:	13356013	Filing Dt:	01/23/2012
Publication #:	US20120119366	Pub Dt:	05/17/2012
Title:	ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT

Patent #:	9059096	Issue Dt:	06/16/2015	Application #:	13356090	Filing Dt:	01/23/2012
Publication #:	US20130187171	Pub Dt:	07/25/2013
Title:	METHOD TO FORM SILICIDE CONTACT IN TRENCHES

Patent #:	8352900	Issue Dt:	01/08/2013	Application #:	13356681	Filing Dt:	01/24/2012
Title:	ANALYTIC EXPERIMENTAL ESTIMATOR FOR IMPACT OF VOLTAGE-OVERSHOOT OF VOLTAGE WAVEFORM ON DIELECTRIC FAILURE/BREAKDOWN

Patent #:	8343863	Issue Dt:	01/01/2013	Application #:	13357656	Filing Dt:	01/25/2012
Publication #:	US20120135587	Pub Dt:	05/31/2012
Title:	N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS

Patent #:	8476717	Issue Dt:	07/02/2013	Application #:	13357757	Filing Dt:	01/25/2012
Publication #:	US20120126339	Pub Dt:	05/24/2012
Title:	SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS

Patent #:	8765559	Issue Dt:	07/01/2014	Application #:	13358101	Filing Dt:	01/25/2012
Publication #:	US20120196417	Pub Dt:	08/02/2012
Title:	SOPHISTICATED GATE ELECTRODE STRUCTURES FORMED BY CAP LAYER REMOVAL WITH REDUCED LOSS OF EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL

Patent #:	8423936	Issue Dt:	04/16/2013	Application #:	13358105	Filing Dt:	01/25/2012
Publication #:	US20120124533	Pub Dt:	05/17/2012
Title:	SEMICONDUCTOR STRUCTURE AND METHOD OF DESIGNING SEMICONDUCTOR STRUCTURE TO AVOID HIGH VOLTAGE INITIATED LATCH-UP IN LOW VOLTAGE SECTORS

Patent #:	9099982	Issue Dt:	08/04/2015	Application #:	13358172	Filing Dt:	01/25/2012
Publication #:	US20130187729	Pub Dt:	07/25/2013
Title:	METHOD OF MANUFACTURING SWITCHING FILTERS AND DESIGN STRUCTURES

Patent #:	9059138	Issue Dt:	06/16/2015	Application #:	13358180	Filing Dt:	01/25/2012
Publication #:	US20130187198	Pub Dt:	07/25/2013
Title:	HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE

Patent #:	8411719	Issue Dt:	04/02/2013	Application #:	13358963	Filing Dt:	01/26/2012
Publication #:	US20120120976	Pub Dt:	05/17/2012
Title:	3D OPTOELECTRONIC PACKAGING

Patent #:	8609505	Issue Dt:	12/17/2013	Application #:	13359032	Filing Dt:	01/26/2012
Publication #:	US20120122293	Pub Dt:	05/17/2012
Title:	METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL

Patent #:	8483253	Issue Dt:	07/09/2013	Application #:	13359100	Filing Dt:	01/26/2012
Publication #:	US20120120978	Pub Dt:	05/17/2012
Title:	3D OPTOELECTRONIC PACKAGING

Patent #:	8716869	Issue Dt:	05/06/2014	Application #:	13359107	Filing Dt:	01/26/2012
Publication #:	US20130193554	Pub Dt:	08/01/2013
Title:	CELL ARRAY AND DENSITY FEATURES WITH DECOUPLING CAPACITORS

Patent #:	8941190	Issue Dt:	01/27/2015	Application #:	13359177	Filing Dt:	01/26/2012
Publication #:	US20120119284	Pub Dt:	05/17/2012
Title:	SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Patent #:	8669186	Issue Dt:	03/11/2014	Application #:	13359197	Filing Dt:	01/26/2012
Publication #:	US20130196508	Pub Dt:	08/01/2013
Title:	Methods of Forming SRAM Devices Using Sidewall Image Transfer Techniques

Patent #:	8587068	Issue Dt:	11/19/2013	Application #:	13359454	Filing Dt:	01/26/2012
Publication #:	US20130193515	Pub Dt:	08/01/2013
Title:	SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS

Patent #:	8487401	Issue Dt:	07/16/2013	Application #:	13359634	Filing Dt:	01/27/2012
Publication #:	US20120133022	Pub Dt:	05/31/2012
Title:	METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE

Patent #:	8852407	Issue Dt:	10/07/2014	Application #:	13359729	Filing Dt:	01/27/2012
Publication #:	US20120193236	Pub Dt:	08/02/2012
Title:	ELECTRON BEAM SCULPTING OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING

Patent #:	8940554	Issue Dt:	01/27/2015	Application #:	13359970	Filing Dt:	01/27/2012
Publication #:	US20120125538	Pub Dt:	05/24/2012
Title:	METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS

Patent #:	8299609	Issue Dt:	10/30/2012	Application #:	13360055	Filing Dt:	01/27/2012
Publication #:	US20120119333	Pub Dt:	05/17/2012
Title:	PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP

Patent #:	8640065	Issue Dt:	01/28/2014	Application #:	13360083	Filing Dt:	01/27/2012
Publication #:	US20130198705	Pub Dt:	08/01/2013
Title:	CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY

Patent #:	8367483	Issue Dt:	02/05/2013	Application #:	13360203	Filing Dt:	01/27/2012
Publication #:	US20120122280	Pub Dt:	05/17/2012
Title:	ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION

Patent #:	8367484	Issue Dt:	02/05/2013	Application #:	13360248	Filing Dt:	01/27/2012
Publication #:	US20120129340	Pub Dt:	05/24/2012
Title:	ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION

Patent #:	8368069	Issue Dt:	02/05/2013	Application #:	13360270	Filing Dt:	01/27/2012
Publication #:	US20120126366	Pub Dt:	05/24/2012
Title:	ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION

Patent #:	8368070	Issue Dt:	02/05/2013	Application #:	13360277	Filing Dt:	01/27/2012
Publication #:	US20120126367	Pub Dt:	05/24/2012
Title:	ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION

Patent #:	8614447	Issue Dt:	12/24/2013	Application #:	13361004	Filing Dt:	01/30/2012
Publication #:	US20130193441	Pub Dt:	08/01/2013
Title:	SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER

Patent #:	8390068	Issue Dt:	03/05/2013	Application #:	13361051	Filing Dt:	01/30/2012
Publication #:	US20120119257	Pub Dt:	05/17/2012
Title:	ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME

Patent #:	8445374	Issue Dt:	05/21/2013	Application #:	13361057	Filing Dt:	01/30/2012
Publication #:	US20120135564	Pub Dt:	05/31/2012
Title:	SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE

Patent #:	8516407	Issue Dt:	08/20/2013	Application #:	13361595	Filing Dt:	01/30/2012
Publication #:	US20130198696	Pub Dt:	08/01/2013
Title:	METHODS FOR QUANTITATIVELY EVALUATING THE QUALITY OF DOUBLE PATTERNING TECHNOLOGY-COMPLIANT LAYOUTS

Patent #:	8350343	Issue Dt:	01/08/2013	Application #:	13362019	Filing Dt:	01/31/2012
Publication #:	US20120133000	Pub Dt:	05/31/2012
Title:	FIELD EFFECT TRANSISTOR WITH CHANNEL REGION EDGE AND CENTER PORTIONS HAVING DIFFERENT BAND STRUCTURES FOR SUPPRESSED CORNER LEAKAGE

Patent #:	8361887	Issue Dt:	01/29/2013	Application #:	13362043	Filing Dt:	01/31/2012
Publication #:	US20120129319	Pub Dt:	05/24/2012
Title:	METHOD OF PROGRAMMING ELECTRICAL ANTIFUSE

Patent #:	8841764	Issue Dt:	09/23/2014	Application #:	13362366	Filing Dt:	01/31/2012
Publication #:	US20130196855	Pub Dt:	08/01/2013
Title:	SUPERCONDUCTING QUANTUM CIRCUIT HAVING A RESONANT CAVITY THERMALIZED WITH METAL COMPONENTS

Patent #:	8481410	Issue Dt:	07/09/2013	Application #:	13362398	Filing Dt:	01/31/2012
Publication #:	US20130196485	Pub Dt:	08/01/2013
Title:	METHODS OF EPITAXIAL FINFET

Patent #:	9119464	Issue Dt:	09/01/2015	Application #:	13362635	Filing Dt:	01/31/2012
Publication #:	US20130192634	Pub Dt:	08/01/2013
Title:	BRUSH CLEANING SYSTEM

Patent #:	9291735	Issue Dt:	03/22/2016	Application #:	13362754	Filing Dt:	01/31/2012
Publication #:	US20130197877	Pub Dt:	08/01/2013
Title:	PROBABLISTIC SUBSURFACE MODELING FOR IMPROVED DRILL CONTROL AND REAL-TIME CORRECTION

Patent #:	8772878	Issue Dt:	07/08/2014	Application #:	13362763	Filing Dt:	01/31/2012
Publication #:	US20120129308	Pub Dt:	05/24/2012
Title:	PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL

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Title:	LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID

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Title:	FILM FOR PACKAGING PRODUCT, ESPECIALLY AN ENVELOPE

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Title:	THERMALLY INSULATED PHASE MATERIAL CELLS

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Title:	RECESSED GATE CHANNEL WITH LOW VT CORNER

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Title:	TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES

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Title:	THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS

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Title:	LOCAL BOTTOM GATES FOR GRAPHENE AND CARBON NANOTUBE DEVICES

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Title:	IMPLEMENTING MULTIPLE DIFFERENT TYPES OF DIES FOR MEMORY STACKING

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100

Patent #:	8476988	Issue Dt:	07/02/2013	Application #:	13364569	Filing Dt:	02/02/2012
Publication #:	US20120131776	Pub Dt:	05/31/2012
Title:	DESIGN STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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