|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13570972
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
STRUCTURE WITH SUB-LITHOGRAPHIC RANDOM CONDUCTORS AS A PHYSICAL UNCLONABLE FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13570989
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13571094
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
GATED DIODE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13571190
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
SRAM INTEGRATED CIRCUITS WITH BURIED SADDLE-SHAPED FINFET AND METHODS FOR THEIR FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13571429
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
SCHOTTKY FET FABRICATED WITH GATE LAST PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13571470
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
METHODS OF IN-SITU VAPOR PHASE DEPOSITION OF SELF-ASSEMBLED MONOLAYERS AS COPPER ADHESION PROMOTERS AND DIFFUSION BARRIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13571521
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
FABRICATION OF DEVICES HAVING DIFFERENT INTERFACIAL OXIDE THICKNESS VIA LATERAL OXIDATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13571607
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
DOUBLE CONTACTS FOR CARBON NANOTUBES THIN FILM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13571657
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
|
Title:
|
TFET WITH NANOWIRE SOURCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13571791
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
METHODS OF FORMING METAL OXIDE NANOSTRUCTURES, AND NANOSTRUCTURES THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13571920
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13571986
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13572004
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2015
| | | | |
|
Title:
|
COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13572037
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
METHOD FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13572039
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
METHOD FOR FABRICATING MOSFET ON SILICON-ON-INSULATOR WITH INTERNAL BODY CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13572114
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13572289
|
Filing Dt:
|
08/10/2012
|
|
Title:
|
RELIABLE PHYSICAL UNCLONABLE FUNCTION FOR DEVICE AUTHENTICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13572343
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUITS WITH IMPROVED SPACERS AND METHODS FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13572742
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
BEOL COMPATIBLE FET STRUCTRURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13572954
|
Filing Dt:
|
08/13/2012
|
|
Title:
|
SYSTEM YIELD OPTIMIZATION USING THE RESULTS OF INTEGRATED CIRCUIT CHIP PERFORMANCE PATH TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
13572988
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
COMPUTING MULTI-MAGNET BASED DEVICES AND METHODS FOR SOLUTION OF OPTIMIZATION PROBLEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13573000
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
DETERMINING CELL-STATE IN PHASE-CHANGE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13584055
|
Filing Dt:
|
08/13/2012
|
|
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND LOW-K SPACERS AND THE RESULTING DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13584120
|
Filing Dt:
|
10/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
|
Title:
|
MULTI-BIT RESISTANCE MEASUREMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13584156
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
STRUCTURE AND METHOD TO FORM INPUT/OUTPUT DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13584176
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
HIGH DENSITY BULK FIN CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13584199
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
CONTACTS-FIRST SELF-ALIGNED CARBON NANOTUBE TRANSISTOR WITH GATE-ALL-AROUND
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
13584326
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
|
Title:
|
TWO MASK PROCESS FOR ELECTROPLATING METAL EMPLOYING A NEGATIVE ELECTROPHORETIC PHOTORESIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13584423
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
|
Title:
|
DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13584981
|
Filing Dt:
|
08/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DRY CHEMICAL REMOVAL PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13585152
|
Filing Dt:
|
08/14/2012
|
|
Title:
|
IDENTIFICATION OF ILLEGAL DEVICES USING CONTACT MAPPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13585395
|
Filing Dt:
|
08/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13585465
|
Filing Dt:
|
08/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
DOUBLE CONTACTS FOR CARBON NANOTUBES THIN FILM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13585974
|
Filing Dt:
|
08/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
METHODS OF THINNING AND/OR DICING SEMICONDUCTING SUBSTRATES HAVING INTEGRATED CIRCUIT PRODUCTS FORMED THEREON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13586136
|
Filing Dt:
|
08/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
MEMORY CELL ASSEMBLY INCLUDING AN AVOID DISTURB CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13586182
|
Filing Dt:
|
08/15/2012
|
|
Title:
|
MULTI-ELEMENT PACKAGING OF CONCENTRATOR PHOTOVOLTAIC CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13586187
|
Filing Dt:
|
08/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
|
Title:
|
PHOTONIC MODULATOR WITH A SEMICONDUCTOR CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13587088
|
Filing Dt:
|
08/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
TONE INVERSION OF SELF-ASSEMBLED SELF-ALIGNED STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13587146
|
Filing Dt:
|
08/16/2012
|
|
Title:
|
WRITING SCHEME FOR PHASE CHANGE MATERIAL-CONTENT ADDRESSABLE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13587288
|
Filing Dt:
|
08/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A BODY-CONTACTED SOI FINFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13587508
|
Filing Dt:
|
08/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
CONTACTS-FIRST SELF-ALIGNED CARBON NANOTUBE TRANSISTOR WITH GATE-ALL-AROUND
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13587521
|
Filing Dt:
|
08/16/2012
|
|
Title:
|
USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13587694
|
Filing Dt:
|
08/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
|
Title:
|
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13587970
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
REDUCING EDGE DIE REFLECTIVITY IN EXTREME ULTRAVIOLET LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13587998
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13588059
|
Filing Dt:
|
08/17/2012
|
|
Title:
|
NOVEL REPLACEMENT GATE PROCESS FLOW FOR HIGHLY SCALED SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13588218
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
|
Title:
|
COMPACT THERMALLY CONTROLLED THIN FILM RESISTORS UTILIZING SUBSTRATE CONTACTS AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13588260
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
|
Title:
|
DATA CENTER COOLING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13588327
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
DEVICE COMPRISING A PLURALITY OF STATIC RANDOM ACCESS MEMORY CELLS AND METHOD OF OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13588382
|
Filing Dt:
|
08/17/2012
|
|
Title:
|
HIGH DENSITY SELECTIVE DEPOSITION OF CARBON NANOTUBES ONTO A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13588460
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
COMPRESSIVE STRESS TRANSFER IN AN INTERLAYER DIELECTRIC OF A SEMICONDUCTOR DEVICE BY PROVIDING A BI-LAYER OF SUPERIOR ADHESION AND INTERNAL STRESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
13588517
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
METHODS OF FORMING A REPLACEMENT GATE STRUCTURE HAVING A GATE ELECTRODE COMPRISED OF A DEPOSITED INTERMETALLIC COMPOUND MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13588585
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
METALLURGICAL CLAMSHELL METHODS FOR MICRO LAND GRID ARRAY FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13588724
|
Filing Dt:
|
08/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
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Application #:
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13589325
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Filing Dt:
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08/20/2012
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Publication #:
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Pub Dt:
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08/29/2013
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Title:
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SEMI-AUTOMATIC CONVERSION AND EXECUTION OF FUNCTIONAL MANUAL TESTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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11/04/2014
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Application #:
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13589606
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Filing Dt:
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08/20/2012
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Publication #:
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Pub Dt:
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12/06/2012
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Title:
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DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
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Application #:
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13589680
|
Filing Dt:
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08/20/2012
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Publication #:
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Pub Dt:
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02/21/2013
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Title:
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RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
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Application #:
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13589702
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Filing Dt:
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08/20/2012
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Publication #:
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Pub Dt:
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02/21/2013
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Title:
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RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
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Application #:
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13589707
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Filing Dt:
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08/20/2012
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Publication #:
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Pub Dt:
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02/20/2014
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Title:
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TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
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Application #:
|
13590212
|
Filing Dt:
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08/21/2012
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|
Title:
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FIELD EFFECT TRANSISTORS WITH LOW BODY RESISTANCE AND SELF-BALANCED BODY POTENTIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
13590251
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Filing Dt:
|
08/21/2012
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|
Publication #:
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|
Pub Dt:
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02/27/2014
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Title:
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SENSING BIOMOLECULES USING SCANNING PROBE WITH TWIN- NANOPORE TO DETECT A CHANGE IN THE MAGNITUDE OF THE CURRENT THROUGH THE SECOND NANOPORE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
08/27/2013
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Application #:
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13590300
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Filing Dt:
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08/21/2012
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Publication #:
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Pub Dt:
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12/06/2012
| | | | |
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Title:
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SPATIAL CORRELATION-BASED ESTIMATION OF YIELD OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
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Application #:
|
13590556
|
Filing Dt:
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08/21/2012
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|
Publication #:
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Pub Dt:
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02/27/2014
| | | | |
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Title:
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FORMING A HARDMASK CAPPING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13592434
|
Filing Dt:
|
08/23/2012
|
|
Publication #:
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|
Pub Dt:
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02/27/2014
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR APPLYING POST GRAPHIC DATA SYSTEM STREAM ENHANCEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
13593590
|
Filing Dt:
|
08/24/2012
|
|
Publication #:
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Pub Dt:
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02/06/2014
| | | | |
|
Title:
|
RATE ADAPTIVE TRANSMISSION OF WIRELESS BROADCAST PACKETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
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Application #:
|
13593614
|
Filing Dt:
|
08/24/2012
|
|
Publication #:
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Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
METHODS OF FORMING A LAYER OF SILICON ON A LAYER OF SILICON/GERMANIUM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13594037
|
Filing Dt:
|
08/24/2012
|
|
Publication #:
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|
Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
GATE TUNABLE TUNNEL DIODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13594198
|
Filing Dt:
|
08/24/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
OPTIMIZATION OF A MANUFACTURING PROCESS OF AN INTEGRATED CIRCUIT LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13594292
|
Filing Dt:
|
08/24/2012
|
|
Publication #:
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|
Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13595025
|
Filing Dt:
|
08/27/2012
|
|
Publication #:
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Pub Dt:
|
03/07/2013
| | | | |
|
Title:
|
IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13595208
|
Filing Dt:
|
08/27/2012
|
|
Publication #:
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Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SEMICONDUCTOR DEVICES INCLUDING A RETROGRADE WELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13595432
|
Filing Dt:
|
08/27/2012
|
|
Title:
|
HIGH DENSITY SELECTIVE DEPOSITION OF CARBON NANOTUBES ONTO A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13595574
|
Filing Dt:
|
08/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
METHOD OF FORMING HARDMASK LAYER WITH ALTERNATING NANOLAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13595650
|
Filing Dt:
|
08/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
LITHOGRAPHIC CD CORRECTION BY SECOND EXPOSURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13596126
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
METHOD FOR POST DECOMPOSITION DENSITY BALANCING IN INTEGRATED CIRCUIT LAYOUTS, RELATED SYSTEM AND PROGRAM PRODUCT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13596140
|
Filing Dt:
|
08/28/2012
|
|
Title:
|
DENSITY BALANCING IN MULTIPLE PATTERNING LITHOGRAPHY USING INTEGRATED CIRCUIT LAYOUT FILL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13596198
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
BEOL INTEGRATION SCHEME FOR COPPER CMP TO PREVENT DENDRITE FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2015
|
Application #:
|
13596234
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2014
| | | | |
|
Title:
|
EPITAXIALLY THICKENED DOPED OR UNDOPED CORE NANOWIRE FET STRUCTURE AND METHOD FOR INCREASING EFFECTIVE DEVICE WIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13596251
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
SCANNING PROBE WITH TWIN-NANOPORE OR A-SINGLE-NANOPORE FOR SENSING BIOMOLECULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13596351
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
ENCODING A DATA WORD FOR WRITING THE ENCODED DATA WORD IN A MULTI-LEVEL SOLID STATE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13596410
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13596687
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13596808
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
METHOD AND DEVICE TO ACHIEVE SELF-STOP AND PRECISE GATE HEIGHT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
13597331
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
BORDERLESS CONTACTS FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13597412
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
PLATED LAMINATION STRUCTURES FOR INTEGRATED MAGNETIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13597610
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
GATE TUNABLE TUNNEL DIODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13597752
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13597799
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
SEMICONDUCTOR FIN ON LOCAL OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13597802
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13598001
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
DRAM REFRESH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13598080
|
Filing Dt:
|
08/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
FINFET WITH SELF-ALIGNED PUNCHTHROUGH STOPPER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13598787
|
Filing Dt:
|
08/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
SRAM LOCAL EVALUATION LOGIC FOR COLUMN SELECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13599256
|
Filing Dt:
|
08/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13600314
|
Filing Dt:
|
08/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
FINFET WITH REDUCED PARASITIC CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13600324
|
Filing Dt:
|
08/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
SUSPENDED NANOWIRE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2015
|
Application #:
|
13600598
|
Filing Dt:
|
08/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13600625
|
Filing Dt:
|
08/31/2012
|
|
Title:
|
SILICON GERMANIUM CHANNEL WITH SILICON BUFFER REGIONS FOR FIN FIELD EFFECT TRANSISTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13601072
|
Filing Dt:
|
08/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
|
Title:
|
METHOD OF FORMING A MATERIAL LAYER IN A SEMICONDUCTOR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13601240
|
Filing Dt:
|
08/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
|
Title:
|
CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13602117
|
Filing Dt:
|
09/01/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE
|
|
