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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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09256786
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Filing Dt:
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02/24/1999
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Title:
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ARRANGEMENT IN A NETWORK REPEATER FOR MONITORING LINK INTEGRITY AND AUTOMATICALLY DOWN SHIFTING LINK SPEED
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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09584301
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Filing Dt:
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05/31/2000
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Title:
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METHOD AND APPARATUS FOR POWERING DOWN THE CPU/MEMORY CONTROLLER COMPLEX WHILE PRESERVING THE SELF REFRESH STATE OF MEMORY IN THE SYSTEM
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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09621931
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Filing Dt:
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07/24/2000
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Title:
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A SYSTEM AND METHOD FOR SELECTING BETWEEN A VOLTAGE SPECIFIED BY A PROCESSOR AND AN ALTERNATE VOLTAGE TO BE SUPPLIED TO HE PROCESSOR
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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09760560
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Filing Dt:
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01/16/2001
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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METHOD AND INTERFACE FOR GLITCH-FREE CLOCK SWITCHING
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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09824389
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Filing Dt:
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04/02/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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METHOD AND SYSTEM OF AUTOMATIC DELAY DETECTION AND RECEIVER ADJUSTMENT FOR SYNCHRONOUS BUS INTERFACE
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Patent #:
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Issue Dt:
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12/08/2009
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09825905
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Filing Dt:
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04/04/2001
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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METHOD AND APPARATUS FOR SECURING PORTIONS OF MEMORY
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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09852372
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Filing Dt:
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05/10/2001
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Title:
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SECURE EXECUTION BOX
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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09853234
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Filing Dt:
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05/11/2001
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Title:
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INTERRUPTABLE AND RE-ENTERABLE SYSTEM MANAGEMENT MODE PROGRAMMING CODE
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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09853395
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Filing Dt:
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05/11/2001
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Title:
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ENHANCED SECURITY AND MANAGEABILITY USING SECURE STORAGE IN A PERSONAL COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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09853437
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Filing Dt:
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05/11/2001
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Title:
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PERSONAL COMPUTER SECURITY MECHANSIM
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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09853447
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Filing Dt:
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05/11/2001
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Title:
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INTEGRATED CIRCUIT FOR SECURITY AND MANAGEABILITY
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09892328
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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USING TYPE BITS TO TRACK STORAGE OF ECC AND PREDECODE BITS IN A LEVEL TWO CACHE
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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09901329
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Filing Dt:
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07/09/2001
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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SOFTWARE MODEM FOR COMMUNICATING DATA USING ENCRYPTED DATA AND UNENCRYPTED CONTROL CODES
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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09904751
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Filing Dt:
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07/13/2001
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Title:
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HARMONIC MIXER
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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09907083
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Filing Dt:
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07/17/2001
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Title:
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POWER STATE RESYNCHRONIZATION
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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09969304
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Filing Dt:
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10/02/2001
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Title:
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APPARATUS AND METHOD FOR PROVIDING AN EXTERNAL CLOCK FROM A CIRCUIT IN SLEEP MODE IN A PROCESSOR -BASED SYSTEM
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Patent #:
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Issue Dt:
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12/04/2007
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10044707
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Filing Dt:
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01/11/2002
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Title:
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PROCESSING TASKS WITH FAILURE RECOVERY
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Patent #:
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Issue Dt:
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04/18/2006
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10090507
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Filing Dt:
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03/04/2002
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Title:
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COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
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Patent #:
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Issue Dt:
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06/06/2006
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10091766
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Filing Dt:
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03/05/2002
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Title:
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COMPUTER SYSTEM INITIALIZATION VIA BOOT CODE STORED IN A NON-VOLATILE MEMORY HAVING AN INTERFACE COMPATIBLE WITH SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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02/17/2009
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10107784
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Filing Dt:
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03/27/2002
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Title:
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INPUT/OUTPUT PERMISSION BITMAPS FOR COMPARTMENTALIZED SECURITY
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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10108253
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Filing Dt:
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03/27/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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SYSTEM AND METHOD PROVIDING REGION-GRANULAR, HARDWARE-CONTROLLED MEMORY ENCRYPTION
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10180207
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Filing Dt:
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06/27/2002
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Title:
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PIGGYBACKING OF ECC CORRECTIONS BEHIND LOADS
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10184434
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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ATA AND SATA COMPLIANT CONTROLLER
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10249291
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Filing Dt:
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03/28/2003
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Publication #:
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Pub Dt:
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09/30/2004
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Title:
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HIGH SPEED CLOCK DIVIDER WITH SYNCHRONOUS PHASE START-UP OVER PHYSICALLY DISTRIBUTED SPACE
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10256970
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Filing Dt:
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09/27/2002
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Title:
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COMPUTER SYSTEM WITH PROCESSOR CACHE THAT STORES REMOTE CACHE PRESENCE INFORMATION
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10259665
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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ON-CHIP HIGH SPEED DATA INTERFACE
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Patent #:
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02/27/2007
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10259708
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09/27/2002
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10/30/2003
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Title:
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DIGITAL AUTOMATIC GAIN CONTROL FOR TRANSCEIVER DEVICES
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07/26/2005
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10259710
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09/27/2002
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10/09/2003
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Title:
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ATA/SATA COMBINED CONTROLLER
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02/21/2006
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10284642
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10/31/2002
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10/30/2003
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Title:
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DIRECT CONVERSION RECEIVER HAVING A GAIN-SETTING DEPENDENT FILTER PARAMETER
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Patent #:
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03/21/2006
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10285935
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11/01/2002
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02/05/2004
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Title:
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RETRY MECHANISM FOR BLOCKING INTERFACES
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Patent #:
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01/22/2013
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10323272
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12/18/2002
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06/24/2004
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Title:
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Parallel fault detection
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12/04/2007
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10323987
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12/18/2002
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SYSTEM AND METHOD FOR STATE-BASED PROFILING OF MULTIPROCESSOR SYSTEMS
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02/15/2005
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10324761
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12/20/2002
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01/01/2004
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Title:
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PASSIVE IMPEDANCE NETWORK FOR ROTATING A PHASE SYSTEM
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05/29/2007
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10324782
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12/20/2002
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04/22/2004
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EXTENDED HOST CONTROLLER TEST MODE SUPPORT FOR USE WITH FULL-SPEED USB DEVICES
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03/28/2006
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10324806
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12/20/2002
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10/07/2004
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06/06/2006
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10361088
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02/07/2003
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05/06/2004
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EQUALIZING CIRCUIT WITH NOTCH COMPENSATION FOR A DIRECT COVERSION RECEIVER
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10/31/2006
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10419091
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04/18/2003
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04/25/2006
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10423993
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04/25/2003
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02/13/2007
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10425974
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04/29/2003
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05/30/2006
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04/30/2003
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09/04/2007
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10429159
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05/02/2003
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11/04/2004
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02/19/2008
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10434692
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05/09/2003
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04/05/2005
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10609360
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06/28/2003
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12/30/2004
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04/06/2010
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10614970
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07/08/2003
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03/29/2005
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11/07/2006
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10676437
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10/01/2003
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04/07/2005
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SYSTEM AND METHOD FOR HANDLING EXCEPTIONAL INSTRUCTIONS IN A TRACE CACHE BASED PROCESSOR
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01/16/2007
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10/01/2003
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05/09/2006
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10676636
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10/01/2003
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Title:
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Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
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08/02/2005
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10683823
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10/10/2003
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02/27/2007
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10699667
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11/04/2003
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Title:
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12/30/2008
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02/24/2004
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08/25/2005
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Autonomous Self-Monitoring and Corrective Operation of an Integrated Circuit
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10/10/2006
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10720466
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11/24/2003
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05/26/2005
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11/29/2011
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10726902
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12/03/2003
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06/09/2005
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05/13/2008
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10755692
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01/12/2004
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04/08/2008
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04/06/2004
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03/10/2009
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10839872
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05/06/2004
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11/17/2005
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NETWORK INTERFACE WITH SECURITY ASSOCIATION DATA PREFETCH FOR HIGH SPEED OFFLOADED SECURITY PROCESSING
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05/25/2010
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05/10/2004
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04/29/2008
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11/02/2010
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10887069
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07/08/2004
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07/07/2009
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10932999
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09/02/2004
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11/13/2007
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10956537
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10/01/2004
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08/14/2007
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10/01/2004
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04/06/2006
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DYNAMIC RECONFIGURATION OF CACHE MEMORY
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05/23/2006
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10970266
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10/21/2004
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12/01/2005
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DIGITALLY CONTROLLED FILTER TUNING FOR WLAN COMMUNICATION DEVICES
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12/26/2006
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11033754
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01/13/2005
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Title:
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DUAL-MODE OUTPUT DRIVER CONFIGURED FOR OUTPUTTING A SIGNAL ACCORDING TO EITHER A SELECTED HIGH VOLTAGE/LOW SPEED MODE OR A LOW VOLTAGE/HIGH SPEED MODE
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08/14/2007
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11033755
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01/13/2005
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11/14/2006
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11033757
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01/13/2005
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VOLTAGE MODE TRANSCEIVER HAVING PROGRAMMABLE VOLTAGE SWING AND EXTERNAL REFERENCE-BASED CALIBRATION
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09/07/2010
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11042218
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01/25/2005
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07/27/2006
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SCRATCH PAD FOR STORING INTERMEDIATE LOOP FILTER DATA
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Patent #:
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Issue Dt:
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08/26/2008
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Application #:
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11066752
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Filing Dt:
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02/25/2005
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Title:
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EXECUTING SYSTEM MANAGEMENT MODE CODE AS VIRTUAL MACHINE GUEST
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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11066873
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Filing Dt:
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02/25/2005
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Title:
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VIRTUALIZATION OF REAL MODE EXECUTION
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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11076323
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Filing Dt:
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03/09/2005
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Title:
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SYSTEM FOR ENABLING AND DISABLING CACHE AND A METHOD THEREOF
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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11098153
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Filing Dt:
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04/04/2005
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Publication #:
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Pub Dt:
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10/05/2006
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Title:
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SYSTEM FOR SPECULATIVE BRANCH PREDICTION OPTIMIZATION AND METHOD THEREOF
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Patent #:
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Issue Dt:
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11/05/2013
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Application #:
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11098273
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Filing Dt:
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04/04/2005
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Title:
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System and method for aligning change-of-flow instructions in an instruction buffer
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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11140803
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Filing Dt:
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05/31/2005
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Title:
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SERIAL INTERFACE HAVING A READ TEMPERATURE COMMAND
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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11146863
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06/07/2005
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Publication #:
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12/07/2006
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Title:
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MICROPROCESSOR INCLUDING A CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
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Patent #:
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Issue Dt:
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02/02/2010
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Application #:
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11151318
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Filing Dt:
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06/14/2005
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Title:
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CONTROL OF PCI MEMORY READ BEHAVIOR USING MEMORY READ ALIAS AND MEMORY COMMAND REISSUE BITS
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Patent #:
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12/09/2008
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11192153
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07/28/2005
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Title:
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USING A SHUFFLE UNIT TO IMPLEMENT SHIFT OPERATIONS IN A PROCESSOR
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Patent #:
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12/22/2009
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11192259
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07/28/2005
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Publication #:
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02/01/2007
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Title:
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VERIFIED COMPUTING ENVIRONMENT FOR PERSONAL INTERNET COMMUNICATOR
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Patent #:
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Issue Dt:
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06/02/2009
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11278840
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04/06/2006
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Publication #:
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Pub Dt:
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10/11/2007
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Title:
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TIME WEIGHTED MOVING AVERAGE FILTER
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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11279981
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Filing Dt:
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04/17/2006
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Title:
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COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
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Patent #:
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09/18/2007
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11286454
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11/23/2005
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Title:
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DELAY-LOCKED LOOP HAVING A PLURALITY OF LOCK MODES
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Patent #:
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Issue Dt:
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09/16/2008
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11297856
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12/09/2005
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Publication #:
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Pub Dt:
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06/14/2007
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Title:
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MEMORY ACCESS REQUEST ARBITRATION
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Patent #:
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02/17/2009
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11316499
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12/21/2005
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Publication #:
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Pub Dt:
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02/01/2007
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Title:
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SECURE PATCH INSTALLATION FOR WWAN SYSTEMS
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Patent #:
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Issue Dt:
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04/30/2013
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Application #:
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11317593
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Filing Dt:
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12/23/2005
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Title:
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STRIDED BLOCK TRANSFER INSTRUCTION
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Patent #:
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Issue Dt:
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02/05/2013
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Application #:
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11321706
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Filing Dt:
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12/29/2005
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Title:
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DATA BLOCK TRANSFER TO CACHE
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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11325054
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01/03/2006
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Publication #:
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Pub Dt:
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07/05/2007
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Title:
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SYSTEM AND METHOD FOR OPERATING COMPONENTS OF AN INTEGRATED CIRCUIT AT INDEPENDENT FREQUENCIES AND/OR VOLTAGES
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Patent #:
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07/14/2009
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11348136
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02/06/2006
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Title:
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METHOD AND APPARATUS FOR CROSSTALK REDUCTION
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Patent #:
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06/01/2010
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11368785
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03/06/2006
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Publication #:
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09/06/2007
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Title:
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ASYMMETRIC CONTROL OF HIGH-SPEED BIDIRECTIONAL SIGNALING
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03/17/2009
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11368792
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03/06/2006
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Title:
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SYSTEM FOR PHASE TRACKING AND EQUALIZATION ACROSS A BYTE GROUP FOR ASYMMETRIC CONTROL OF HIGH-SPEED BIDIRECTIONAL SIGNALING
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Patent #:
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09/29/2009
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11379864
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04/24/2006
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Title:
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ERROR DETECTION IN A COMMUNICATION LINK
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Patent #:
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Issue Dt:
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07/27/2010
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11385329
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Filing Dt:
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03/21/2006
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Title:
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INCREMENTALLY ADJUSTABLE SKEW AND DUTY CYCLE CORRECTION FOR CLOCK SIGNALS WITHIN A CLOCK DISTRIBUTION NETWORK
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Patent #:
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Issue Dt:
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06/02/2009
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11503390
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08/11/2006
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Publication #:
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Pub Dt:
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02/15/2007
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Title:
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CONTROLLING AN I/O MMU
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11503700
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Filing Dt:
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08/14/2006
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Publication #:
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Pub Dt:
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02/14/2008
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Title:
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SYSTEM AND METHOD FOR LIMITING PROCESSOR PERFORMANCE
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Patent #:
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Issue Dt:
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08/24/2010
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11518843
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09/11/2006
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03/13/2008
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Title:
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SYSTEM FOR CONTROLLING HIGH-SPEED BIDIRECTIONAL COMMUNICATION
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07/22/2008
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11556882
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11/06/2006
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06/05/2008
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Title:
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CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING
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10/12/2010
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11557745
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11/08/2006
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05/03/2007
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Title:
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DIGITAL MEASURING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CHIP OPERATING PARAMETERS
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01/18/2011
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11559049
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11/13/2006
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05/15/2008
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Title:
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FILTERING AND REMAPPING INTERRUPTS
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04/06/2010
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11590286
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10/31/2006
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06/19/2008
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Title:
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MEMORY CONTROLLER INCLUDING A DUAL-MODE MEMORY INTERCONNECT
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12/28/2010
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11590290
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10/31/2006
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05/01/2008
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Title:
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MEMORY SYSTEM INCLUDING ASYMMETRIC HIGH-SPEED DIFFERENTIAL MEMORY INTERCONNECT
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11/23/2010
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11610219
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12/13/2006
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06/19/2008
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Title:
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PARTIAL CRC INSERTION IN DATA PACKETS FOR EARLY FORWARDING
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01/26/2010
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11623500
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01/16/2007
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07/19/2007
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Title:
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ADDRESS TRANSLATION FOR INPUT/OUTPUT (I/O) DEVICES AND INTERRUPT REMAPPING FOR I/O DEVICES IN AN I/O MEMORY MANAGEMENT UNIT (IOMMU)
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