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Reel/Frame:055173/0781   Pages: 15
Recorded: 01/29/2021
Attorney Dkt #:251367-9070
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 162
Page 1 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
05/22/2012
Application #:
09256786
Filing Dt:
02/24/1999
Title:
ARRANGEMENT IN A NETWORK REPEATER FOR MONITORING LINK INTEGRITY AND AUTOMATICALLY DOWN SHIFTING LINK SPEED
2
Patent #:
Issue Dt:
05/02/2006
Application #:
09584301
Filing Dt:
05/31/2000
Title:
METHOD AND APPARATUS FOR POWERING DOWN THE CPU/MEMORY CONTROLLER COMPLEX WHILE PRESERVING THE SELF REFRESH STATE OF MEMORY IN THE SYSTEM
3
Patent #:
Issue Dt:
06/08/2004
Application #:
09621931
Filing Dt:
07/24/2000
Title:
A SYSTEM AND METHOD FOR SELECTING BETWEEN A VOLTAGE SPECIFIED BY A PROCESSOR AND AN ALTERNATE VOLTAGE TO BE SUPPLIED TO HE PROCESSOR
4
Patent #:
Issue Dt:
05/02/2006
Application #:
09760560
Filing Dt:
01/16/2001
Publication #:
Pub Dt:
09/26/2002
Title:
METHOD AND INTERFACE FOR GLITCH-FREE CLOCK SWITCHING
5
Patent #:
Issue Dt:
05/10/2005
Application #:
09824389
Filing Dt:
04/02/2001
Publication #:
Pub Dt:
10/03/2002
Title:
METHOD AND SYSTEM OF AUTOMATIC DELAY DETECTION AND RECEIVER ADJUSTMENT FOR SYNCHRONOUS BUS INTERFACE
6
Patent #:
Issue Dt:
12/08/2009
Application #:
09825905
Filing Dt:
04/04/2001
Publication #:
Pub Dt:
10/10/2002
Title:
METHOD AND APPARATUS FOR SECURING PORTIONS OF MEMORY
7
Patent #:
Issue Dt:
06/20/2006
Application #:
09852372
Filing Dt:
05/10/2001
Title:
SECURE EXECUTION BOX
8
Patent #:
Issue Dt:
03/01/2005
Application #:
09853234
Filing Dt:
05/11/2001
Title:
INTERRUPTABLE AND RE-ENTERABLE SYSTEM MANAGEMENT MODE PROGRAMMING CODE
9
Patent #:
Issue Dt:
05/08/2007
Application #:
09853395
Filing Dt:
05/11/2001
Title:
ENHANCED SECURITY AND MANAGEABILITY USING SECURE STORAGE IN A PERSONAL COMPUTER SYSTEM
10
Patent #:
Issue Dt:
12/14/2004
Application #:
09853437
Filing Dt:
05/11/2001
Title:
PERSONAL COMPUTER SECURITY MECHANSIM
11
Patent #:
Issue Dt:
11/23/2004
Application #:
09853447
Filing Dt:
05/11/2001
Title:
INTEGRATED CIRCUIT FOR SECURITY AND MANAGEABILITY
12
Patent #:
Issue Dt:
10/12/2004
Application #:
09892328
Filing Dt:
06/26/2001
Publication #:
Pub Dt:
12/26/2002
Title:
USING TYPE BITS TO TRACK STORAGE OF ECC AND PREDECODE BITS IN A LEVEL TWO CACHE
13
Patent #:
Issue Dt:
03/27/2007
Application #:
09901329
Filing Dt:
07/09/2001
Publication #:
Pub Dt:
01/09/2003
Title:
SOFTWARE MODEM FOR COMMUNICATING DATA USING ENCRYPTED DATA AND UNENCRYPTED CONTROL CODES
14
Patent #:
Issue Dt:
08/01/2006
Application #:
09904751
Filing Dt:
07/13/2001
Title:
HARMONIC MIXER
15
Patent #:
Issue Dt:
09/21/2004
Application #:
09907083
Filing Dt:
07/17/2001
Title:
POWER STATE RESYNCHRONIZATION
16
Patent #:
Issue Dt:
12/14/2004
Application #:
09969304
Filing Dt:
10/02/2001
Title:
APPARATUS AND METHOD FOR PROVIDING AN EXTERNAL CLOCK FROM A CIRCUIT IN SLEEP MODE IN A PROCESSOR -BASED SYSTEM
17
Patent #:
Issue Dt:
12/04/2007
Application #:
10044707
Filing Dt:
01/11/2002
Title:
PROCESSING TASKS WITH FAILURE RECOVERY
18
Patent #:
Issue Dt:
04/18/2006
Application #:
10090507
Filing Dt:
03/04/2002
Title:
COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
19
Patent #:
Issue Dt:
06/06/2006
Application #:
10091766
Filing Dt:
03/05/2002
Title:
COMPUTER SYSTEM INITIALIZATION VIA BOOT CODE STORED IN A NON-VOLATILE MEMORY HAVING AN INTERFACE COMPATIBLE WITH SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
20
Patent #:
Issue Dt:
02/17/2009
Application #:
10107784
Filing Dt:
03/27/2002
Title:
INPUT/OUTPUT PERMISSION BITMAPS FOR COMPARTMENTALIZED SECURITY
21
Patent #:
Issue Dt:
03/13/2012
Application #:
10108253
Filing Dt:
03/27/2002
Publication #:
Pub Dt:
10/02/2003
Title:
SYSTEM AND METHOD PROVIDING REGION-GRANULAR, HARDWARE-CONTROLLED MEMORY ENCRYPTION
22
Patent #:
Issue Dt:
05/09/2006
Application #:
10180207
Filing Dt:
06/27/2002
Title:
PIGGYBACKING OF ECC CORRECTIONS BEHIND LOADS
23
Patent #:
Issue Dt:
05/29/2007
Application #:
10184434
Filing Dt:
06/27/2002
Publication #:
Pub Dt:
10/09/2003
Title:
ATA AND SATA COMPLIANT CONTROLLER
24
Patent #:
Issue Dt:
01/31/2006
Application #:
10249291
Filing Dt:
03/28/2003
Publication #:
Pub Dt:
09/30/2004
Title:
HIGH SPEED CLOCK DIVIDER WITH SYNCHRONOUS PHASE START-UP OVER PHYSICALLY DISTRIBUTED SPACE
25
Patent #:
Issue Dt:
08/22/2006
Application #:
10256970
Filing Dt:
09/27/2002
Title:
COMPUTER SYSTEM WITH PROCESSOR CACHE THAT STORES REMOTE CACHE PRESENCE INFORMATION
26
Patent #:
Issue Dt:
08/22/2006
Application #:
10259665
Filing Dt:
09/27/2002
Publication #:
Pub Dt:
10/02/2003
Title:
ON-CHIP HIGH SPEED DATA INTERFACE
27
Patent #:
Issue Dt:
02/27/2007
Application #:
10259708
Filing Dt:
09/27/2002
Publication #:
Pub Dt:
10/30/2003
Title:
DIGITAL AUTOMATIC GAIN CONTROL FOR TRANSCEIVER DEVICES
28
Patent #:
Issue Dt:
07/26/2005
Application #:
10259710
Filing Dt:
09/27/2002
Publication #:
Pub Dt:
10/09/2003
Title:
ATA/SATA COMBINED CONTROLLER
29
Patent #:
Issue Dt:
02/21/2006
Application #:
10284642
Filing Dt:
10/31/2002
Publication #:
Pub Dt:
10/30/2003
Title:
DIRECT CONVERSION RECEIVER HAVING A GAIN-SETTING DEPENDENT FILTER PARAMETER
30
Patent #:
Issue Dt:
03/21/2006
Application #:
10285935
Filing Dt:
11/01/2002
Publication #:
Pub Dt:
02/05/2004
Title:
RETRY MECHANISM FOR BLOCKING INTERFACES
31
Patent #:
Issue Dt:
01/22/2013
Application #:
10323272
Filing Dt:
12/18/2002
Publication #:
Pub Dt:
06/24/2004
Title:
Parallel fault detection
32
Patent #:
Issue Dt:
12/04/2007
Application #:
10323987
Filing Dt:
12/18/2002
Title:
SYSTEM AND METHOD FOR STATE-BASED PROFILING OF MULTIPROCESSOR SYSTEMS
33
Patent #:
Issue Dt:
02/15/2005
Application #:
10324761
Filing Dt:
12/20/2002
Publication #:
Pub Dt:
01/01/2004
Title:
PASSIVE IMPEDANCE NETWORK FOR ROTATING A PHASE SYSTEM
34
Patent #:
Issue Dt:
05/29/2007
Application #:
10324782
Filing Dt:
12/20/2002
Publication #:
Pub Dt:
04/22/2004
Title:
EXTENDED HOST CONTROLLER TEST MODE SUPPORT FOR USE WITH FULL-SPEED USB DEVICES
35
Patent #:
Issue Dt:
03/28/2006
Application #:
10324806
Filing Dt:
12/20/2002
Publication #:
Pub Dt:
10/07/2004
Title:
ELECTRONIC CIRCUIT WITH IMPROVED CURRENT STABILISATION
36
Patent #:
Issue Dt:
06/06/2006
Application #:
10361088
Filing Dt:
02/07/2003
Publication #:
Pub Dt:
05/06/2004
Title:
EQUALIZING CIRCUIT WITH NOTCH COMPENSATION FOR A DIRECT COVERSION RECEIVER
37
Patent #:
Issue Dt:
10/31/2006
Application #:
10419091
Filing Dt:
04/18/2003
Title:
METHOD FOR SELECTIVELY DISABLING INTERRUPTS ON A SECURE EXECUTION MODE-CAPABLE PROCESSOR
38
Patent #:
Issue Dt:
04/25/2006
Application #:
10423993
Filing Dt:
04/25/2003
Title:
SYSTEM AND METHOD FOR FACILITATING COMMUNICATION ACROSS AN ASYNCHRONOUS CLOCK BOUNDARY
39
Patent #:
Issue Dt:
02/13/2007
Application #:
10425974
Filing Dt:
04/29/2003
Title:
DDR ON-THE-FLY SYNCHRONIZATION
40
Patent #:
Issue Dt:
05/30/2006
Application #:
10426755
Filing Dt:
04/30/2003
Title:
SYSTEM AND METHOD FOR BLOCKING CACHE USE DURING DEBUGGING
41
Patent #:
Issue Dt:
09/04/2007
Application #:
10429159
Filing Dt:
05/02/2003
Publication #:
Pub Dt:
11/04/2004
Title:
SPECULATION POINTERS TO IDENTIFY DATA-SPECULATIVE OPERATIONS IN MICROPROCESSOR
42
Patent #:
Issue Dt:
02/19/2008
Application #:
10434692
Filing Dt:
05/09/2003
Title:
APPARATUS AND METHOD FOR BALANCED SPINLOCK SUPPORT IN NUMA SYSTEMS
43
Patent #:
Issue Dt:
04/05/2005
Application #:
10609360
Filing Dt:
06/28/2003
Publication #:
Pub Dt:
12/30/2004
Title:
NON-ABRUPT SWITCHING OF SLEEP TRANSISTOR OF POWER GATE STRUCTURE
44
Patent #:
Issue Dt:
04/06/2010
Application #:
10614970
Filing Dt:
07/08/2003
Title:
SYSTEM AND METHOD OF IMPLEMENTING MICROCODE OPERATIONS AS SUBROUTINES
45
Patent #:
Issue Dt:
03/29/2005
Application #:
10653802
Filing Dt:
09/03/2003
Title:
CIRCULAR BUFFER USING GROUPING FOR FIND FIRST FUNCTION
46
Patent #:
Issue Dt:
11/07/2006
Application #:
10676437
Filing Dt:
10/01/2003
Publication #:
Pub Dt:
04/07/2005
Title:
SYSTEM AND METHOD FOR HANDLING EXCEPTIONAL INSTRUCTIONS IN A TRACE CACHE BASED PROCESSOR
47
Patent #:
Issue Dt:
01/16/2007
Application #:
10676600
Filing Dt:
10/01/2003
Title:
FACILITATING COLD RESET AND WARM RESET TASKING IN A COMPUTER SYSTEM
48
Patent #:
Issue Dt:
05/09/2006
Application #:
10676636
Filing Dt:
10/01/2003
Title:
Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
49
Patent #:
Issue Dt:
08/02/2005
Application #:
10683823
Filing Dt:
10/10/2003
Title:
LATCH CIRCUIT WITH METASTABILITY TRAP AND METHOD THEREFOR
50
Patent #:
Issue Dt:
02/27/2007
Application #:
10699667
Filing Dt:
11/04/2003
Title:
FREQUENCY DOMAIN ESTIMATION OF IQ IMBALANCE IN A WIRELESS OFDM DIRECT CONVERSION RECEIVER USING LOOPBACK CONNECTION
51
Patent #:
Issue Dt:
12/30/2008
Application #:
10708316
Filing Dt:
02/24/2004
Publication #:
Pub Dt:
08/25/2005
Title:
Autonomous Self-Monitoring and Corrective Operation of an Integrated Circuit
52
Patent #:
Issue Dt:
10/10/2006
Application #:
10720466
Filing Dt:
11/24/2003
Publication #:
Pub Dt:
05/26/2005
Title:
SINGLE SUPPLY LEVEL CONVERTER
53
Patent #:
Issue Dt:
11/29/2011
Application #:
10726902
Filing Dt:
12/03/2003
Publication #:
Pub Dt:
06/09/2005
Title:
TRANSITIONING FROM INSTRUCTION CACHE TO TRACE CACHE ON LABEL BOUNDARIES
54
Patent #:
Issue Dt:
05/13/2008
Application #:
10755692
Filing Dt:
01/12/2004
Title:
CONTROLLING WRITES TO NON-RENAMED REGISTER SPACE IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR
55
Patent #:
Issue Dt:
04/08/2008
Application #:
10817811
Filing Dt:
04/06/2004
Title:
OFDM RECEIVER HAVING ADAPTIVE CHANNEL ESTIMATOR FOR CORRECTING CHANNEL FADING BASED ON ACCUMULATED PSEUDO POWER VALUES
56
Patent #:
Issue Dt:
03/10/2009
Application #:
10839872
Filing Dt:
05/06/2004
Publication #:
Pub Dt:
11/17/2005
Title:
NETWORK INTERFACE WITH SECURITY ASSOCIATION DATA PREFETCH FOR HIGH SPEED OFFLOADED SECURITY PROCESSING
57
Patent #:
Issue Dt:
05/25/2010
Application #:
10843255
Filing Dt:
05/10/2004
Title:
MEDIA ACCELERATOR INTERFACE API
58
Patent #:
Issue Dt:
04/29/2008
Application #:
10858791
Filing Dt:
06/02/2004
Title:
METHOD FOR OPTIMIZING LOOP CONTROL OF MICROCODED INSTRUCTIONS
59
Patent #:
Issue Dt:
11/02/2010
Application #:
10887069
Filing Dt:
07/08/2004
Title:
DATA PROCESSOR HAVING A CACHE WITH EFFICIENT STORAGE OF PREDECODE INFORMATION, CACHE, AND METHOD
60
Patent #:
Issue Dt:
07/07/2009
Application #:
10932999
Filing Dt:
09/02/2004
Title:
METHOD AND APPARATUS FOR DYNAMIC ADJUSTMENT OF A SENSOR SAMPLING RATE
61
Patent #:
Issue Dt:
11/13/2007
Application #:
10956537
Filing Dt:
10/01/2004
Title:
COMBINED SYSTEM RESPONSES IN A CHIP MULTIPROCESSOR
62
Patent #:
Issue Dt:
08/14/2007
Application #:
10956560
Filing Dt:
10/01/2004
Publication #:
Pub Dt:
04/06/2006
Title:
DYNAMIC RECONFIGURATION OF CACHE MEMORY
63
Patent #:
Issue Dt:
05/23/2006
Application #:
10970266
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
12/01/2005
Title:
DIGITALLY CONTROLLED FILTER TUNING FOR WLAN COMMUNICATION DEVICES
64
Patent #:
Issue Dt:
12/26/2006
Application #:
11033754
Filing Dt:
01/13/2005
Title:
DUAL-MODE OUTPUT DRIVER CONFIGURED FOR OUTPUTTING A SIGNAL ACCORDING TO EITHER A SELECTED HIGH VOLTAGE/LOW SPEED MODE OR A LOW VOLTAGE/HIGH SPEED MODE
65
Patent #:
Issue Dt:
08/14/2007
Application #:
11033755
Filing Dt:
01/13/2005
Title:
ALIGNMENT OF LOCAL TRANSMIT CLOCK TO SYNCHRONOUS DATA TRANSFER CLOCK HAVING PROGRAMMABLE TRANSFER RATE
66
Patent #:
Issue Dt:
11/14/2006
Application #:
11033757
Filing Dt:
01/13/2005
Title:
VOLTAGE MODE TRANSCEIVER HAVING PROGRAMMABLE VOLTAGE SWING AND EXTERNAL REFERENCE-BASED CALIBRATION
67
Patent #:
Issue Dt:
09/07/2010
Application #:
11042218
Filing Dt:
01/25/2005
Publication #:
Pub Dt:
07/27/2006
Title:
SCRATCH PAD FOR STORING INTERMEDIATE LOOP FILTER DATA
68
Patent #:
Issue Dt:
08/26/2008
Application #:
11066752
Filing Dt:
02/25/2005
Title:
EXECUTING SYSTEM MANAGEMENT MODE CODE AS VIRTUAL MACHINE GUEST
69
Patent #:
Issue Dt:
02/28/2012
Application #:
11066873
Filing Dt:
02/25/2005
Title:
VIRTUALIZATION OF REAL MODE EXECUTION
70
Patent #:
Issue Dt:
04/06/2010
Application #:
11076323
Filing Dt:
03/09/2005
Title:
SYSTEM FOR ENABLING AND DISABLING CACHE AND A METHOD THEREOF
71
Patent #:
Issue Dt:
08/16/2011
Application #:
11098153
Filing Dt:
04/04/2005
Publication #:
Pub Dt:
10/05/2006
Title:
SYSTEM FOR SPECULATIVE BRANCH PREDICTION OPTIMIZATION AND METHOD THEREOF
72
Patent #:
Issue Dt:
11/05/2013
Application #:
11098273
Filing Dt:
04/04/2005
Title:
System and method for aligning change-of-flow instructions in an instruction buffer
73
Patent #:
Issue Dt:
06/12/2007
Application #:
11140803
Filing Dt:
05/31/2005
Title:
SERIAL INTERFACE HAVING A READ TEMPERATURE COMMAND
74
Patent #:
Issue Dt:
06/17/2008
Application #:
11146863
Filing Dt:
06/07/2005
Publication #:
Pub Dt:
12/07/2006
Title:
MICROPROCESSOR INCLUDING A CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
75
Patent #:
Issue Dt:
02/02/2010
Application #:
11151318
Filing Dt:
06/14/2005
Title:
CONTROL OF PCI MEMORY READ BEHAVIOR USING MEMORY READ ALIAS AND MEMORY COMMAND REISSUE BITS
76
Patent #:
Issue Dt:
12/09/2008
Application #:
11192153
Filing Dt:
07/28/2005
Title:
USING A SHUFFLE UNIT TO IMPLEMENT SHIFT OPERATIONS IN A PROCESSOR
77
Patent #:
Issue Dt:
12/22/2009
Application #:
11192259
Filing Dt:
07/28/2005
Publication #:
Pub Dt:
02/01/2007
Title:
VERIFIED COMPUTING ENVIRONMENT FOR PERSONAL INTERNET COMMUNICATOR
78
Patent #:
Issue Dt:
06/02/2009
Application #:
11278840
Filing Dt:
04/06/2006
Publication #:
Pub Dt:
10/11/2007
Title:
TIME WEIGHTED MOVING AVERAGE FILTER
79
Patent #:
Issue Dt:
01/01/2008
Application #:
11279981
Filing Dt:
04/17/2006
Title:
COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
80
Patent #:
Issue Dt:
09/18/2007
Application #:
11286454
Filing Dt:
11/23/2005
Title:
DELAY-LOCKED LOOP HAVING A PLURALITY OF LOCK MODES
81
Patent #:
Issue Dt:
09/16/2008
Application #:
11297856
Filing Dt:
12/09/2005
Publication #:
Pub Dt:
06/14/2007
Title:
MEMORY ACCESS REQUEST ARBITRATION
82
Patent #:
Issue Dt:
02/17/2009
Application #:
11316499
Filing Dt:
12/21/2005
Publication #:
Pub Dt:
02/01/2007
Title:
SECURE PATCH INSTALLATION FOR WWAN SYSTEMS
83
Patent #:
Issue Dt:
04/30/2013
Application #:
11317593
Filing Dt:
12/23/2005
Title:
STRIDED BLOCK TRANSFER INSTRUCTION
84
Patent #:
Issue Dt:
02/05/2013
Application #:
11321706
Filing Dt:
12/29/2005
Title:
DATA BLOCK TRANSFER TO CACHE
85
Patent #:
Issue Dt:
08/28/2007
Application #:
11325054
Filing Dt:
01/03/2006
Publication #:
Pub Dt:
07/05/2007
Title:
SYSTEM AND METHOD FOR OPERATING COMPONENTS OF AN INTEGRATED CIRCUIT AT INDEPENDENT FREQUENCIES AND/OR VOLTAGES
86
Patent #:
Issue Dt:
07/14/2009
Application #:
11348136
Filing Dt:
02/06/2006
Title:
METHOD AND APPARATUS FOR CROSSTALK REDUCTION
87
Patent #:
Issue Dt:
06/01/2010
Application #:
11368785
Filing Dt:
03/06/2006
Publication #:
Pub Dt:
09/06/2007
Title:
ASYMMETRIC CONTROL OF HIGH-SPEED BIDIRECTIONAL SIGNALING
88
Patent #:
Issue Dt:
03/17/2009
Application #:
11368792
Filing Dt:
03/06/2006
Title:
SYSTEM FOR PHASE TRACKING AND EQUALIZATION ACROSS A BYTE GROUP FOR ASYMMETRIC CONTROL OF HIGH-SPEED BIDIRECTIONAL SIGNALING
89
Patent #:
Issue Dt:
09/29/2009
Application #:
11379864
Filing Dt:
04/24/2006
Title:
ERROR DETECTION IN A COMMUNICATION LINK
90
Patent #:
Issue Dt:
07/27/2010
Application #:
11385329
Filing Dt:
03/21/2006
Title:
INCREMENTALLY ADJUSTABLE SKEW AND DUTY CYCLE CORRECTION FOR CLOCK SIGNALS WITHIN A CLOCK DISTRIBUTION NETWORK
91
Patent #:
Issue Dt:
06/02/2009
Application #:
11503390
Filing Dt:
08/11/2006
Publication #:
Pub Dt:
02/15/2007
Title:
CONTROLLING AN I/O MMU
92
Patent #:
Issue Dt:
06/29/2010
Application #:
11503700
Filing Dt:
08/14/2006
Publication #:
Pub Dt:
02/14/2008
Title:
SYSTEM AND METHOD FOR LIMITING PROCESSOR PERFORMANCE
93
Patent #:
Issue Dt:
08/24/2010
Application #:
11518843
Filing Dt:
09/11/2006
Publication #:
Pub Dt:
03/13/2008
Title:
SYSTEM FOR CONTROLLING HIGH-SPEED BIDIRECTIONAL COMMUNICATION
94
Patent #:
Issue Dt:
07/22/2008
Application #:
11556882
Filing Dt:
11/06/2006
Publication #:
Pub Dt:
06/05/2008
Title:
CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING
95
Patent #:
Issue Dt:
10/12/2010
Application #:
11557745
Filing Dt:
11/08/2006
Publication #:
Pub Dt:
05/03/2007
Title:
DIGITAL MEASURING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CHIP OPERATING PARAMETERS
96
Patent #:
Issue Dt:
01/18/2011
Application #:
11559049
Filing Dt:
11/13/2006
Publication #:
Pub Dt:
05/15/2008
Title:
FILTERING AND REMAPPING INTERRUPTS
97
Patent #:
Issue Dt:
04/06/2010
Application #:
11590286
Filing Dt:
10/31/2006
Publication #:
Pub Dt:
06/19/2008
Title:
MEMORY CONTROLLER INCLUDING A DUAL-MODE MEMORY INTERCONNECT
98
Patent #:
Issue Dt:
12/28/2010
Application #:
11590290
Filing Dt:
10/31/2006
Publication #:
Pub Dt:
05/01/2008
Title:
MEMORY SYSTEM INCLUDING ASYMMETRIC HIGH-SPEED DIFFERENTIAL MEMORY INTERCONNECT
99
Patent #:
Issue Dt:
11/23/2010
Application #:
11610219
Filing Dt:
12/13/2006
Publication #:
Pub Dt:
06/19/2008
Title:
PARTIAL CRC INSERTION IN DATA PACKETS FOR EARLY FORWARDING
100
Patent #:
Issue Dt:
01/26/2010
Application #:
11623500
Filing Dt:
01/16/2007
Publication #:
Pub Dt:
07/19/2007
Title:
ADDRESS TRANSLATION FOR INPUT/OUTPUT (I/O) DEVICES AND INTERRUPT REMAPPING FOR I/O DEVICES IN AN I/O MEMORY MANAGEMENT UNIT (IOMMU)
Assignor
1
Exec Dt:
12/23/2020
Assignee
1
NO. 1, DUSING 1ST RD. , HSINCHU SCIENCE PARK
HSINCHU CITY, TAIWAN 30078
Correspondence name and address
MCCLURE, QUALEY & RODACK LLP
280 INTERSTATE NORTH CIRCLE
SUITE 550
ATLANTA, GA 30339

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