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Reel/Frame:055468/0023   Pages: 6
Recorded: 03/02/2021
Attorney Dkt #:VARIOUS
Conveyance: MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 48
1
Patent #:
6327687
Issue Dt:
12/04/2001
Application #:
09619985
Filing Dt:
07/20/2000
Title:
Test pattern compression for an integrated circuit test environment
2
Patent #:
6557129
Issue Dt:
04/29/2003
Application #:
09619988
Filing Dt:
07/20/2000
Title:
METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES
3
Patent #:
7493540
Issue Dt:
02/17/2009
Application #:
09620021
Filing Dt:
07/20/2000
Title:
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS TO A CIRCUIT-UNDER-TEST
4
Patent #:
6353842
Issue Dt:
03/05/2002
Application #:
09620023
Filing Dt:
07/20/2000
Title:
Method for synthesizing linear finite state machines
5
Patent #:
6874109
Issue Dt:
03/29/2005
Application #:
09713662
Filing Dt:
11/15/2000
Title:
PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY
6
Patent #:
6684358
Issue Dt:
01/27/2004
Application #:
09713664
Filing Dt:
11/15/2000
Title:
DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS
7
Patent #:
6671843
Issue Dt:
12/30/2003
Application #:
09737620
Filing Dt:
12/14/2000
Title:
METHOD FOR PROVIDING USER DEFINABLE ALGORITHMS IN MEMORY BIST
8
Patent #:
6557160
Issue Dt:
04/29/2003
Application #:
09741698
Filing Dt:
12/19/2000
Publication #:
US20010004764
Pub Dt:
06/21/2001
Title:
CORRELATION OF BEHAVIORAL HDL SIGNALS
9
Patent #:
6415421
Issue Dt:
07/02/2002
Application #:
09747190
Filing Dt:
12/22/2000
Publication #:
US20010052107
Pub Dt:
12/13/2001
Title:
INTEGRATED VERIFICATION AND MANUFACTURABILITY TOOL
10
Patent #:
6611952
Issue Dt:
08/26/2003
Application #:
09839376
Filing Dt:
04/20/2001
Title:
INTERACTIVE MEMORY ALLOCATION IN A BEHAVIORAL SYNTHESIS TOOL
11
Patent #:
6961918
Issue Dt:
11/01/2005
Application #:
09888332
Filing Dt:
06/21/2001
Publication #:
US20020019730
Pub Dt:
02/14/2002
Title:
SYSTEM FOR INTELLECTUAL PROPERTY REUSE IN INTEGRATED CIRCUIT DESIGN
12
Patent #:
7392168
Issue Dt:
06/24/2008
Application #:
09898431
Filing Dt:
07/02/2001
Publication #:
US20020133801
Pub Dt:
09/19/2002
Title:
METHOD OF COMPENSATING FOR ETCH EFFECTS IN PHOTOLITHOGRAPHIC PROCESSING
13
Patent #:
7120879
Issue Dt:
10/10/2006
Application #:
09919650
Filing Dt:
07/31/2001
Publication #:
US20030033039
Pub Dt:
02/13/2003
Title:
HIERARCHICAL PRESENTATION TECHNIQUES FOR A DESIGN TOOL
14
Patent #:
6892252
Issue Dt:
05/10/2005
Application #:
09921741
Filing Dt:
08/01/2001
Publication #:
US20020035656
Pub Dt:
03/21/2002
Title:
ASYMMETRIC DATA PATH MEDIA ACCESS CONTROLLER
15
Patent #:
7099808
Issue Dt:
08/29/2006
Application #:
09957889
Filing Dt:
09/20/2001
Publication #:
US20020116696
Pub Dt:
08/22/2002
Title:
CAPACITANCE AND TRANSMISSION LINE MEASUREMENTS FOR AN INTEGRATED CIRCUIT
16
Patent #:
7069521
Issue Dt:
06/27/2006
Application #:
10160653
Filing Dt:
05/30/2002
Publication #:
US20020149627
Pub Dt:
10/17/2002
Title:
METHOD AND APPARATUS FOR EXPLORING A MULTI-ELEMENT DESIGN THROUGH USER DIRECTED SELECTIVE RENDERING
17
Patent #:
7644333
Issue Dt:
01/05/2010
Application #:
10194377
Filing Dt:
07/12/2002
Publication #:
US20030115525
Pub Dt:
06/19/2003
Title:
RESTARTABLE LOGIC BIST CONTROLLER
18
Patent #:
6934897
Issue Dt:
08/23/2005
Application #:
10210794
Filing Dt:
07/31/2002
Publication #:
US20030191996
Pub Dt:
10/09/2003
Title:
SCHEDULING THE CONCURRENT TESTING OF MULTIPLE CORES EMBEDDED IN AN INTEGRATED CIRCUIT
19
Patent #:
6711718
Issue Dt:
03/23/2004
Application #:
10269525
Filing Dt:
10/10/2002
Publication #:
US20030131326
Pub Dt:
07/10/2003
Title:
PARALLEL ELECTRONIC DESIGN AUTOMATION: DISTRIBUTED SIMULTANEOUS EDITING
20
Patent #:
6708313
Issue Dt:
03/16/2004
Application #:
10269614
Filing Dt:
10/10/2002
Publication #:
US20030131332
Pub Dt:
07/10/2003
Title:
PARALLEL ELECTRONIC DESIGN AUTOMATION: SHARED SIMULTANEOUS EDITING
21
Patent #:
7013442
Issue Dt:
03/14/2006
Application #:
10293900
Filing Dt:
11/12/2002
Publication #:
US20030131334
Pub Dt:
07/10/2003
Title:
SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS
22
Patent #:
7062734
Issue Dt:
06/13/2006
Application #:
10319018
Filing Dt:
12/12/2002
Publication #:
US20030192020
Pub Dt:
10/09/2003
Title:
SLACK TIME ANALYSIS THROUGH LATCHES ON A CIRCUIT DESIGN
23
Patent #:
7013439
Issue Dt:
03/14/2006
Application #:
10356382
Filing Dt:
01/31/2003
Publication #:
US20040005089
Pub Dt:
01/08/2004
Title:
CONTRAST BASED RESOLUTION ENHANCING TECHNOLOGY
24
Patent #:
7310787
Issue Dt:
12/18/2007
Application #:
10383274
Filing Dt:
03/07/2003
Publication #:
US20030172055
Pub Dt:
09/11/2003
Title:
ARRAY TRANSFORMATION IN A BEHAVIORAL SYNTHESIS TOOL.
25
Patent #:
6928634
Issue Dt:
08/09/2005
Application #:
10387224
Filing Dt:
03/10/2003
Publication #:
US20040133871
Pub Dt:
07/08/2004
Title:
MATRIX OPTICAL PROCESS CORRECTION
26
Patent #:
6817003
Issue Dt:
11/09/2004
Application #:
10402079
Filing Dt:
03/26/2003
Publication #:
US20030189863
Pub Dt:
10/09/2003
Title:
SHORT EDGE MANAGEMENT IN RULE BASED OPC
27
Patent #:
7239996
Issue Dt:
07/03/2007
Application #:
10447762
Filing Dt:
05/28/2003
Publication #:
US20030229483
Pub Dt:
12/11/2003
Title:
CAUSALITY BASED EVENT DRIVEN TIMING ANALYSIS ENGINE
28
Patent #:
6799313
Issue Dt:
09/28/2004
Application #:
10453959
Filing Dt:
06/04/2003
Publication #:
US20030208742
Pub Dt:
11/06/2003
Title:
SPACE CLASSIFICATION FOR RESOLUTION ENHANCEMENT TECHNIQUES
29
Patent #:
7386833
Issue Dt:
06/10/2008
Application #:
10653998
Filing Dt:
09/04/2003
Publication #:
US20040044514
Pub Dt:
03/04/2004
Title:
POLYMORPHIC COMPUTATIONAL SYSTEM AND METHOD IN SIGNALS INTELLIGENCE ANALYSIS
30
Patent #:
7143377
Issue Dt:
11/28/2006
Application #:
10701598
Filing Dt:
11/06/2003
Title:
FUNCTIONAL VERIFICATION OF LOGIC AND MEMORY CIRCUITS WITH MULTIPLE ASYNCHRONOUS DOMAINS
31
Patent #:
7240321
Issue Dt:
07/03/2007
Application #:
10730765
Filing Dt:
12/08/2003
Publication #:
US20040230936
Pub Dt:
11/18/2004
Title:
SELECTIVE PROMOTION FOR RESOLUTION ENHANCEMENT TECHNIQUES
32
Patent #:
7305633
Issue Dt:
12/04/2007
Application #:
10736908
Filing Dt:
12/17/2003
Publication #:
US20040260530
Pub Dt:
12/23/2004
Title:
DISTRIBUTED CONFIGURATION OF INTEGRATED CIRCUITS IN AN EMULATION SYSTEM
33
Patent #:
7502976
Issue Dt:
03/10/2009
Application #:
10779205
Filing Dt:
02/13/2004
Publication #:
US20040190331
Pub Dt:
09/30/2004
Title:
TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT
34
Patent #:
7174531
Issue Dt:
02/06/2007
Application #:
10811418
Filing Dt:
03/26/2004
Publication #:
US20040230937
Pub Dt:
11/18/2004
Title:
CREATING PHOTOLITHOGRAPHIC MASKS
35
Patent #:
7587695
Issue Dt:
09/08/2009
Application #:
10869923
Filing Dt:
06/18/2004
Publication #:
US20040225988
Pub Dt:
11/11/2004
Title:
PROTECTION BOUNDARIES IN A PARALLEL PRINTED CIRCUIT BOARD DESIGN ENVIRONMENT
36
Patent #:
7318205
Issue Dt:
01/08/2008
Application #:
11006238
Filing Dt:
12/06/2004
Publication #:
US20050081169
Pub Dt:
04/14/2005
Title:
MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING
37
Patent #:
7281234
Issue Dt:
10/09/2007
Application #:
11040195
Filing Dt:
01/20/2005
Publication #:
US20050208396
Pub Dt:
09/22/2005
Title:
SHORT EDGE SMOOTHING FOR ENHANCED SCATTER BAR PLACEMENT
38
Patent #:
7412675
Issue Dt:
08/12/2008
Application #:
11202935
Filing Dt:
08/12/2005
Publication #:
US20060059443
Pub Dt:
03/16/2006
Title:
HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION
39
Patent #:
7237168
Issue Dt:
06/26/2007
Application #:
11231562
Filing Dt:
09/20/2005
Publication #:
US20060090113
Pub Dt:
04/27/2006
Title:
DESIGN FOR TEST OF ANALOG MODULE SYSTEMS
40
Patent #:
7607117
Issue Dt:
10/20/2009
Application #:
11295107
Filing Dt:
12/05/2005
Publication #:
US20060085779
Pub Dt:
04/20/2006
Title:
REPRESENTING DEVICE LAYOUT USING TREE STRUCTURE
41
Patent #:
7716624
Issue Dt:
05/11/2010
Application #:
11438031
Filing Dt:
05/19/2006
Publication #:
US20060236299
Pub Dt:
10/19/2006
Title:
MASK CREATION WITH HIERARCHY MANAGEMENT USING COVER CELLS
42
Patent #:
7823001
Issue Dt:
10/26/2010
Application #:
11553532
Filing Dt:
10/27/2006
Publication #:
US20070045789
Pub Dt:
03/01/2007
Title:
LATENCY ADJUSTMENT BETWEEN INTEGRATED CIRCUIT CHIPS
43
Patent #:
8250537
Issue Dt:
08/21/2012
Application #:
11613160
Filing Dt:
12/19/2006
Publication #:
US20070168986
Pub Dt:
07/19/2007
Title:
FLEXIBLE HORIZONTAL STACK DISPLAY AND EDITOR
44
Patent #:
7640524
Issue Dt:
12/29/2009
Application #:
11876652
Filing Dt:
10/22/2007
Publication #:
US20080046855
Pub Dt:
02/21/2008
Title:
CONNECTIVITY-BASED SYMBOL GENERATION IN WIRING DIAGRAMS
45
Patent #:
7747973
Issue Dt:
06/29/2010
Application #:
11969650
Filing Dt:
01/04/2008
Publication #:
US20080104564
Pub Dt:
05/01/2008
Title:
CLUSTERING CIRCUIT PATHS IN ELECTRONIC CIRCUIT DESIGN
46
Patent #:
7882478
Issue Dt:
02/01/2011
Application #:
12039389
Filing Dt:
02/28/2008
Publication #:
US20080235646
Pub Dt:
09/25/2008
Title:
SPACERS FOR REDUCING CROSSTALK AND MAINTAINING CLEARANCES
47
Patent #:
8046209
Issue Dt:
10/25/2011
Application #:
12116888
Filing Dt:
05/07/2008
Publication #:
US20080215304
Pub Dt:
09/04/2008
Title:
COHERENT STATE AMONG MULTIPLE SIMULATION MODELS IN AN EDA SIMULATION ENVIRONMENT
48
Patent #:
9740506
Issue Dt:
08/22/2017
Application #:
12772013
Filing Dt:
04/30/2010
Publication #:
US20100281457
Pub Dt:
11/04/2010
Title:
AUTOMATING INTERACTIONS WITH SOFTWARE USER INTERFACES
Assignor
1
MENTOR GRAPHICS CORPORATION
Exec Dt:
12/30/2020
Newly Merged Entity Data
1
SIEMENS INDUSTRY SOFTWARE INC.
Exec Dt:
12/30/2020
Newly Merged Entity's New Name
1
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600
PLANO, TEXAS 75024
Correspondence name and address
SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
3850 QUADRANGLE BOULEVARD
ORLANDO, FL 32817

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