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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:055883/0078   Pages: 5
Recorded: 04/09/2021
Attorney Dkt #:VARIOUS
Conveyance: MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 15
1
Patent #:
Issue Dt:
05/12/2015
Application #:
13938046
Filing Dt:
07/09/2013
Publication #:
Pub Dt:
01/09/2014
Title:
PRIORITISING EVENT DATA OVER CONFIGURATION DATA IN A SINGLE INTERFACE IN A SOC/DEBUG ARCHITECTURE
2
Patent #:
Issue Dt:
12/22/2015
Application #:
13938053
Filing Dt:
07/09/2013
Publication #:
Pub Dt:
01/09/2014
Title:
DEBUG ARCHITECTURE
3
Patent #:
Issue Dt:
04/07/2015
Application #:
13938065
Filing Dt:
07/09/2013
Publication #:
Pub Dt:
01/09/2014
Title:
DEBUG ARCHITECTURE
4
Patent #:
Issue Dt:
11/03/2015
Application #:
13938077
Filing Dt:
07/09/2013
Publication #:
Pub Dt:
01/09/2014
Title:
DEBUG ARCHITECTURE
5
Patent #:
Issue Dt:
05/05/2015
Application #:
13938088
Filing Dt:
07/09/2013
Publication #:
Pub Dt:
01/09/2014
Title:
PRIORITIZING TRANSPORT OF DEBUG DATA ON AN INTEGRATED CIRCUIT CHIP BY DATA TYPE
6
Patent #:
Issue Dt:
07/11/2017
Application #:
13938098
Filing Dt:
07/09/2013
Publication #:
Pub Dt:
01/09/2014
Title:
DEBUG ARCHITECTURE
7
Patent #:
Issue Dt:
11/17/2015
Application #:
14251044
Filing Dt:
04/11/2014
Publication #:
Pub Dt:
08/13/2015
Title:
Functional Testing of an Integrated Circuit Chip
8
Patent #:
Issue Dt:
09/22/2015
Application #:
14251157
Filing Dt:
04/11/2014
Publication #:
Pub Dt:
08/13/2015
Title:
Monitoring Functional Testing of an Integrated Circuit Chip
9
Patent #:
Issue Dt:
08/23/2016
Application #:
14251260
Filing Dt:
04/11/2014
Publication #:
Pub Dt:
09/24/2015
Title:
Routing Debug Messages
10
Patent #:
Issue Dt:
11/20/2018
Application #:
14843745
Filing Dt:
09/02/2015
Publication #:
Pub Dt:
12/31/2015
Title:
DEBUG ARCHITECTURE
11
Patent #:
Issue Dt:
04/25/2017
Application #:
14879597
Filing Dt:
10/09/2015
Publication #:
Pub Dt:
02/04/2016
Title:
Functional Testing of an Integrated Circuit Chip
12
Patent #:
Issue Dt:
03/27/2018
Application #:
15241805
Filing Dt:
08/19/2016
Publication #:
Pub Dt:
12/08/2016
Title:
DEBUG ARCHITECTURE
13
Patent #:
Issue Dt:
08/27/2019
Application #:
15365686
Filing Dt:
11/30/2016
Publication #:
Pub Dt:
06/01/2017
Title:
INTEGRATED CIRCUIT SECURITY
14
Patent #:
Issue Dt:
03/27/2018
Application #:
15617953
Filing Dt:
06/08/2017
Publication #:
Pub Dt:
09/28/2017
Title:
DEBUG ARCHITECTURE
15
Patent #:
Issue Dt:
01/21/2020
Application #:
15906730
Filing Dt:
02/27/2018
Publication #:
Pub Dt:
07/05/2018
Title:
Reconfiguring Debug Circuitry
Assignor
1
Exec Dt:
12/30/2020
Newly Merged Entity Data
1
Exec Dt:
12/30/2020
Newly Merged Entity's New Name
1
5800 GRANITE PARKWAY, SUITE 600
PLANO, TEXAS 75024
Correspondence name and address
SIEMENS CORPORATION
INTELLECTUAL PROPERTY DEPT
3850 QUADRANGLE BLVD
ORLANDO, FL 32817

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