Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 056055/0389 | |
| Pages: | 7 |
| | Recorded: | 04/27/2021 | | |
Attorney Dkt #: | RA488 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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06/01/2021
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Application #:
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16665179
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Filing Dt:
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10/28/2019
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Publication #:
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Pub Dt:
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04/23/2020
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Title:
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Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal
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Patent #:
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Issue Dt:
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12/13/2022
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Application #:
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17241660
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Filing Dt:
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04/27/2021
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Publication #:
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Pub Dt:
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10/14/2021
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Title:
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Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement
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Assignee
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4453 N FIRST STREET, SUITE 100 |
SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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MARC P. SCHUYLER
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PO BOX 2535
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SARATOGA, CA 95070
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05/12/2024 05:07 PM
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